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| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index e0be784329..9a0111d9d8 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -129,9 +129,6 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; }]; - // FIXME: We are reserving r12 in case the PEI needs to use it to - // generate large stack offset. Make it available once we have register - // scavenging. Similarly r3 is reserved in Thumb mode for now. let MethodBodies = [{ // FP is R11, R9 is available. static const unsigned ARM_GPR_AO_1[] = { |