diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index c609ee6174..6884e0001c 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -288,7 +288,7 @@ def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), // Conditional code operand for conditional branches and conditional moves. // No AlwaysVal value. -def ccop : ImmutablePredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> { +def ccop : PredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> { let PrintMethod = "printPredicateOperand"; } diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 4ffde0a97f..fe18978400 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -272,8 +272,8 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg // that doesn't matter. -def pred : ImmutablePredicateOperand<OtherVT, (ops imm, CRRC), - (ops (i32 20), CR0)> { +def pred : PredicateOperand<OtherVT, (ops imm, CRRC), + (ops (i32 20), CR0)> { let PrintMethod = "printPredicateOperand"; } |