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authorEvan Cheng <evan.cheng@apple.com>2007-07-06 23:22:46 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-07-06 23:22:46 +0000
commit06aae67b8315aa915f55abd5927453dbe8b11169 (patch)
tree7629eeefe0d01d8b46c301efd26cdf53cbdcca0d
parent14c46554039ac26c431d72725663409eeab864ae (diff)
Do away with ImmutablePredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td2
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.td4
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index c609ee6174..6884e0001c 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -288,7 +288,7 @@ def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
// Conditional code operand for conditional branches and conditional moves.
// No AlwaysVal value.
-def ccop : ImmutablePredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
+def ccop : PredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
let PrintMethod = "printPredicateOperand";
}
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 4ffde0a97f..fe18978400 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -272,8 +272,8 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
// that doesn't matter.
-def pred : ImmutablePredicateOperand<OtherVT, (ops imm, CRRC),
- (ops (i32 20), CR0)> {
+def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
+ (ops (i32 20), CR0)> {
let PrintMethod = "printPredicateOperand";
}