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-rw-r--r--lib/Target/ARM/ARMInstrInfo.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 3e3b0eeb6c..c609ee6174 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -292,10 +292,10 @@ def ccop : ImmutablePredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
let PrintMethod = "printPredicateOperand";
}
-// Conditional code result for cmp, etc.
+// Conditional code result for instructions whose 's' bit is set, e.g. subs.
//
-def cc_out : PredicateDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
- let PrintMethod = "printPredicateOperand";
+def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
+ let PrintMethod = "printSBitModifierOperand";
}
//===----------------------------------------------------------------------===//