diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 06096a74dc..1a930dcd64 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -182,7 +182,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); // We can custom expand all VECTOR_SHUFFLEs to VPERM. - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); @@ -192,8 +192,12 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); + + setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); } + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); + addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); |