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| author | Chris Lattner <sabre@nondot.org> | 2006-04-03 23:55:43 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-04-03 23:55:43 +0000 |
| commit | 01cae0799dd4a43c02edc3b5e08e9010ac4ae459 (patch) | |
| tree | f5315bb2e674891c28e08c7278f5db117ceb9dd8 | |
| parent | 97ac5fadb7e6fb39af672c5f4a51890d7b517a0f (diff) | |
Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27385 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 06096a74dc..1a930dcd64 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -182,7 +182,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); // We can custom expand all VECTOR_SHUFFLEs to VPERM. - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); @@ -192,8 +192,12 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); + + setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); } + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); + addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); |