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authorBill Wendling <isanbard@gmail.com>2010-10-12 23:22:27 +0000
committerBill Wendling <isanbard@gmail.com>2010-10-12 23:22:27 +0000
commitcaa3d467ab849ebf671441f3adf1ecda715e98fe (patch)
tree36ca31f03e0cfcb5f5fa6d27b2e3611ce1650f76 /test
parent3f490f3469dd30b47d7b59a9b84750c31dc19633 (diff)
Add encodings for VDIV and VMUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/MC/ARM/simple-fp-encoding.ll38
1 files changed, 35 insertions, 3 deletions
diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll
index 88bf8be638..136c9cb043 100644
--- a/test/MC/ARM/simple-fp-encoding.ll
+++ b/test/MC/ARM/simple-fp-encoding.ll
@@ -38,17 +38,49 @@ entry:
ret float %sub
}
-define i1 @f5(double %a, double %b) nounwind readnone {
+define double @f5(double %a, double %b) nounwind readnone {
entry:
; CHECK: f5
+; CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
+ %div = fdiv double %a, %b
+ ret double %div
+}
+
+define float @f6(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f6
+; CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
+ %div = fdiv float %a, %b
+ ret float %div
+}
+
+define double @f7(double %a, double %b) nounwind readnone {
+entry:
+; CHECK: f7
+; CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
+ %mul = fmul double %a, %b
+ ret double %mul
+}
+
+define float @f8(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f8
+; CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
+ %mul = fmul float %a, %b
+ ret float %mul
+}
+
+define i1 @f100(double %a, double %b) nounwind readnone {
+entry:
+; CHECK: f100
; CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
%cmp = fcmp oeq double %a, %b
ret i1 %cmp
}
-define i1 @f6(float %a, float %b) nounwind readnone {
+define i1 @f101(float %a, float %b) nounwind readnone {
entry:
-; CHECK: f6
+; CHECK: f101
; CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
%cmp = fcmp oeq float %a, %b
ret i1 %cmp