Add encodings for VDIV and VMUL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 69 insertions, 15 deletions

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index e233b45306..98c5f51202 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -158,6 +158,24 @@ class ADbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
   let Inst{22}    = Dd{4};
 }
 
+class ASbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
+                  dag iops, InstrItinClass itin, string opc, string asm,
+                  list<dag> pattern>
+  : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
+  // Instruction operands.
+  bits<5> Sd;
+  bits<5> Sn;
+  bits<5> Sm;
+
+  // Encode instruction operands.
+  let Inst{3-0}   = Sm{4-1};
+  let Inst{5}     = Sm{0};
+  let Inst{19-16} = Sn{4-1};
+  let Inst{7}     = Sn{0};
+  let Inst{15-12} = Sd{4-1};
+  let Inst{22}    = Sd{0};
+}
+
 class ASbIn_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
                    dag iops, InstrItinClass itin, string opc, string asm,
                    list<dag> pattern>
@@ -201,21 +219,25 @@ def VSUBS  : ASbIn_Encode<0b11100, 0b11, 1, 0,
                           IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
                           [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>;
 
-def VDIVD  : ADbI<0b11101, 0b00, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
-                 IIC_fpDIV64, "vdiv", ".f64\t$dst, $a, $b",
-                 [(set DPR:$dst, (fdiv DPR:$a, (f64 DPR:$b)))]>;
+def VDIVD  : ADbI_Encode<0b11101, 0b00, 0, 0,
+                         (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
+                         IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
+                         [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
 
-def VDIVS  : ASbI<0b11101, 0b00, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
-                 IIC_fpDIV32, "vdiv", ".f32\t$dst, $a, $b",
-                 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
+def VDIVS  : ASbI_Encode<0b11101, 0b00, 0, 0,
+                         (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
+                         IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
+                         [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
 
-def VMULD  : ADbI<0b11100, 0b10, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
-                 IIC_fpMUL64, "vmul", ".f64\t$dst, $a, $b",
-                 [(set DPR:$dst, (fmul DPR:$a, (f64 DPR:$b)))]>;
+def VMULD  : ADbI_Encode<0b11100, 0b10, 0, 0,
+                         (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
+                         IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
+                         [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
 
-def VMULS  : ASbIn<0b11100, 0b10, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
-                  IIC_fpMUL32, "vmul", ".f32\t$dst, $a, $b",
-                  [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
+def VMULS  : ASbIn_Encode<0b11100, 0b10, 0, 0,
+                          (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
+                          IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
+                          [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>;
 
 def VNMULD  : ADbI<0b11100, 0b10, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
                   IIC_fpMUL64, "vnmul", ".f64\t$dst, $a, $b",
diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll
index 88bf8be638..136c9cb043 100644
--- a/test/MC/ARM/simple-fp-encoding.ll
+++ b/test/MC/ARM/simple-fp-encoding.ll
@@ -38,17 +38,49 @@ entry:
   ret float %sub
 }
 
-define i1 @f5(double %a, double %b) nounwind readnone {
+define double @f5(double %a, double %b) nounwind readnone {
 entry:
 ; CHECK: f5
+; CHECK: vdiv.f64 d16, d17, d16  @ encoding: [0xa0,0x0b,0xc1,0xee]
+  %div = fdiv double %a, %b
+  ret double %div
+}
+
+define float @f6(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f6
+; CHECK: vdiv.f32 s0, s1, s0  @ encoding: [0x80,0x0a,0x80,0xee]
+  %div = fdiv float %a, %b
+  ret float %div
+}
+
+define double @f7(double %a, double %b) nounwind readnone {
+entry:
+; CHECK: f7
+; CHECK: vmul.f64 d16, d17, d16  @ encoding: [0xa0,0x0b,0x61,0xee]
+  %mul = fmul double %a, %b
+  ret double %mul
+}
+
+define float @f8(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f8
+; CHECK: vmul.f32 s0, s1, s0  @ encoding: [0x80,0x0a,0x20,0xee]
+  %mul = fmul float %a, %b
+  ret float %mul
+}
+
+define i1 @f100(double %a, double %b) nounwind readnone {
+entry:
+; CHECK: f100
 ; CHECK: vcmpe.f64 d17, d16  @ encoding: [0xe0,0x1b,0xf4,0xee]
   %cmp = fcmp oeq double %a, %b
   ret i1 %cmp
 }
 
-define i1 @f6(float %a, float %b) nounwind readnone {
+define i1 @f101(float %a, float %b) nounwind readnone {
 entry:
-; CHECK: f6
+; CHECK: f101
 ; CHECK: vcmpe.f32 s1, s0  @ encoding: [0xc0,0x0a,0xf4,0xee]
   %cmp = fcmp oeq float %a, %b
   ret i1 %cmp