diff options
| author | Chris Lattner <sabre@nondot.org> | 2002-12-01 23:24:58 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2002-12-01 23:24:58 +0000 |
| commit | a4978ccbcbc64b35e909d067bfd48f6750ecaccd (patch) | |
| tree | 678290434cc6cc534d97fe0da631a2bb7bc9e9c8 /lib | |
| parent | c2505985ceb78fb5f82e4b66e25e498786ccbd0a (diff) | |
Don't add implicit regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4840 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/InstSelectSimple.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelSimple.cpp | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 992fba72ca..d9facda10e 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -502,7 +502,7 @@ void ISel::visitDivRem(BinaryOperator &I) { if (isSigned) { // Emit a sign extension instruction... - BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg); + BuildMI(BB, ExtOpcode[Class], 0); } else { // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 992fba72ca..d9facda10e 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -502,7 +502,7 @@ void ISel::visitDivRem(BinaryOperator &I) { if (isSigned) { // Emit a sign extension instruction... - BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg); + BuildMI(BB, ExtOpcode[Class], 0); } else { // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); |