Fix FastISel's assumption that i1 values are always zero-extended

by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 4 insertions, 2 deletions

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index d6cdc3fb64..50f1935dcd 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -671,12 +671,14 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
 }
 
 bool X86FastISel::X86SelectZExt(Instruction *I) {
-  // Special-case hack: The only i1 values we know how to produce currently
-  // set the upper bits of an i8 value to zero.
+  // Handle zero-extension from i1 to i8, which is common.
   if (I->getType() == Type::Int8Ty &&
       I->getOperand(0)->getType() == Type::Int1Ty) {
     unsigned ResultReg = getRegForValue(I->getOperand(0));
     if (ResultReg == 0) return false;
+    // Set the high bits to zero.
+    ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
+    if (ResultReg == 0) return false;
     UpdateValueMap(I, ResultReg);
     return true;
   }