Fix FastISel's assumption that i1 values are always zero-extended

by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 18 insertions, 3 deletions

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 229376d293..3523dda97e 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -497,7 +497,14 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
   if (!InputReg)
     // Unhandled operand.  Halt "fast" selection and bail.
     return false;
-    
+
+  // If the operand is i1, arrange for the high bits in the register to be zero.
+  if (I->getOperand(0)->getType() == Type::Int1Ty) {
+   InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
+   if (!InputReg)
+     return false;
+  }
+
   unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
                                   DstVT.getSimpleVT(),
                                   Opcode,
@@ -970,3 +977,9 @@ unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
   }
   return ResultReg;
 }
+
+/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
+/// with all but the least significant bit set to zero.
+unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
+  return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
+}
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index d6cdc3fb64..50f1935dcd 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -671,12 +671,14 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
 }
 
 bool X86FastISel::X86SelectZExt(Instruction *I) {
-  // Special-case hack: The only i1 values we know how to produce currently
-  // set the upper bits of an i8 value to zero.
+  // Handle zero-extension from i1 to i8, which is common.
   if (I->getType() == Type::Int8Ty &&
       I->getOperand(0)->getType() == Type::Int1Ty) {
     unsigned ResultReg = getRegForValue(I->getOperand(0));
     if (ResultReg == 0) return false;
+    // Set the high bits to zero.
+    ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
+    if (ResultReg == 0) return false;
     UpdateValueMap(I, ResultReg);
     return true;
   }