diff options
| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-10 22:47:03 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-10 22:47:03 +0000 |
| commit | 5b5708106e409d2b8bb23335f7de8dda361dca3e (patch) | |
| tree | 9f4d60975d44f6ecfa27a0e1e31f741b230601e5 /lib/Target/PowerPC/PowerPCInstrInfo.cpp | |
| parent | 698fbd5b940c7ea0b3855499c879a465385f6f52 (diff) | |
Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15631 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PowerPCInstrInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PowerPCInstrInfo.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/PowerPC/PowerPCInstrInfo.cpp b/lib/Target/PowerPC/PowerPCInstrInfo.cpp index ba14b36baf..17b0989e1f 100644 --- a/lib/Target/PowerPC/PowerPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PowerPCInstrInfo.cpp @@ -26,32 +26,32 @@ bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, unsigned& destReg) const { MachineOpCode oc = MI.getOpcode(); - if (oc == PPC32::OR) { // or r1, r2, r2 + if (oc == PPC::OR) { // or r1, r2, r2 assert(MI.getNumOperands() == 3 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && MI.getOperand(2).isRegister() && - "invalid PPC32 OR instruction!"); + "invalid PPC OR instruction!"); if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { sourceReg = MI.getOperand(1).getReg(); destReg = MI.getOperand(0).getReg(); return true; } - } else if (oc == PPC32::ADDI) { // addi r1, r2, 0 + } else if (oc == PPC::ADDI) { // addi r1, r2, 0 assert(MI.getNumOperands() == 3 && MI.getOperand(0).isRegister() && MI.getOperand(2).isImmediate() && - "invalid PPC32 ADDI instruction!"); + "invalid PPC ADDI instruction!"); if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) { sourceReg = MI.getOperand(1).getReg(); destReg = MI.getOperand(0).getReg(); return true; } - } else if (oc == PPC32::FMR) { // fmr r1, r2 + } else if (oc == PPC::FMR) { // fmr r1, r2 assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && - "invalid PPC32 FMR instruction"); + "invalid PPC FMR instruction"); sourceReg = MI.getOperand(1).getReg(); destReg = MI.getOperand(0).getReg(); return true; |