Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15631 91177308-0d34-0410-b5e6-96231b3b80d8

12 files changed, 879 insertions, 879 deletions

diff --git a/lib/Target/PowerPC/PPC32AsmPrinter.cpp b/lib/Target/PowerPC/PPC32AsmPrinter.cpp
index 8f41683c5a..b52f055c8c 100644
--- a/lib/Target/PowerPC/PPC32AsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPC32AsmPrinter.cpp
@@ -478,16 +478,16 @@ void Printer::printOp(const MachineOperand &MO,
 
 void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
   int Imm = MO.getImmedValue();
-  if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
+  if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) {
     O << (short)Imm;
-  } else if (ArgType == PPC32II::Zimm16) {
+  } else if (ArgType == PPCII::Zimm16) {
     O << (unsigned short)Imm;
   } else {
     O << Imm;
   }
 }
 
-/// printMachineInstruction -- Print out a single PPC32 LLVM instruction
+/// printMachineInstruction -- Print out a single PPC LLVM instruction
 /// MI in Darwin syntax to the current output stream.
 ///
 void Printer::printMachineInstruction(const MachineInstr *MI) {
@@ -498,15 +498,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
 
   unsigned ArgCount = MI->getNumOperands();
   unsigned ArgType[] = {
-    (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
-    (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
-    (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
-    (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask,
-    (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask
+    (Desc.TSFlags >> PPCII::Arg0TypeShift) & PPCII::ArgTypeMask,
+    (Desc.TSFlags >> PPCII::Arg1TypeShift) & PPCII::ArgTypeMask,
+    (Desc.TSFlags >> PPCII::Arg2TypeShift) & PPCII::ArgTypeMask,
+    (Desc.TSFlags >> PPCII::Arg3TypeShift) & PPCII::ArgTypeMask,
+    (Desc.TSFlags >> PPCII::Arg4TypeShift) & PPCII::ArgTypeMask
   };
-  assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
+  assert(((Desc.TSFlags & PPCII::VMX) == 0) &&
          "Instruction requires VMX support");
-  assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
+  assert(((Desc.TSFlags & PPCII::PPC64) == 0) &&
          "Instruction requires 64 bit support");
   ++EmittedInsts;
 
@@ -514,27 +514,27 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
   // appropriate number of args that the assembler expects.  This is because
   // may have many arguments appended to record the uses of registers that are
   // holding arguments to the called function.
-  if (Opcode == PPC32::COND_BRANCH) {
+  if (Opcode == PPC::COND_BRANCH) {
     std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
     abort();
-  } else if (Opcode == PPC32::IMPLICIT_DEF) {
+  } else if (Opcode == PPC::IMPLICIT_DEF) {
     O << "; IMPLICIT DEF ";
     printOp(MI->getOperand(0));
     O << "\n";
     return;
-  } else if (Opcode == PPC32::CALLpcrel) {
+  } else if (Opcode == PPC::CALLpcrel) {
     O << TII.getName(Opcode) << " ";
     printOp(MI->getOperand(0));
     O << "\n";
     return;
-  } else if (Opcode == PPC32::CALLindirect) {
+  } else if (Opcode == PPC::CALLindirect) {
     O << TII.getName(Opcode) << " ";
     printImmOp(MI->getOperand(0), ArgType[0]);
     O << ", ";
     printImmOp(MI->getOperand(1), ArgType[0]);
     O << "\n";
     return;
-  } else if (Opcode == PPC32::MovePCtoLR) {
+  } else if (Opcode == PPC::MovePCtoLR) {
     // FIXME: should probably be converted to cout.width and cout.fill
     O << "bl \"L0000" << LabelNumber << "$pb\"\n";
     O << "\"L0000" << LabelNumber << "$pb\":\n";
@@ -545,34 +545,34 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
   }
 
   O << TII.getName(Opcode) << " ";
-  if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
+  if (Opcode == PPC::LOADLoDirect || Opcode == PPC::LOADLoIndirect) {
     printOp(MI->getOperand(0));
     O << ", lo16(";
     printOp(MI->getOperand(2));
     O << "-\"L0000" << LabelNumber << "$pb\")";
     O << "(";
-    if (MI->getOperand(1).getReg() == PPC32::R0)
+    if (MI->getOperand(1).getReg() == PPC::R0)
       O << "0";
     else
       printOp(MI->getOperand(1));
     O << ")\n";
-  } else if (Opcode == PPC32::LOADHiAddr) {
+  } else if (Opcode == PPC::LOADHiAddr) {
     printOp(MI->getOperand(0));
     O << ", ";
-    if (MI->getOperand(1).getReg() == PPC32::R0)
+    if (MI->getOperand(1).getReg() == PPC::R0)
       O << "0";
     else
       printOp(MI->getOperand(1));
     O << ", ha16(" ;
     printOp(MI->getOperand(2));
      O << "-\"L0000" << LabelNumber << "$pb\")\n";
-  } else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
+  } else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) {
     printOp(MI->getOperand(0));
     O << ", ";
     printImmOp(MI->getOperand(1), ArgType[1]);
     O << "(";
     if (MI->getOperand(2).hasAllocatedReg() &&
-        MI->getOperand(2).getReg() == PPC32::R0)
+        MI->getOperand(2).getReg() == PPC::R0)
       O << "0";
     else
       printOp(MI->getOperand(2));
@@ -580,9 +580,9 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
   } else {
     for (i = 0; i < ArgCount; ++i) {
       // addi and friends
-      if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 &&
+      if (i == 1 && ArgCount == 3 && ArgType[2] == PPCII::Simm16 &&
           MI->getOperand(1).hasAllocatedReg() && 
-          MI->getOperand(1).getReg() == PPC32::R0) {
+          MI->getOperand(1).getReg() == PPC::R0) {
         O << "0";
       // for long branch support, bc $+8
       } else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 96d83799f6..5d438e7ca2 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -443,7 +443,7 @@ unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
   } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
     unsigned Reg = makeAnotherReg(V->getType());
     unsigned FI = getFixedSizedAllocaFI(AI);
-    addFrameReference(BuildMI(*MBB, IPt, PPC32::ADDI, 2, Reg), FI, 0, false);
+    addFrameReference(BuildMI(*MBB, IPt, PPC::ADDI, 2, Reg), FI, 0, false);
     return Reg;
   }
 
@@ -530,13 +530,13 @@ void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
     MachineBasicBlock &FirstMBB = F->front();
     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
     GlobalBaseReg = makeAnotherReg(Type::IntTy);
-    BuildMI(FirstMBB, MBBI, PPC32::IMPLICIT_DEF, 0, PPC32::LR);
-    BuildMI(FirstMBB, MBBI, PPC32::MovePCtoLR, 0, GlobalBaseReg);
+    BuildMI(FirstMBB, MBBI, PPC::IMPLICIT_DEF, 0, PPC::LR);
+    BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, GlobalBaseReg);
     GlobalBaseInitialized = true;
   }
   // Emit our copy of GlobalBaseReg to the destination register in the
   // current MBB
-  BuildMI(*MBB, IP, PPC32::OR, 2, R).addReg(GlobalBaseReg)
+  BuildMI(*MBB, IP, PPC::OR, 2, R).addReg(GlobalBaseReg)
     .addReg(GlobalBaseReg);
 }
 
@@ -578,7 +578,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
 
     // Handle bool
     if (C->getType() == Type::BoolTy) {
-      BuildMI(*MBB, IP, PPC32::LI, 1, R).addSImm(C == ConstantBool::True);
+      BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
       return;
     }
     
@@ -586,21 +586,21 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
     if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
       unsigned uval = CUI->getValue();
       if (uval < 32768) {
-        BuildMI(*MBB, IP, PPC32::LI, 1, R).addSImm(uval);
+        BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(uval);
       } else {
         unsigned Temp = makeAnotherReg(Type::IntTy);
-        BuildMI(*MBB, IP, PPC32::LIS, 1, Temp).addSImm(uval >> 16);
-        BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(Temp).addImm(uval);
+        BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(uval >> 16);
+        BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(uval);
       }
       return;
     } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
       int sval = CSI->getValue();
       if (sval < 32768 && sval >= -32768) {
-        BuildMI(*MBB, IP, PPC32::LI, 1, R).addSImm(sval);
+        BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(sval);
       } else {
         unsigned Temp = makeAnotherReg(Type::IntTy);
-        BuildMI(*MBB, IP, PPC32::LIS, 1, Temp).addSImm(sval >> 16);
-        BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(Temp).addImm(sval);
+        BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(sval >> 16);
+        BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(sval);
       }
       return;
     }
@@ -621,26 +621,26 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
     unsigned Reg2 = makeAnotherReg(Type::IntTy);
     // Move value at base + distance into return reg
     copyGlobalBaseToRegister(MBB, IP, GlobalBase);
-    BuildMI(*MBB, IP, PPC32::LOADHiAddr, 2, Reg1).addReg(GlobalBase)
+    BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1).addReg(GlobalBase)
       .addConstantPoolIndex(CPI);
-    BuildMI(*MBB, IP, PPC32::LOADLoDirect, 2, Reg2).addReg(Reg1)
+    BuildMI(*MBB, IP, PPC::LOADLoDirect, 2, Reg2).addReg(Reg1)
       .addConstantPoolIndex(CPI);
 
-    unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
+    unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
     BuildMI(*MBB, IP, LoadOpcode, 2, R).addSImm(0).addReg(Reg2);
   } else if (isa<ConstantPointerNull>(C)) {
     // Copy zero (null pointer) to the register.
-    BuildMI(*MBB, IP, PPC32::LI, 1, R).addSImm(0);
+    BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
   } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
     // GV is located at base + distance
     unsigned GlobalBase = makeAnotherReg(Type::IntTy);
     unsigned TmpReg = makeAnotherReg(GV->getType());
     unsigned Opcode = (GV->hasWeakLinkage() || GV->isExternal()) ? 
-      PPC32::LOADLoIndirect : PPC32::LOADLoDirect;
+      PPC::LOADLoIndirect : PPC::LOADLoDirect;
     
     // Move value at base + distance into return reg
     copyGlobalBaseToRegister(MBB, IP, GlobalBase);
-    BuildMI(*MBB, IP, PPC32::LOADHiAddr, 2, TmpReg).addReg(GlobalBase)
+    BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg).addReg(GlobalBase)
       .addGlobalAddress(GV);
     BuildMI(*MBB, IP, Opcode, 2, R).addReg(TmpReg).addGlobalAddress(GV);
   
@@ -660,12 +660,12 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
   unsigned FPR_remaining = 13;
   unsigned GPR_idx = 0, FPR_idx = 0;
   static const unsigned GPR[] = { 
-    PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
-    PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
+    PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+    PPC::R7, PPC::R8, PPC::R9, PPC::R10,
   };
   static const unsigned FPR[] = {
-    PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4, PPC32::F5, PPC32::F6, PPC32::F7,
-    PPC32::F8, PPC32::F9, PPC32::F10, PPC32::F11, PPC32::F12, PPC32::F13
+    PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
+    PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
   };
     
   MachineFrameInfo *MFI = F->getFrameInfo();
@@ -680,11 +680,11 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
       if (ArgLive) {
         FI = MFI->CreateFixedObject(4, ArgOffset);
         if (GPR_remaining > 0) {
-          BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
-          BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+          BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+          BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
             .addReg(GPR[GPR_idx]);
         } else {
-          addFrameReference(BuildMI(BB, PPC32::LBZ, 2, Reg), FI);
+          addFrameReference(BuildMI(BB, PPC::LBZ, 2, Reg), FI);
         }
       }
       break;
@@ -692,11 +692,11 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
       if (ArgLive) {
         FI = MFI->CreateFixedObject(4, ArgOffset);
         if (GPR_remaining > 0) {
-          BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
-          BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+          BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+          BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
             .addReg(GPR[GPR_idx]);
         } else {
-          addFrameReference(BuildMI(BB, PPC32::LHZ, 2, Reg), FI);
+          addFrameReference(BuildMI(BB, PPC::LHZ, 2, Reg), FI);
         }
       }
       break;
@@ -704,11 +704,11 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
       if (ArgLive) {
         FI = MFI->CreateFixedObject(4, ArgOffset);
         if (GPR_remaining > 0) {
-          BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
-          BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+          BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+          BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
             .addReg(GPR[GPR_idx]);
         } else {
-          addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
+          addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
         }
       }
       break;
@@ -716,15 +716,15 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
       if (ArgLive) {
         FI = MFI->CreateFixedObject(8, ArgOffset);
         if (GPR_remaining > 1) {
-          BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
-          BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
-          BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+          BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+          BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
+          BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
             .addReg(GPR[GPR_idx]);
-          BuildMI(BB, PPC32::OR, 2, Reg+1).addReg(GPR[GPR_idx+1])
+          BuildMI(BB, PPC::OR, 2, Reg+1).addReg(GPR[GPR_idx+1])
             .addReg(GPR[GPR_idx+1]);
         } else {
-          addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
-          addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg+1), FI, 4);
+          addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
+          addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg+1), FI, 4);
         }
       }
       // longs require 4 additional bytes and use 2 GPRs
@@ -739,12 +739,12 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
         FI = MFI->CreateFixedObject(4, ArgOffset);
 
         if (FPR_remaining > 0) {
-          BuildMI(BB, PPC32::IMPLICIT_DEF, 0, FPR[FPR_idx]);
-          BuildMI(BB, PPC32::FMR, 1, Reg).addReg(FPR[FPR_idx]);
+          BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
+          BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
           FPR_remaining--;
           FPR_idx++;
         } else {
-          addFrameReference(BuildMI(BB, PPC32::LFS, 2, Reg), FI);
+          addFrameReference(BuildMI(BB, PPC::LFS, 2, Reg), FI);
         }
       }
       break;
@@ -753,12 +753,12 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
         FI = MFI->CreateFixedObject(8, ArgOffset);
 
         if (FPR_remaining > 0) {
-          BuildMI(BB, PPC32::IMPLICIT_DEF, 0, FPR[FPR_idx]);
-          BuildMI(BB, PPC32::FMR, 1, Reg).addReg(FPR[FPR_idx]);
+          BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
+          BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
           FPR_remaining--;
           FPR_idx++;
         } else {
-          addFrameReference(BuildMI(BB, PPC32::LFD, 2, Reg), FI);
+          addFrameReference(BuildMI(BB, PPC::LFD, 2, Reg), FI);
         }
       }
 
@@ -806,12 +806,12 @@ void ISel::SelectPHINodes() {
       // Create a new machine instr PHI node, and insert it.
       unsigned PHIReg = getReg(*PN);
       MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
-                                    PPC32::PHI, PN->getNumOperands(), PHIReg);
+                                    PPC::PHI, PN->getNumOperands(), PHIReg);
 
       MachineInstr *LongPhiMI = 0;
       if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
         LongPhiMI = BuildMI(MBB, PHIInsertPoint,
-                            PPC32::PHI, PN->getNumOperands(), PHIReg+1);
+                            PPC::PHI, PN->getNumOperands(), PHIReg+1);
 
       // PHIValues - Map of blocks to incoming virtual registers.  We use this
       // so that we only initialize one incoming value for a particular block,
@@ -858,7 +858,7 @@ void ISel::SelectPHINodes() {
             MachineBasicBlock::iterator PI = PredMBB->begin();
 
             // Skip over any PHI nodes though!
-            while (PI != PredMBB->end() && PI->getOpcode() == PPC32::PHI)
+            while (PI != PredMBB->end() && PI->getOpcode() == PPC::PHI)
               ++PI;
 
             ValReg = getReg(Val, PredMBB, PI);
@@ -948,19 +948,19 @@ static unsigned getSetCCNumber(unsigned Opcode) {
 static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
   switch (Opcode) {
   default: assert(0 && "Unknown setcc instruction!");
-  case Instruction::SetEQ: return PPC32::BEQ;
-  case Instruction::SetNE: return PPC32::BNE;
-  case Instruction::SetLT: return PPC32::BLT;
-  case Instruction::SetGE: return PPC32::BGE;
-  case Instruction::SetGT: return PPC32::BGT;
-  case Instruction::SetLE: return PPC32::BLE;
+  case Instruction::SetEQ: return PPC::BEQ;
+  case Instruction::SetNE: return PPC::BNE;
+  case Instruction::SetLT: return PPC::BLT;
+  case Instruction::SetGE: return PPC::BGE;
+  case Instruction::SetGT: return PPC::BGT;
+  case Instruction::SetLE: return PPC::BLE;
   }
 }
 
 /// emitUCOM - emits an unordered FP compare.
 void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
                      unsigned LHS, unsigned RHS) {
-    BuildMI(*MBB, IP, PPC32::FCMPU, 2, PPC32::CR0).addReg(LHS).addReg(RHS);
+    BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
 }
 
 /// EmitComparison - emits a comparison of the two operands, returning the
@@ -979,29 +979,29 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
   if (Class == cByte) {
     unsigned TmpReg = makeAnotherReg(CompTy);
     if (CompTy->isSigned())
-      BuildMI(*MBB, IP, PPC32::EXTSB, 1, TmpReg).addReg(Op0r);
+      BuildMI(*MBB, IP, PPC::EXTSB, 1, TmpReg).addReg(Op0r);
     else
-      BuildMI(*MBB, IP, PPC32::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
+      BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
         .addImm(24).addImm(31);
     Op0r = TmpReg;
   } else if (Class == cShort) {
     unsigned TmpReg = makeAnotherReg(CompTy);
     if (CompTy->isSigned())
-      BuildMI(*MBB, IP, PPC32::EXTSH, 1, TmpReg).addReg(Op0r);
+      BuildMI(*MBB, IP, PPC::EXTSH, 1, TmpReg).addReg(Op0r);
     else
-      BuildMI(*MBB, IP, PPC32::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
+      BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
         .addImm(16).addImm(31);
     Op0r = TmpReg;
   }
   
   // Use crand for lt, gt and crandc for le, ge
-  unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC32::CRAND : PPC32::CRANDC;
+  unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
   // ? cr1[lt] : cr1[gt]
   unsigned CR1field = (OpNum == 2 || OpNum == 3) ? 4 : 5;
   // ? cr0[lt] : cr0[gt]
   unsigned CR0field = (OpNum == 2 || OpNum == 5) ? 0 : 1;
-  unsigned Opcode = CompTy->isSigned() ? PPC32::CMPW : PPC32::CMPLW;
-  unsigned OpcodeImm = CompTy->isSigned() ? PPC32::CMPWI : PPC32::CMPLWI;
+  unsigned Opcode = CompTy->isSigned() ? PPC::CMPW : PPC::CMPLW;
+  unsigned OpcodeImm = CompTy->isSigned() ? PPC::CMPWI : PPC::CMPLWI;
 
   // Special case handling of: cmp R, i
   if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
@@ -1010,10 +1010,10 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
 
       // Treat compare like ADDI for the purposes of immediate suitability
       if (canUseAsImmediateForOpcode(CI, 0)) {
-        BuildMI(*MBB, IP, OpcodeImm, 2, PPC32::CR0).addReg(Op0r).addSImm(Op1v);
+        BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
       } else {
         unsigned Op1r = getReg(Op1, MBB, IP);
-        BuildMI(*MBB, IP, Opcode, 2, PPC32::CR0).addReg(Op0r).addReg(Op1r);
+        BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
       }
       return OpNum;
     } else {
@@ -1027,27 +1027,27 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
         unsigned HiTmp = makeAnotherReg(Type::IntTy);
         unsigned FinalTmp = makeAnotherReg(Type::IntTy);
 
-        BuildMI(*MBB, IP, PPC32::XORI, 2, LoLow).addReg(Op0r+1)
+        BuildMI(*MBB, IP, PPC::XORI, 2, LoLow).addReg(Op0r+1)
           .addImm(LowCst & 0xFFFF);
-        BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow)
+        BuildMI(*MBB, IP, PPC::XORIS, 2, LoTmp).addReg(LoLow)
           .addImm(LowCst >> 16);
-        BuildMI(*MBB, IP, PPC32::XORI, 2, HiLow).addReg(Op0r)
+        BuildMI(*MBB, IP, PPC::XORI, 2, HiLow).addReg(Op0r)
           .addImm(HiCst & 0xFFFF);
-        BuildMI(*MBB, IP, PPC32::XORIS, 2, HiTmp).addReg(HiLow)
+        BuildMI(*MBB, IP, PPC::XORIS, 2, HiTmp).addReg(HiLow)
           .addImm(HiCst >> 16);
-        BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
+        BuildMI(*MBB, IP, PPC::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
         return OpNum;
       } else {
         unsigned ConstReg = makeAnotherReg(CompTy);
         copyConstantToRegister(MBB, IP, CI, ConstReg);
 
         // cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
-        BuildMI(*MBB, IP, Opcode, 2, PPC32::CR0).addReg(Op0r)
+        BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r)
           .addReg(ConstReg);
-        BuildMI(*MBB, IP, Opcode, 2, PPC32::CR1).addReg(Op0r+1)
+        BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1)
           .addReg(ConstReg+1);
-        BuildMI(*MBB, IP, PPC32::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
-        BuildMI(*MBB, IP, PPC32::CROR, 3).addImm(CR0field).addImm(CR0field)
+        BuildMI(*MBB, IP, PPC::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
+        BuildMI(*MBB, IP, PPC::CROR, 3).addImm(CR0field).addImm(CR0field)
           .addImm(2);
         return OpNum;
       }
@@ -1061,7 +1061,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
   case cByte:
   case cShort:
   case cInt:
-    BuildMI(*MBB, IP, Opcode, 2, PPC32::CR0).addReg(Op0r).addReg(Op1r);
+    BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
     break;
 
   case cFP32:
@@ -1074,19 +1074,19 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
       unsigned LoTmp = makeAnotherReg(Type::IntTy);
       unsigned HiTmp = makeAnotherReg(Type::IntTy);
       unsigned FinalTmp = makeAnotherReg(Type::IntTy);
-      BuildMI(*MBB, IP, PPC32::XOR, 2, HiTmp).addReg(Op0r).addReg(Op1r);
-      BuildMI(*MBB, IP, PPC32::XOR, 2, LoTmp).addReg(Op0r+1).addReg(Op1r+1);
-      BuildMI(*MBB, IP, PPC32::ORo,  2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
+      BuildMI(*MBB, IP, PPC::XOR, 2, HiTmp).addReg(Op0r).addReg(Op1r);
+      BuildMI(*MBB, IP, PPC::XOR, 2, LoTmp).addReg(Op0r+1).addReg(Op1r+1);
+      BuildMI(*MBB, IP, PPC::ORo,  2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
       break;  // Allow the sete or setne to be generated from flags set by OR
     } else {
       unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
       unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
 
       // cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
-      BuildMI(*MBB, IP, Opcode, 2, PPC32::CR0).addReg(Op0r).addReg(Op1r);
-      BuildMI(*MBB, IP, Opcode, 2, PPC32::CR1).addReg(Op0r+1).addReg(Op1r+1);
-      BuildMI(*MBB, IP, PPC32::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
-      BuildMI(*MBB, IP, PPC32::CROR, 3).addImm(CR0field).addImm(CR0field)
+      BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
+      BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1).addReg(Op1r+1);
+      BuildMI(*MBB, IP, PPC::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
+      BuildMI(*MBB, IP, PPC::CROR, 3).addImm(CR0field).addImm(CR0field)
         .addImm(2);
       return OpNum;
     }
@@ -1124,10 +1124,10 @@ void ISel::visitSetCondInst(SetCondInst &I) {
   // bCC. But MBB->getFirstTerminator() can't understand this.
   MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
   F->getBasicBlockList().insert(It, copy1MBB);
-  BuildMI(BB, Opcode, 2).addReg(PPC32::CR0).addMBB(copy1MBB);
+  BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
   MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
   F->getBasicBlockList().insert(It, copy0MBB);
-  BuildMI(BB, PPC32::B, 1).addMBB(copy0MBB);
+  BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
   MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
   F->getBasicBlockList().insert(It, sinkMBB);
   // Update machine-CFG edges
@@ -1139,8 +1139,8 @@ void ISel::visitSetCondInst(SetCondInst &I) {
   //   b sinkMBB
   BB = copy1MBB;
   unsigned TrueValue = makeAnotherReg(I.getType());
-  BuildMI(BB, PPC32::LI, 1, TrueValue).addSImm(1);
-  BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
+  BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
+  BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
   // Update machine-CFG edges
   BB->addSuccessor(sinkMBB);
 
@@ -1149,7 +1149,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
   //   fallthrough
   BB = copy0MBB;
   unsigned FalseValue = makeAnotherReg(I.getType());
-  BuildMI(BB, PPC32::LI, 1, FalseValue).addSImm(0);
+  BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
   // Update machine-CFG edges
   BB->addSuccessor(sinkMBB);
 
@@ -1157,7 +1157,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
   //  ...
   BB = sinkMBB;
-  BuildMI(BB, PPC32::PHI, 4, DestReg).addReg(FalseValue)
+  BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
     .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
 }
 
@@ -1188,7 +1188,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
     Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
   } else {
     unsigned CondReg = getReg(Cond, MBB, IP);
-    BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(CondReg).addSImm(0);
+    BuildMI(*MBB, IP, PPC::CMPI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
     Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
   }
 
@@ -1208,10 +1208,10 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
   // bCC. But MBB->getFirstTerminator() can't understand this.
   MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
   F->getBasicBlockList().insert(It, copy1MBB);
-  BuildMI(BB, Opcode, 2).addReg(PPC32::CR0).addMBB(copy1MBB);
+  BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
   MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
   F->getBasicBlockList().insert(It, copy0MBB);
-  BuildMI(BB, PPC32::B, 1).addMBB(copy0MBB);
+  BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
   MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
   F->getBasicBlockList().insert(It, sinkMBB);
   // Update machine-CFG edges
@@ -1223,7 +1223,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
   //   b sinkMBB
   BB = copy1MBB;
   unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
-  BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
+  BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
   // Update machine-CFG edges
   BB->addSuccessor(sinkMBB);
 
@@ -1239,11 +1239,11 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
   //  ...
   BB = sinkMBB;
-  BuildMI(BB, PPC32::PHI, 4, DestReg).addReg(FalseValue)
+  BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
     .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
   // For a register pair representing a long value, define the second reg
   if (getClass(TrueVal->getType()) == cLong)
-    BuildMI(BB, PPC32::LI, 1, DestReg+1).addImm(0);
+    BuildMI(BB, PPC::LI, 1, DestReg+1).addImm(0);
   return;
 }
 
@@ -1268,11 +1268,11 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
       int TheVal = CI->getRawValue() & 0xFFFFFFFF;
 
       if (TheVal < 32768 && TheVal >= -32768) {
-        BuildMI(BB, PPC32::LI, 1, targetReg).addSImm(TheVal);
+        BuildMI(BB, PPC::LI, 1, targetReg).addSImm(TheVal);
       } else {
         unsigned TmpReg = makeAnotherReg(Type::IntTy);
-        BuildMI(BB, PPC32::LIS, 1, TmpReg).addSImm(TheVal >> 16);
-        BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(TmpReg)
+        BuildMI(BB, PPC::LIS, 1, TmpReg).addSImm(TheVal >> 16);
+        BuildMI(BB, PPC::ORI, 2, targetReg).addReg(TmpReg)
           .addImm(TheVal & 0xFFFF);
       }
       return;
@@ -1285,22 +1285,22 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
   case cByte:
     // Extend value into target register (8->32)
     if (isUnsigned)
-      BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
+      BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
         .addZImm(24).addZImm(31);
     else
-      BuildMI(BB, PPC32::EXTSB, 1, targetReg).addReg(Reg);
+      BuildMI(BB, PPC::EXTSB, 1, targetReg).addReg(Reg);
     break;
   case cShort:
     // Extend value into target register (16->32)
     if (isUnsigned)
-      BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
+      BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
         .addZImm(16).addZImm(31);
     else
-      BuildMI(BB, PPC32::EXTSH, 1, targetReg).addReg(Reg);
+      BuildMI(BB, PPC::EXTSH, 1, targetReg).addReg(Reg);
     break;
   case cInt:
     // Move value into target register (32->32)
-    BuildMI(BB, PPC32::OR, 2, targetReg).addReg(Reg).addReg(Reg);
+    BuildMI(BB, PPC::OR, 2, targetReg).addReg(Reg).addReg(Reg);
     break;
   default:
     assert(0 && "Unpromotable operand class in promote32");
@@ -1317,25 +1317,25 @@ void ISel::visitReturnInst(ReturnInst &I) {
     case cByte:   // integral return values: extend or move into r3 and return
     case cShort:
     case cInt:
-      promote32(PPC32::R3, ValueRecord(RetVal));
+      promote32(PPC::R3, ValueRecord(RetVal));
       break;
     case cFP32:
     case cFP64: {   // Floats & Doubles: Return in f1
       unsigned RetReg = getReg(RetVal);
-      BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
+      BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(RetReg);
       break;
     }
     case cLong: {
       unsigned RetReg = getReg(RetVal);
-      BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
-      BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
+      BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(RetReg).addReg(RetReg);
+      BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(RetReg+1).addReg(RetReg+1);
       break;
     }
     default:
       visitInstruction(I);
     }
   }
-  BuildMI(BB, PPC32::BLR, 1).addImm(0);
+  BuildMI(BB, PPC::BLR, 1).addImm(0);
 }
 
 // getBlockAfter - Return the basic block which occurs lexically after the
@@ -1360,7 +1360,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
 
   if (!BI.isConditional()) {  // Unconditional branch?
     if (BI.getSuccessor(0) != NextBB) 
-      BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
+      BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
     return;
   }
   
@@ -1370,19 +1370,19 @@ void ISel::visitBranchInst(BranchInst &BI) {
     // Nope, cannot fold setcc into this branch.  Emit a branch on a condition
     // computed some other way...
     unsigned condReg = getReg(BI.getCondition());
-    BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(condReg)
+    BuildMI(BB, PPC::CMPLI, 3, PPC::CR0).addImm(0).addReg(condReg)
       .addImm(0);
     if (BI.getSuccessor(1) == NextBB) {
       if (BI.getSuccessor(0) != NextBB)
-        BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(PPC32::BNE)
+        BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BNE)
           .addMBB(MBBMap[BI.getSuccessor(0)])
           .addMBB(MBBMap[BI.getSuccessor(1)]);
     } else {
-      BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(PPC32::BEQ)
+      BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BEQ)
         .addMBB(MBBMap[BI.getSuccessor(1)])
         .addMBB(MBBMap[BI.getSuccessor(0)]);
       if (BI.getSuccessor(0) != NextBB)
-        BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
+        BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
     }
     return;
   }
@@ -1393,16 +1393,16 @@ void ISel::visitBranchInst(BranchInst &BI) {
   OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
   
   if (BI.getSuccessor(0) != NextBB) {
-    BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(Opcode)
+    BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
       .addMBB(MBBMap[BI.getSuccessor(0)])
       .addMBB(MBBMap[BI.getSuccessor(1)]);
     if (BI.getSuccessor(1) != NextBB)
-      BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
+      BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
   } else {
     // Change to the inverse condition...
     if (BI.getSuccessor(1) != NextBB) {
       Opcode = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode);
-      BuildMI(BB, PPC32::COND_BRANCH, 3).addReg(PPC32::CR0).addImm(Opcode)
+      BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
         .addMBB(MBBMap[BI.getSuccessor(1)])
         .addMBB(MBBMap[BI.getSuccessor(0)]);
     }
@@ -1443,20 +1443,20 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
 
     // Adjust the stack pointer for the new arguments...
     // These functions are automatically eliminated by the prolog/epilog pass
-    BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
+    BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
 
     // Arguments go on the stack in reverse order, as specified by the ABI.
     // Offset to the paramater area on the stack is 24.
     int GPR_remaining = 8, FPR_remaining = 13;
     unsigned GPR_idx = 0, FPR_idx = 0;
     static const unsigned GPR[] = { 
-      PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
-      PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
+      PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+      PPC::R7, PPC::R8, PPC::R9, PPC::R10,
     };
     static const unsigned FPR[] = {
-      PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4, PPC32::F5, PPC32::F6, 
-      PPC32::F7, PPC32::F8, PPC32::F9, PPC32::F10, PPC32::F11, PPC32::F12, 
-      PPC32::F13
+      PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, 
+      PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, 
+      PPC::F13
     };
     
     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
@@ -1470,13 +1470,13 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
           
         // Reg or stack?
         if (GPR_remaining > 0) {
-          BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
+          BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
             .addReg(ArgReg);
           CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
         }
         if (GPR_remainin