diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-08-05 22:05:03 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-05 22:05:03 +0000 |
| commit | 3c304a3ba18a040d3c3dbd15ab69da5543cdbd54 (patch) | |
| tree | aca20e2ff4d3219b44cf073bce8b032293453a46 /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | 8c4a8735ecf12bc2447129810ec1d6079fc767f2 (diff) | |
Consolidate the GPOpt stuff to all use the Subtarget, instead of still
depending on the command line option. Now the command line option just
sets the subtarget as appropriate. G5 opts will now default to on on
G5-enabled nightly testers among other machines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22688 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index b9cdb858b3..ae7f9b64a8 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -96,7 +96,7 @@ namespace { setOperationAction(ISD::SREM , MVT::f32, Expand); // If we're enabling GP optimizations, use hardware square root - if (!GPOPT) { + if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) { setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); } @@ -536,6 +536,7 @@ namespace { Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted"); Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations"); Statistic<>FrameOff("ppc-codegen", "Number of frame idx offsets collapsed"); + //===--------------------------------------------------------------------===// /// ISel - PPC32 specific code to select PPC32 machine instructions for /// SelectionDAG operations. @@ -929,7 +930,9 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) { void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){ unsigned IntCR = MakeReg(MVT::i32); BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg); - BuildMI(BB, GPOPT ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7); + bool GPOpt = + TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor(); + BuildMI(BB, GPOpt ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7); if (Inv) { unsigned Tmp1 = MakeReg(MVT::i32); BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx)) |