diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-11-27 23:37:22 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-11-27 23:37:22 +0000 |
| commit | c0f64ffab93d11fb27a3b8a0707b77400918a20e (patch) | |
| tree | cc2cfef30bfb1344f83d8cfd08aace72274bde47 /lib/Target/Alpha/AlphaLLRP.cpp | |
| parent | 722a0cafbd47eb6b8bf9a9e9dce2f6cb8383fef1 (diff) | |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaLLRP.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaLLRP.cpp | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp index eb2387740f..eb4867d668 100644 --- a/lib/Target/Alpha/AlphaLLRP.cpp +++ b/lib/Target/Alpha/AlphaLLRP.cpp @@ -15,6 +15,8 @@ #include "Alpha.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/ADT/SetOperations.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/CommandLine.h" @@ -42,6 +44,7 @@ namespace { } bool runOnMachineFunction(MachineFunction &F) { + const TargetInstrInfo *TII = F.getTarget().getInstrInfo(); bool Changed = false; MachineInstr* prev[3] = {0,0,0}; unsigned count = 0; @@ -70,7 +73,7 @@ namespace { prev[0] = prev[1]; prev[1] = prev[2]; prev[2] = 0; - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 1; count += 1; @@ -81,9 +84,9 @@ namespace { MI->getOperand(1).getImmedValue()) { prev[0] = prev[2]; prev[1] = prev[2] = 0; - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 2; count += 2; @@ -93,11 +96,11 @@ namespace { && prev[2]->getOperand(1).getImmedValue() == MI->getOperand(1).getImmedValue()) { prev[0] = prev[1] = prev[2] = 0; - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 3; count += 3; @@ -130,7 +133,7 @@ namespace { if (ub || AlignAll) { //we can align stuff for free at this point while (count % 4) { - BuildMI(MBB, MBB.end(), Alpha::BISr, 2, Alpha::R31) + BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31).addReg(Alpha::R31); ++count; ++nopalign; |