Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead

of opcode and number of operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8

36 files changed, 400 insertions, 356 deletions

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 7ad33f596f..1aa8b40e7e 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -27,7 +27,6 @@ namespace llvm {
 class Value;
 class Function;
 class MachineBasicBlock;
-class TargetInstrInfo;
 class TargetInstrDescriptor;
 class TargetMachine;
 class GlobalValue;
@@ -296,7 +295,7 @@ public:
 ///
 class MachineInstr {
   short Opcode;                         // the opcode
-  short NumImplicitOps;                 // Number of implicit operands (which
+  unsigned short NumImplicitOps;        // Number of implicit operands (which
                                         // are determined at construction time).
 
   std::vector<MachineOperand> Operands; // the operands
@@ -314,19 +313,20 @@ class MachineInstr {
   friend struct ilist_traits<MachineInstr>;
 
 public:
-  /// MachineInstr ctor - This constructor reserves space for numOperand
-  /// operands.
-  MachineInstr(short Opcode, unsigned numOperands);
+  /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
+  /// opcode 0 and no operands.
+  MachineInstr();
 
   /// MachineInstr ctor - This constructor create a MachineInstr and add the
-  /// implicit operands. It reserves space for numOperand operands.
-  MachineInstr(const TargetInstrInfo &TII, short Opcode, unsigned numOperands);
+  /// implicit operands. It reserves space for number of operands specified by
+  /// TargetInstrDescriptor.
+  MachineInstr(const TargetInstrDescriptor &TID);
 
   /// MachineInstr ctor - Work exactly the same as the ctor above, except that
   /// the MachineInstr is created and added to the end of the specified basic
   /// block.
   ///
-  MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
+  MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
 
   ~MachineInstr();
 
diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index 1fd9348820..8bacdee696 100644
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -19,10 +19,11 @@
 
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
+class TargetInstrDescriptor;
+
 class MachineInstrBuilder {
   MachineInstr *MI;
 public:
@@ -83,36 +84,29 @@ public:
 };
 
 /// BuildMI - Builder interface.  Specify how to create the initial instruction
-/// itself.  NumOperands is the number of operands to the machine instruction to
-/// allow for memory efficient representation of machine instructions.
+/// itself.
 ///
-inline MachineInstrBuilder BuildMI(const TargetInstrInfo &TII, int Opcode,
-                                   unsigned NumOperands) {
-  return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands));
+inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
+  return MachineInstrBuilder(new MachineInstr(TID));
 }
 
 /// BuildMI - This version of the builder sets up the first operand as a
-/// destination virtual register.  NumOperands is the number of additional add*
-/// calls that are expected, not including the destination register.
+/// destination virtual register.
 ///
-inline MachineInstrBuilder  BuildMI(const TargetInstrInfo &TII, int Opcode,
-                                    unsigned NumOperands, unsigned DestReg) {
-  return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands+1))
-               .addReg(DestReg, true);
+  inline MachineInstrBuilder  BuildMI(const TargetInstrDescriptor &TID,
+                                      unsigned DestReg) {
+  return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
 }
 
 /// BuildMI - This version of the builder inserts the newly-built
 /// instruction before the given position in the given MachineBasicBlock, and
 /// sets up the first operand as a destination virtual register.
-/// NumOperands is the number of additional add* calls that are expected,
-/// not including the destination register.
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::iterator I,
-                                   int Opcode, unsigned NumOperands,
+                                   const TargetInstrDescriptor &TID,
                                    unsigned DestReg) {
-  MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
-                                      getInstrInfo(), Opcode, NumOperands+1);
+  MachineInstr *MI = new MachineInstr(TID);
   BB.insert(I, MI);
   return MachineInstrBuilder(MI).addReg(DestReg, true);
 }
@@ -123,9 +117,8 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::iterator I,
-                                   int Opcode, unsigned NumOperands) {
-  MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
-                                      getInstrInfo(), Opcode, NumOperands);
+                                   const TargetInstrDescriptor &TID) {
+  MachineInstr *MI = new MachineInstr(TID);
   BB.insert(I, MI);
   return MachineInstrBuilder(MI);
 }
@@ -134,20 +127,19 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
 /// instruction at the end of the given MachineBasicBlock, and does NOT take a
 /// destination register.
 ///
-inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
-                                   unsigned NumOperands) {
-  return BuildMI(*BB, BB->end(), Opcode, NumOperands);
+inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
+                                   const TargetInstrDescriptor &TID) {
+  return BuildMI(*BB, BB->end(), TID);
 }
 
 /// BuildMI - This version of the builder inserts the newly-built
 /// instruction at the end of the given MachineBasicBlock, and sets up the first
-/// operand as a destination virtual register. NumOperands is the number of
-/// additional add* calls that are expected, not including the destination
-/// register.
+/// operand as a destination virtual register. 
 ///
-inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
-                                   unsigned NumOperands, unsigned DestReg) {
-  return BuildMI(*BB, BB->end(), Opcode, NumOperands, DestReg);
+inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
+                                   const TargetInstrDescriptor &TID,
+                                   unsigned DestReg) {
+  return BuildMI(*BB, BB->end(), TID, DestReg);
 }
 
 } // End llvm namespace
diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp
index 201b79e130..8d8e9b7c59 100644
--- a/lib/CodeGen/MachineBasicBlock.cpp
+++ b/lib/CodeGen/MachineBasicBlock.cpp
@@ -52,7 +52,7 @@ void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock* N) {
 
 
 MachineInstr* ilist_traits<MachineInstr>::createSentinel() {
-  MachineInstr* dummy = new MachineInstr(0, 0);
+  MachineInstr* dummy = new MachineInstr();
   LeakDetector::removeGarbageObject(dummy);
   return dummy;
 }
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 16e235a679..bafdffb6d4 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -32,14 +32,10 @@ namespace llvm {
   extern const TargetInstrDescriptor *TargetInstrDescriptors;
 }
 
-/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
-/// not a resize for them.  It is expected that if you use this that you call
-/// add* methods below to fill up the operands, instead of the Set methods.
-/// Eventually, the "resizing" ctors will be phased out.
-///
-MachineInstr::MachineInstr(short opcode, unsigned numOperands)
-  : Opcode(opcode), NumImplicitOps(0), parent(0) {
-  Operands.reserve(numOperands);
+/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
+/// opcode 0 and no operands.
+MachineInstr::MachineInstr()
+  : Opcode(0), NumImplicitOps(0), parent(0) {
   // Make sure that we get added to a machine basicblock
   LeakDetector::addGarbageObject(this);
 }
@@ -72,18 +68,18 @@ void MachineInstr::addImplicitDefUseOperands(const TargetInstrDescriptor &TID) {
 }
 
 /// MachineInstr ctor - This constructor create a MachineInstr and add the
-/// implicit operands. It reserves space for numOperand operands.
-MachineInstr::MachineInstr(const TargetInstrInfo &TII, short opcode,
-                           unsigned numOperands)
-  : Opcode(opcode), NumImplicitOps(0), parent(0) {
-  const TargetInstrDescriptor &TID = TII.get(opcode);
+/// implicit operands. It reserves space for number of operands specified by
+/// TargetInstrDescriptor or the numOperands if it is not zero. (for
+/// instructions with variable number of operands).
+MachineInstr::MachineInstr(const TargetInstrDescriptor &TID)
+  : Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
   if (TID.ImplicitDefs)
     for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
       NumImplicitOps++;
   if (TID.ImplicitUses)
     for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
       NumImplicitOps++;
-  Operands.reserve(NumImplicitOps + numOperands);
+  Operands.reserve(NumImplicitOps + TID.numOperands);
   addImplicitDefUseOperands(TID);
   // Make sure that we get added to a machine basicblock
   LeakDetector::addGarbageObject(this);
@@ -92,19 +88,17 @@ MachineInstr::MachineInstr(const TargetInstrInfo &TII, short opcode,
 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
 /// MachineInstr is created and added to the end of the specified basic block.
 ///
-MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
-                           unsigned numOperands)
-  : Opcode(opcode), NumImplicitOps(0), parent(0) {
+MachineInstr::MachineInstr(MachineBasicBlock *MBB,
+                           const TargetInstrDescriptor &TID)
+  : Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
   assert(MBB && "Cannot use inserting ctor with null basic block!");
-  const TargetInstrDescriptor &TID = MBB->getParent()->getTarget().
-    getInstrInfo()->get(opcode);
   if (TID.ImplicitDefs)
     for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
       NumImplicitOps++;
   if (TID.ImplicitUses)
     for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
       NumImplicitOps++;
-  Operands.reserve(NumImplicitOps + numOperands);
+  Operands.reserve(NumImplicitOps + TID.numOperands);
   addImplicitDefUseOperands(TID);
   // Make sure that we get added to a machine basicblock
   LeakDetector::addGarbageObject(this);
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 5330306c2a..e72cdc6b82 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -395,7 +395,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
 #endif
 
     // Create the new machine instruction.
-    MachineInstr *MI = new MachineInstr(*TII, Opc, NumMIOperands);
+    MachineInstr *MI = new MachineInstr(II);
     
     // Add result register values for things that are defined by this
     // instruction.
@@ -518,7 +518,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
       
       // Create the inline asm machine instruction.
       MachineInstr *MI =
-        new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
+        new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
 
       // Add the asm string as an external symbol operand.
       const char *AsmStr =
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index c18b5bc274..0257e1b775 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -294,8 +294,9 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
       }
       unsigned PHIReg = ValueMap[PN];
       assert(PHIReg && "PHI node does not have an assigned virtual register!");
+      const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
       for (unsigned i = 0; i != NumElements; ++i)
-        BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
+        BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
     }
   }
 }
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index beea31ca8e..f99615b572 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -19,7 +19,8 @@
 using namespace llvm;
 
 ARMInstrInfo::ARMInstrInfo()
-  : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
+  : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
+    RI(*this) {
 }
 
 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
@@ -54,5 +55,5 @@ void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
                                   const std::vector<MachineOperand> &Cond)const{
   // Can only insert uncond branches so far.
   assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
-  BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
+  BuildMI(&MBB, get(ARM::b)).addMBB(TBB);
 }
diff --git a/lib/Target/ARM/ARMMul.cpp b/lib/Target/ARM/ARMMul.cpp
index 474039db27..c4eeaac479 100644
--- a/lib/Target/ARM/ARMMul.cpp
+++ b/lib/Target/ARM/ARMMul.cpp
@@ -16,6 +16,8 @@
 #include "ARM.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/Compiler.h"
 
 using namespace llvm;
@@ -60,8 +62,8 @@ bool FixMul::runOnMachineFunction(MachineFunction &MF) {
             RsOp.setReg(Rm);
           } else {
             unsigned scratch = Op == ARM::MUL ? ARM::R12 : ARM::R0;
-            BuildMI(MBB, I, ARM::MOV, 3, scratch).addReg(Rm).addImm(0)
-              .addImm(ARMShift::LSL);
+            BuildMI(MBB, I, MF.getTarget().getInstrInfo()->get(ARM::MOV),
+                    scratch).addReg(Rm).addImm(0).addImm(ARMShift::LSL);
             RmOp.setReg(scratch);
           }
         }
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 3b5ed6a0fa..09c8b1f5d0 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -22,6 +22,7 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include <iostream>
 using namespace llvm;
@@ -35,8 +36,9 @@ static bool hasFP(const MachineFunction &MF) {
   return NoFramePointerElim || MFI->hasVarSizedObjects();
 }
 
-ARMRegisterInfo::ARMRegisterInfo()
-  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
+ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii)
+  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+    TII(tii) {
 }
 
 void ARMRegisterInfo::
@@ -44,7 +46,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                     unsigned SrcReg, int FI,
                     const TargetRegisterClass *RC) const {
   assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::STR, 3).addReg(SrcReg).addFrameIndex(FI).addImm(0);
+  BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI).addImm(0);
 }
 
 void ARMRegisterInfo::
@@ -52,7 +54,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                      unsigned DestReg, int FI,
                      const TargetRegisterClass *RC) const {
   assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::LDR, 2, DestReg).addFrameIndex(FI).addImm(0);
+  BuildMI(MBB, I, TII.get(ARM::LDR), DestReg).addFrameIndex(FI).addImm(0);
 }
 
 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
@@ -64,12 +66,12 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
          RC == ARM::DFPRegsRegisterClass);
 
   if (RC == ARM::IntRegsRegisterClass)
-    BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
+    BuildMI(MBB, I, TII.get(ARM::MOV), DestReg).addReg(SrcReg).addImm(0)
       .addImm(ARMShift::LSL);
   else if (RC == ARM::FPRegsRegisterClass)
-    BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
+    BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
   else
-    BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
+    BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
 }
 
 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
@@ -109,12 +111,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 
       if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
         // sub sp, sp, amount
-        BuildMI(MBB, I, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
+        BuildMI(MBB, I, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(Amount)
           .addImm(0).addImm(ARMShift::LSL);
       } else {
         // add sp, sp, amount
         assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
-        BuildMI(MBB, I, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
+        BuildMI(MBB, I, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(Amount)
           .addImm(0).addImm(ARMShift::LSL);
       }
     }
@@ -155,7 +157,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
     // Insert a set of r12 with the full address
     // r12 = r13 + offset
     MachineBasicBlock *MBB2 = MI.getParent();
-    BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(BaseRegister)
+    BuildMI(*MBB2, II, TII.get(ARM::ADD), ARM::R12).addReg(BaseRegister)
       .addImm(Offset).addImm(0).addImm(ARMShift::LSL);
 
     // Replace the FrameIndex with r12
@@ -191,13 +193,13 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
   MFI->setStackSize(NumBytes);
 
   //sub sp, sp, #NumBytes
-  BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
+  BuildMI(MBB, MBBI, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
 	  .addImm(0).addImm(ARMShift::LSL);
 
   if (HasFP) {
-    BuildMI(MBB, MBBI, ARM::STR, 3)
+    BuildMI(MBB, MBBI, TII.get(ARM::STR))
       .addReg(ARM::R11).addReg(ARM::R13).addImm(0);
-    BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R11).addReg(ARM::R13).addImm(0).
+    BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R11).addReg(ARM::R13).addImm(0).
       addImm(ARMShift::LSL);
   }
 }
@@ -212,13 +214,13 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
   int          NumBytes = (int) MFI->getStackSize();
 
   if (hasFP(MF)) {
-    BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R13).addReg(ARM::R11).addImm(0).
+    BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R13).addReg(ARM::R11).addImm(0).
       addImm(ARMShift::LSL);
-    BuildMI(MBB, MBBI, ARM::LDR, 2, ARM::R11).addReg(ARM::R13).addImm(0);
+    BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
   }
 
   //add sp, sp, #NumBytes
-  BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
+  BuildMI(MBB, MBBI, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
 	  .addImm(0).addImm(ARMShift::LSL);
 }
 
diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h
index 69f5640dd6..9ef761832c 100644
--- a/lib/Target/ARM/ARMRegisterInfo.h
+++ b/lib/Target/ARM/ARMRegisterInfo.h
@@ -21,10 +21,12 @@
 namespace llvm {
 
 class Type;
+class TargetInstrInfo;
 
 struct ARMRegisterInfo : public ARMGenRegisterInfo {
+  const TargetInstrInfo &TII;
 
-  ARMRegisterInfo();
+  ARMRegisterInfo(const TargetInstrInfo &tii);
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 96514d9332..4ac352b674 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -110,25 +110,25 @@ void AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
   // One-way branch.
   if (FBB == 0) {
     if (Cond.empty())   // Unconditional branch
-      BuildMI(&MBB, Alpha::BR, 1).addMBB(TBB);
+      BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
     else                // Conditional branch
       if (isAlphaIntCondCode(Cond[0].getImm()))
-        BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
+        BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
       else
-        BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
+        BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
     return;
   }
   
   // Two-way Conditional Branch.
   if (isAlphaIntCondCode(Cond[0].getImm()))
-    BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
+    BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
   else
-    BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
+    BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
-  BuildMI(&MBB, Alpha::BR, 1).addMBB(FBB);
+  BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
 }
 
 static unsigned AlphaRevCondCode(unsigned Opcode) {
@@ -230,7 +230,7 @@ void AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 
 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, 
                                 MachineBasicBlock::iterator MI) const {
-  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
+  BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
     .addReg(Alpha::R31);
 }
 
diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index eb2387740f..eb4867d668 100644
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -15,6 +15,8 @@
 #include "Alpha.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/ADT/SetOperations.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Support/CommandLine.h"
@@ -42,6 +44,7 @@ namespace {
     }
 
     bool runOnMachineFunction(MachineFunction &F) {
+      const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
       bool Changed = false;
       MachineInstr* prev[3] = {0,0,0};
       unsigned count = 0;
@@ -70,7 +73,7 @@ namespace {
 		  prev[0] = prev[1];
 		  prev[1] = prev[2];
 		  prev[2] = 0;
-		  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
+		  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
 		    .addReg(Alpha::R31); 
 		  Changed = true; nopintro += 1;
 		  count += 1;
@@ -81,9 +84,9 @@ namespace {
 			   MI->getOperand(1).getImmedValue()) {
 		  prev[0] = prev[2];
 		  prev[1] = prev[2] = 0;
-		  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
+		  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
 		    .addReg(Alpha::R31); 
-		  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
+		  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
 		    .addReg(Alpha::R31);
 		  Changed = true; nopintro += 2;
 		  count += 2;
@@ -93,11 +96,11 @@ namespace {
                            && prev[2]->getOperand(1).getImmedValue() == 
                            MI->getOperand(1).getImmedValue()) {
                   prev[0] = prev[1] = prev[2] = 0;
-                  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
+                  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
                     .addReg(Alpha::R31);
-                  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
+                  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
                     .addReg(Alpha::R31);
-                  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
+                  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
                     .addReg(Alpha::R31);
                   Changed = true; nopintro += 3;
                   count += 3;
@@ -130,7 +133,7 @@ namespace {
           if (ub || AlignAll) {
             //we can align stuff for free at this point
             while (count % 4) {
-              BuildMI(MBB, MBB.end(), Alpha::BISr, 2, Alpha::R31)
+              BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
                 .addReg(Alpha::R31).addReg(Alpha::R31);
               ++count;
               ++nopalign;
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index b3efe05686..02d15703b7 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -25,6 +25,7 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/ADT/STLExtras.h"
@@ -66,13 +67,13 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   //<< FrameIdx << "\n";
   //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
   if (RC == Alpha::F4RCRegisterClass)
-    BuildMI(MBB, MI, Alpha::STS, 3)
+    BuildMI(MBB, MI, TII.get(Alpha::STS))
       .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::F8RCRegisterClass)
-    BuildMI(MBB, MI, Alpha::STT, 3)
+    BuildMI(MBB, MI, TII.get(Alpha::STT))
       .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::GPRCRegisterClass)
-    BuildMI(MBB, MI, Alpha::STQ, 3)
+    BuildMI(MBB, MI, TII.get(Alpha::STQ))
       .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else
     abort();
@@ -86,13 +87,13 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
   //<< FrameIdx << "\n";
   if (RC == Alpha::F4RCRegisterClass)
-    BuildMI(MBB, MI, Alpha::LDS, 2, DestReg)
+    BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::F8RCRegisterClass)
-    BuildMI(MBB, MI, Alpha::LDT, 2, DestReg)
+    BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::GPRCRegisterClass)
-    BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg)
+    BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else
     abort();
@@ -116,13 +117,13 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
 	 unsigned InReg = MI->getOperand(1).getReg();
 	 Opc = (Opc == Alpha::BISr) ? Alpha::STQ : 
 	   ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
-	 NewMI = BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
+	 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameInde