Removed tabs everywhere except autogenerated & external files. Add make

target for tabs checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 96 insertions, 93 deletions

diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index a5c984eaf6..6d2d243e3d 100644
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -50,101 +50,104 @@ namespace {
       unsigned count = 0;
       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
            FI != FE; ++FI) {
-	MachineBasicBlock& MBB = *FI;
-	bool ub = false;
-	  for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
-	    if (count%4 == 0)
-	      prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
-	    ++count;
-	    MachineInstr *MI = I++;
-	    switch (MI->getOpcode()) {
-	    case Alpha::LDQ:  case Alpha::LDL:
-	    case Alpha::LDWU: case Alpha::LDBU:
-	    case Alpha::LDT: case Alpha::LDS:
-	    case Alpha::STQ:  case Alpha::STL:
-	    case Alpha::STW:  case Alpha::STB:
-	    case Alpha::STT: case Alpha::STS:
-	      if (MI->getOperand(2).getReg() == Alpha::R30) {
-		if (prev[0] 
-		    && prev[0]->getOperand(2).getReg() == 
-		    MI->getOperand(2).getReg()
-		    && prev[0]->getOperand(1).getImmedValue() == 
-		    MI->getOperand(1).getImmedValue()) {
-		  prev[0] = prev[1];
-		  prev[1] = prev[2];
-		  prev[2] = 0;
-		  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-		    .addReg(Alpha::R31); 
-		  Changed = true; nopintro += 1;
-		  count += 1;
-		} else if (prev[1] 
-			   && prev[1]->getOperand(2).getReg() == 
-			   MI->getOperand(2).getReg()
-			   && prev[1]->getOperand(1).getImmedValue() == 
-			   MI->getOperand(1).getImmedValue()) {
-		  prev[0] = prev[2];
-		  prev[1] = prev[2] = 0;
-		  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-		    .addReg(Alpha::R31); 
-		  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-		    .addReg(Alpha::R31);
-		  Changed = true; nopintro += 2;
-		  count += 2;
-		} else if (prev[2] 
-                           && prev[2]->getOperand(2).getReg() == 
-                           MI->getOperand(2).getReg()
-                           && prev[2]->getOperand(1).getImmedValue() == 
-                           MI->getOperand(1).getImmedValue()) {
-                  prev[0] = prev[1] = prev[2] = 0;
-                  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                    .addReg(Alpha::R31);
-                  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                    .addReg(Alpha::R31);
-                  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                    .addReg(Alpha::R31);
-                  Changed = true; nopintro += 3;
-                  count += 3;
-                }
-                prev[0] = prev[1];
-                prev[1] = prev[2];
-                prev[2] = MI;
-        	break;
-              }
-              prev[0] = prev[1];
-              prev[1] = prev[2];
-              prev[2] = 0;
-              break;
-            case Alpha::ALTENT:
-            case Alpha::MEMLABEL:
-            case Alpha::PCLABEL:
-            case Alpha::IDEF_I:
-            case Alpha::IDEF_F32:
-            case Alpha::IDEF_F64:
-              --count;
-              break;
-            case Alpha::BR:
-            case Alpha::JMP:
-              ub = true;
-              //fall through
-            default:
-              prev[0] = prev[1];
-              prev[1] = prev[2];
-              prev[2] = 0;
-              break;
-            }
+        MachineBasicBlock& MBB = *FI;
+        bool ub = false;
+        for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
+          if (count%4 == 0)
+            prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
+          ++count;
+          MachineInstr *MI = I++;
+          switch (MI->getOpcode()) {
+          case Alpha::LDQ:  case Alpha::LDL:
+          case Alpha::LDWU: case Alpha::LDBU:
+          case Alpha::LDT: case Alpha::LDS:
+          case Alpha::STQ:  case Alpha::STL:
+          case Alpha::STW:  case Alpha::STB:
+          case Alpha::STT: case Alpha::STS:
+           if (MI->getOperand(2).getReg() == Alpha::R30) {
+             if (prev[0] 
+                 && prev[0]->getOperand(2).getReg() == 
+                 MI->getOperand(2).getReg()
+                 && prev[0]->getOperand(1).getImmedValue() == 
+                 MI->getOperand(1).getImmedValue()) {
+               prev[0] = prev[1];
+               prev[1] = prev[2];
+               prev[2] = 0;
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31)
+                 .addReg(Alpha::R31); 
+               Changed = true; nopintro += 1;
+               count += 1;
+             } else if (prev[1] 
+                        && prev[1]->getOperand(2).getReg() == 
+                        MI->getOperand(2).getReg()
+                        && prev[1]->getOperand(1).getImmedValue() == 
+                        MI->getOperand(1).getImmedValue()) {
+               prev[0] = prev[2];
+               prev[1] = prev[2] = 0;
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31)
+                 .addReg(Alpha::R31); 
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31)
+                 .addReg(Alpha::R31);
+               Changed = true; nopintro += 2;
+               count += 2;
+             } else if (prev[2] 
+                        && prev[2]->getOperand(2).getReg() == 
+                        MI->getOperand(2).getReg()
+                        && prev[2]->getOperand(1).getImmedValue() == 
+                        MI->getOperand(1).getImmedValue()) {
+               prev[0] = prev[1] = prev[2] = 0;
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+                 .addReg(Alpha::R31);
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+                 .addReg(Alpha::R31);
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+                 .addReg(Alpha::R31);
+               Changed = true; nopintro += 3;
+               count += 3;
+             }
+             prev[0] = prev[1];
+             prev[1] = prev[2];
+             prev[2] = MI;
+             break;
+           }
+           prev[0] = prev[1];
+           prev[1] = prev[2];
+           prev[2] = 0;
+           break;
+          case Alpha::ALTENT:
+          case Alpha::MEMLABEL:
+          case Alpha::PCLABEL:
+          case Alpha::IDEF_I:
+          case Alpha::IDEF_F32:
+          case Alpha::IDEF_F64:
+            --count;
+            break;
+          case Alpha::BR:
+          case Alpha::JMP:
+            ub = true;
+            //fall through
+          default:
+            prev[0] = prev[1];
+            prev[1] = prev[2];
+            prev[2] = 0;
+            break;
           }
-          if (ub || AlignAll) {
-            //we can align stuff for free at this point
-            while (count % 4) {
-              BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
-                .addReg(Alpha::R31).addReg(Alpha::R31);
-              ++count;
-              ++nopalign;
-              prev[0] = prev[1];
-              prev[1] = prev[2];
-              prev[2] = 0;
-            }
+        }
+        if (ub || AlignAll) {
+          //we can align stuff for free at this point
+          while (count % 4) {
+            BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
+              .addReg(Alpha::R31).addReg(Alpha::R31);
+            ++count;
+            ++nopalign;
+            prev[0] = prev[1];
+            prev[1] = prev[2];
+            prev[2] = 0;
           }
+        }
       }
       return Changed;
     }