diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-07 18:33:19 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-07 18:33:19 +0000 |
| commit | 4d4e25740bd1225f413a10db6166b620d2f5fbbb (patch) | |
| tree | 4be29fe4c1390e23b11ab9fb2cb051f3100a1020 /lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | |
| parent | 45e1a53efd40a594fa8bb59aee75bb0984770d29 (diff) | |
Add some more comments about checkings of invalid register numbers.
And two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index bc0ba92d58..f4fa3de268 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1110,6 +1110,11 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn, // A8.6.3 ADC (register-shifted register) // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + // + // This also accounts for shift instructions (register) where, fortunately, + // Inst{19-16} = 0b0000. + // A8.6.89 LSL (register) + // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; if (decodeRd(insn) == 15 || decodeRn(insn) == 15 || decodeRm(insn) == 15 || decodeRs(insn) == 15) return false; |