From 4d4e25740bd1225f413a10db6166b620d2f5fbbb Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Thu, 7 Apr 2011 18:33:19 +0000 Subject: Add some more comments about checkings of invalid register numbers. And two test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index bc0ba92d58..f4fa3de268 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1110,6 +1110,11 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn, // A8.6.3 ADC (register-shifted register) // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + // + // This also accounts for shift instructions (register) where, fortunately, + // Inst{19-16} = 0b0000. + // A8.6.89 LSL (register) + // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; if (decodeRd(insn) == 15 || decodeRn(insn) == 15 || decodeRm(insn) == 15 || decodeRs(insn) == 15) return false; -- cgit v1.2.3-70-g09d2