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authorDuncan Sands <baldrick@free.fr>2008-07-15 10:14:24 +0000
committerDuncan Sands <baldrick@free.fr>2008-07-15 10:14:24 +0000
commit8d56a6f4d8b010d4c582225a08ece971613f6fe3 (patch)
tree596dae37856af5d347d319fad92dfe179277c88a /lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
parentbf304c20651b80309af4c0fb3a14c0d73eaa984f (diff)
LegalizeTypes support for promotion of SIGN_EXTEND_INREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53603 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 756057cf66..062e29e6ac 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -66,6 +66,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
+ case ISD::SIGN_EXTEND_INREG:
+ Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
@@ -344,6 +346,12 @@ SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
}
+SDOperand DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
+ SDOperand Op = GetPromotedInteger(N->getOperand(0));
+ return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
+ N->getOperand(1));
+}
+
SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
// The input may have strange things in the top bits of the registers, but
// these operations don't care. They may have weird bits going out, but