diff options
| author | Duncan Sands <baldrick@free.fr> | 2008-07-15 10:14:24 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2008-07-15 10:14:24 +0000 |
| commit | 8d56a6f4d8b010d4c582225a08ece971613f6fe3 (patch) | |
| tree | 596dae37856af5d347d319fad92dfe179277c88a | |
| parent | bf304c20651b80309af4c0fb3a14c0d73eaa984f (diff) | |
LegalizeTypes support for promotion of SIGN_EXTEND_INREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53603 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 8 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll | 17 |
3 files changed, 26 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 756057cf66..062e29e6ac 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -66,6 +66,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; case ISD::SHL: Result = PromoteIntRes_SHL(N); break; + case ISD::SIGN_EXTEND_INREG: + Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; case ISD::SRA: Result = PromoteIntRes_SRA(N); break; case ISD::SRL: Result = PromoteIntRes_SRL(N); break; case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; @@ -344,6 +346,12 @@ SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); } +SDOperand DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { + SDOperand Op = GetPromotedInteger(N->getOperand(0)); + return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, + N->getOperand(1)); +} + SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { // The input may have strange things in the top bits of the registers, but // these operations don't care. They may have weird bits going out, but diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 4063c97587..8e7462ff6f 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -228,6 +228,7 @@ private: SDOperand PromoteIntRes_SETCC(SDNode *N); SDOperand PromoteIntRes_SHL(SDNode *N); SDOperand PromoteIntRes_SimpleIntBinOp(SDNode *N); + SDOperand PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N); SDOperand PromoteIntRes_SRA(SDNode *N); SDOperand PromoteIntRes_SRL(SDNode *N); SDOperand PromoteIntRes_TRUNCATE(SDNode *N); diff --git a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll new file mode 100644 index 0000000000..32e36427c5 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9" + +define i16 @t(i16* %dct) signext nounwind { +entry: + load i16* null, align 2 ; <i16>:0 [#uses=2] + lshr i16 %0, 11 ; <i16>:1 [#uses=0] + trunc i16 %0 to i8 ; <i8>:2 [#uses=1] + sext i8 %2 to i16 ; <i16>:3 [#uses=1] + add i16 0, %3 ; <i16>:4 [#uses=1] + sext i16 %4 to i32 ; <i32>:5 [#uses=1] + %dcval.0.in = shl i32 %5, 0 ; <i32> [#uses=1] + %dcval.0 = trunc i32 %dcval.0.in to i16 ; <i16> [#uses=1] + store i16 %dcval.0, i16* %dct, align 2 + ret i16 0 +} |