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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-12-18 00:06:56 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-12-18 00:06:56 +0000
commit89cab93fe999f6d81b4b99a71ac797b7ecfec277 (patch)
tree7169b63cbb3a4ff4da76a8fc116a9e7d2a8521ab /lib/CodeGen/RegAllocGreedy.cpp
parent3deb45149a2eaecfc9453db2a7e840531b930cc6 (diff)
Pass a Banner argument to the machine code verifier both from
createMachineVerifierPass and MachineFunction::verify. The banner is printed before the machine code dump, just like the printer pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122113 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocGreedy.cpp')
-rw-r--r--lib/CodeGen/RegAllocGreedy.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index 8dbb56809b..12a1cfcc90 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -329,7 +329,7 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
.splitAroundLoop(Loop->getLoop());
if (VerifyEnabled)
- MF->verify(this);
+ MF->verify(this, "After splitting live range around loop");
// We have new split regs, don't assign anything.
return 0;
@@ -404,7 +404,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
if (VerifyEnabled)
- MF->verify(this);
+ MF->verify(this, "Before greedy register allocator");
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
DomTree = &getAnalysis<MachineDominatorTree>();