diff options
| author | Andrew Trick <atrick@apple.com> | 2012-03-07 05:21:36 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-03-07 05:21:36 +0000 |
| commit | 4c727204271067f3dbf50bd23098b2df8e1cc47a (patch) | |
| tree | 38df07d4b2485a2cae5ecc559b219f1b692f88b6 /lib/CodeGen/PostRASchedulerList.cpp | |
| parent | dbdca36af8ee6028dbea93c639408ba95e5fda2e (diff) | |
misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index e59aa9d51b..4c768acb54 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -703,6 +703,12 @@ void SchedulePostRATDList::ListScheduleTopDown() { } #ifndef NDEBUG - VerifySchedule(/*isBottomUp=*/false); -#endif + unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false); + unsigned Noops = 0; + for (unsigned i = 0, e = Sequence.size(); i != e; ++i) + if (!Sequence[i]) + ++Noops; + assert(Sequence.size() - Noops == ScheduledNodes && + "The number of nodes scheduled doesn't match the expected number!"); +#endif // NDEBUG } |