Constant generation instructions are re-materializable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35161 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 11 insertions, 5 deletions

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 31d923e733..cb0a508bf9 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -137,7 +137,7 @@ def so_imm_neg :
   PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
           so_imm_neg_XFORM>;
 
-def so_imm_not : 
+def so_imm_not :
   PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
           so_imm_not_XFORM>;
 
@@ -709,6 +709,8 @@ def MOVrr : AI1<(ops GPR:$dst, GPR:$src),
                 "mov $dst, $src", []>;
 def MOVrs : AI1<(ops GPR:$dst, so_reg:$src),
                 "mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
+
+let isReMaterializable = 1 in
 def MOVri : AI1<(ops GPR:$dst, so_imm:$src),
                 "mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
 
@@ -806,10 +808,13 @@ defm ORR   : AI1_bin_irs<"orr", BinOpFrag<(or  node:$LHS, node:$RHS)>>;
 defm EOR   : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
 defm BIC   : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
 
-defm MVN   : AI1_unary_irs<"mvn", not>;
-
-def : ARMPat<(i32  so_imm_not:$imm),
-             (MVNi so_imm_not:$imm)>;
+def  MVNr  : AI<(ops GPR:$dst, GPR:$src),
+                "mvn $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
+def  MVNs  : AI<(ops GPR:$dst, so_reg:$src),
+                "mvn $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
+let isReMaterializable = 1 in
+def  MVNi  : AI<(ops GPR:$dst, so_imm:$imm),
+                "mvn $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
 
 def : ARMPat<(and   GPR:$src, so_imm_not:$imm),
              (BICri GPR:$src, so_imm_not:$imm)>;
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 59a0098f44..6b289d9a05 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -374,6 +374,7 @@ def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
                  "lsr $dst, $rhs",
                  [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
 
+let isReMaterializable = 1 in
 def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src),
                  "mov $dst, $src",
                  [(set GPR:$dst, imm0_255:$src)]>;