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authorEvan Cheng <evan.cheng@apple.com>2007-03-19 06:22:07 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-03-19 06:22:07 +0000
commite2e9e44d8ff4a37004cd727036c966b8550d6a8d (patch)
tree1b176466dbbf1ac570dfc187a8293eace310a3b1
parent04677a3b49b2dfb151c4f77345702da489293627 (diff)
Added isReMaterializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35160 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/Target.td1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index fbc972a292..b1ef5c9357 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -165,6 +165,7 @@ class Instruction {
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
+ bit isReMaterializable = 0; // Is this instruction re-materializable?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?