Check in some intermediate code that adds a skeleton for matching vsplt*

instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26894 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 28 insertions, 4 deletions

diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index 1e883001a6..e4e9e68304 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -82,7 +82,19 @@ namespace llvm {
       /// Return with a flag operand, matched by 'blr'
       RET_FLAG,
     };
-  }  
+  }
+
+  /// Define some predicates that are used for node matching.
+  namespace PPC {
+    /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
+    /// specifies a splat of a single element that is suitable for input to
+    /// VSPLTB/VSPLTH/VSPLTW.
+    bool isSplatShuffleMask(SDNode *N) { return false; } // FIXME:
+    
+    /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
+    /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
+    unsigned getVSPLTImmediate(SDNode *N) { return 0; }  // FIXME:
+  }
   
   class PPCTargetLowering : public TargetLowering {
     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 32bbfbf639..2e63119c9c 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -123,6 +123,14 @@ def imm16Shifted : PatLeaf<(imm), [{
   return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
 }], HI16>;
 
+// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
+def VSPLT_get_imm : SDNodeXForm<build_vector, [{
+  return getI32Imm(PPC::getVSPLTImmediate(N));
+}]>;
+
+def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
+  return PPC::isSplatShuffleMask(N);
+}], VSPLT_get_imm>;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Flag Definitions.
@@ -937,6 +945,7 @@ def RLDICR : MDForm_1<30, 1,
                       []>, isPPC64;
 }
 
+
 let PPC970_Unit = 5 in {  // VALU Operations.
 // VA-Form instructions.  3-input AltiVec ops.
 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
@@ -1022,9 +1031,11 @@ def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vsplth $vD, $vB, $UIMM", VecPerm,
                       []>;
-def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
-                      "vspltw $vD, $vB, $UIMM", VecPerm,
-                      []>;
+                      
+//def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+//                      "vspltw $vD, $vB, $UIMM", VecPerm,
+//                      [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
+//                                      VSPLT_shuffle_mask:$UIMM))]>;
                       
 // VX-Form Pseudo Instructions
 
@@ -1033,6 +1044,7 @@ def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
                       []>;
 }
 
+
 //===----------------------------------------------------------------------===//
 // DWARF Pseudo Instructions
 //