diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
40 files changed, 7000 insertions, 11037 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index 96ea09ca8cc..0705df77520 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -3,22 +3,25 @@ # # CPU subtype setup +obj-$(CONFIG_CPU_SUBTYPE_SH7757) += setup-sh7757.o obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o -obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o +obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o -obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o +obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o +obj-$(CONFIG_CPU_SUBTYPE_SH7734) += setup-sh7734.o obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o -obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o +obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o # SMP setup -smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o +smp-$(CONFIG_CPU_SHX3) := smp-shx3.o # Primary on-chip clocks (common) +clock-$(CONFIG_CPU_SUBTYPE_SH7757) := clock-sh7757.o clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o @@ -28,6 +31,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o +clock-$(CONFIG_CPU_SUBTYPE_SH7734) := clock-sh7734.o clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o @@ -35,9 +39,14 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o +pinmux-$(CONFIG_CPU_SUBTYPE_SH7734) := pinmux-sh7734.o +pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o +pinmux-$(CONFIG_CPU_SUBTYPE_SHX3) := pinmux-shx3.o -obj-y += $(clock-y) -obj-$(CONFIG_SMP) += $(smp-y) -obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) +obj-y += $(clock-y) +obj-$(CONFIG_SMP) += $(smp-y) +obj-$(CONFIG_GPIOLIB) += $(pinmux-y) +obj-$(CONFIG_PERF_EVENTS) += perf_event.o +obj-$(CONFIG_HAVE_HW_BREAKPOINT) += ubc.o diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c index 0ee3ee86125..9edc06c02dc 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c @@ -21,6 +21,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/io.h> +#include <linux/clkdev.h> #include <asm/clock.h> /* SH7343 registers */ @@ -36,8 +37,6 @@ /* Fixed 32 KHz root clock for RTC and Power Management purposes */ static struct clk r_clk = { - .name = "rclk", - .id = -1, .rate = 32768, }; @@ -46,8 +45,6 @@ static struct clk r_clk = { * from the platform code. */ struct clk extal_clk = { - .name = "extal", - .id = -1, .rate = 33333333, }; @@ -64,13 +61,11 @@ static unsigned long dll_recalc(struct clk *clk) return clk->parent->rate * mult; } -static struct clk_ops dll_clk_ops = { +static struct sh_clk_ops dll_clk_ops = { .recalc = dll_recalc, }; static struct clk dll_clk = { - .name = "dll_clk", - .id = -1, .ops = &dll_clk_ops, .parent = &r_clk, .flags = CLK_ENABLE_ON_INIT, @@ -86,13 +81,11 @@ static unsigned long pll_recalc(struct clk *clk) return clk->parent->rate * mult; } -static struct clk_ops pll_clk_ops = { +static struct sh_clk_ops pll_clk_ops = { .recalc = pll_recalc, }; static struct clk pll_clk = { - .name = "pll_clk", - .id = -1, .ops = &pll_clk_ops, .flags = CLK_ENABLE_ON_INIT, }; @@ -107,82 +100,165 @@ struct clk *main_clks[] = { static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; -static struct clk_div_mult_table div4_table = { +static struct clk_div_mult_table div4_div_mult_table = { .divisors = divisors, .nr_divisors = ARRAY_SIZE(divisors), .multipliers = multipliers, .nr_multipliers = ARRAY_SIZE(multipliers), }; +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_SIUA, DIV4_SIUB, DIV4_NR }; -#define DIV4(_str, _reg, _bit, _mask, _flags) \ - SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), - [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), - [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), + [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), + [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), + [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), }; -struct clk div6_clks[] = { - SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), +enum { DIV6_V, DIV6_NR }; + +struct clk div6_clks[DIV6_NR] = { + [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), }; -#define MSTP(_str, _parent, _reg, _bit, _flags) \ - SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) - -static struct clk mstp_clks[] = { - MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), - MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), - MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), - MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), - MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), - MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), - MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), - MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), - MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), - MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), - MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), - MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), - MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), - MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), - MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), - MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), - MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), - MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), - MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), - MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0), - MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), - MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), - MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), - - MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), - MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0), - - MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0), - MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0), - MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), - MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), - MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0), - MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), - MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0), - MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0), - MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), - MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), - MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), - MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), - MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), - MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), - MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), - MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), - MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), +#define MSTP(_parent, _reg, _bit, _flags) \ + SH_CLK_MSTP32(_parent, _reg, _bit, _flags) + +enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026, + MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016, + MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010, + MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001, + MSTP109, MSTP108, MSTP100, + MSTP225, MSTP224, MSTP218, MSTP217, MSTP216, + MSTP214, MSTP213, MSTP212, MSTP211, MSTP208, + MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), + [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), + [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), + [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), + [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), + [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), + [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), + [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), + [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), + [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), + [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), + [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), + [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0), + [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0), + [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), + [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), + [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), + [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), + [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), + [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0), + [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0), + [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), + [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), + + [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), + [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0), + + [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0), + [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), + [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), + [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), + [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0), + [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0), + [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0), + [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0), + [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), + [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0), + [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), + [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), + [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), + [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), + [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), + [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), + [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("rclk", &r_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("dll_clk", &dll_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]), + CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), + + /* MSTP32 clocks */ + CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]), + CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]), + CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]), + CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]), + CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]), + CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]), + CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]), + CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]), + CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]), + CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]), + CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]), + CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]), + CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[MSTP014]), + CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]), + CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]), + CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]), + + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP007]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP006]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP005]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP004]), + + CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]), + CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]), + CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]), + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP109]), + CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP108]), + CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]), + CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]), + CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]), + CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]), + CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]), + CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]), + CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]), + CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]), + CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]), + CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]), + CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]), + CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]), + CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]), + CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]), + CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]), + CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]), + CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]), }; int __init arch_clk_init(void) @@ -198,14 +274,16 @@ int __init arch_clk_init(void) for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) - ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); + ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c index a95ebaba095..955b9add781 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c @@ -21,6 +21,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/io.h> +#include <linux/clkdev.h> #include <asm/clock.h> /* SH7366 registers */ @@ -36,8 +37,6 @@ /* Fixed 32 KHz root clock for RTC and Power Management purposes */ static struct clk r_clk = { - .name = "rclk", - .id = -1, .rate = 32768, }; @@ -46,8 +45,6 @@ static struct clk r_clk = { * from the platform code. */ struct clk extal_clk = { - .name = "extal", - .id = -1, .rate = 33333333, }; @@ -64,13 +61,11 @@ static unsigned long dll_recalc(struct clk *clk) return clk->parent->rate * mult; } -static struct clk_ops dll_clk_ops = { +static struct sh_clk_ops dll_clk_ops = { .recalc = dll_recalc, }; static struct clk dll_clk = { - .name = "dll_clk", - .id = -1, .ops = &dll_clk_ops, .parent = &r_clk, .flags = CLK_ENABLE_ON_INIT, @@ -89,13 +84,11 @@ static unsigned long pll_recalc(struct clk *clk) return (clk->parent->rate * mult) / div; } -static struct clk_ops pll_clk_ops = { +static struct sh_clk_ops pll_clk_ops = { .recalc = pll_recalc, }; static struct clk pll_clk = { - .name = "pll_clk", - .id = -1, .ops = &pll_clk_ops, .flags = CLK_ENABLE_ON_INIT, }; @@ -110,79 +103,155 @@ struct clk *main_clks[] = { static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; -static struct clk_div_mult_table div4_table = { +static struct clk_div_mult_table div4_div_mult_table = { .divisors = divisors, .nr_divisors = ARRAY_SIZE(divisors), .multipliers = multipliers, .nr_multipliers = ARRAY_SIZE(multipliers), }; +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_SIUA, DIV4_SIUB, DIV4_NR }; -#define DIV4(_str, _reg, _bit, _mask, _flags) \ - SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), - [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), - [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), - [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), + [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), + [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), + [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), + [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), }; -struct clk div6_clks[] = { - SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), +enum { DIV6_V, DIV6_NR }; + +struct clk div6_clks[DIV6_NR] = { + [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), }; -#define MSTP(_str, _parent, _reg, _bit, _flags) \ - SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) +#define MSTP(_parent, _reg, _bit, _flags) \ + SH_CLK_MSTP32(_parent, _reg, _bit, _flags) + +enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026, + MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016, + MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010, + MSTP007, MSTP006, MSTP005, MSTP002, MSTP001, + MSTP109, MSTP100, + MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217, + MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, + MSTP_NR }; -static struct clk mstp_clks[] = { +static struct clk mstp_clks[MSTP_NR] = { /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ - MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), - MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), - MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), - MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), - MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), - MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), - MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), - MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), - MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), - MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), - MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), - MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), - MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), - MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), - MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), - MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), - MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), - MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), - MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), - MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), - MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), - - MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), - - MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0), - MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0), - MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0), - MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0), - MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0), - MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), - MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), - MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), - MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), - MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), - MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), - MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), - MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), - MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), - MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), - MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), + [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), + [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), + [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), + [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), + [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), + [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), + [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), + [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), + [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), + [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), + [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), + [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), + [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0), + [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0), + [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), + [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), + [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), + [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), + [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), + [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), + [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), + + [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), + + [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0), + [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0), + [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), + [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0), + [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0), + [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), + [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), + [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), + [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), + [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), + [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), + [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), + [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), + [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), + [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("rclk", &r_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("dll_clk", &dll_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]), + CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), + + /* MSTP32 clocks */ + CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]), + CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]), + CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]), + CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]), + CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]), + CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]), + CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]), + CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]), + CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]), + CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]), + CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]), + CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]), + CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[MSTP014]), + CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]), + CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]), + CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]), + + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP007]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP006]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP005]), + + CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]), + CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]), + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP109]), + CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]), + CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]), + CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]), + CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]), + CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]), + CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]), + CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]), + CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]), + CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]), + CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]), + CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]), + CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]), + CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]), + CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]), + CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]), }; int __init arch_clk_init(void) @@ -198,14 +267,16 @@ int __init arch_clk_init(void) for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) - ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); + ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index 40f859354f7..8f07a1a3869 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c @@ -21,7 +21,10 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/io.h> +#include <linux/clkdev.h> +#include <linux/sh_clk.h> #include <asm/clock.h> +#include <cpu/sh7722.h> /* SH7722 registers */ #define FRQCR 0xa4150000 @@ -37,8 +40,6 @@ /* Fixed 32 KHz root clock for RTC and Power Management purposes */ static struct clk r_clk = { - .name = "rclk", - .id = -1, .rate = 32768, }; @@ -47,8 +48,6 @@ static struct clk r_clk = { * from the platform code. */ struct clk extal_clk = { - .name = "extal", - .id = -1, .rate = 33333333, }; @@ -65,13 +64,11 @@ static unsigned long dll_recalc(struct clk *clk) return clk->parent->rate * mult; } -static struct clk_ops dll_clk_ops = { +static struct sh_clk_ops dll_clk_ops = { .recalc = dll_recalc, }; static struct clk dll_clk = { - .name = "dll_clk", - .id = -1, .ops = &dll_clk_ops, .parent = &r_clk, .flags = CLK_ENABLE_ON_INIT, @@ -90,13 +87,11 @@ static unsigned long pll_recalc(struct clk *clk) return (clk->parent->rate * mult) / div; } -static struct clk_ops pll_clk_ops = { +static struct sh_clk_ops pll_clk_ops = { .recalc = pll_recalc, }; static struct clk pll_clk = { - .name = "pll_clk", - .id = -1, .ops = &pll_clk_ops, .flags = CLK_ENABLE_ON_INIT, }; @@ -111,64 +106,127 @@ struct clk *main_clks[] = { static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; -static struct clk_div_mult_table div4_table = { +static struct clk_div_mult_table div4_div_mult_table = { .divisors = divisors, .nr_divisors = ARRAY_SIZE(divisors), .multipliers = multipliers, .nr_multipliers = ARRAY_SIZE(multipliers), }; -enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, - DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR }; +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) -#define DIV4(_str, _reg, _bit, _mask, _flags) \ - SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) +enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), - [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), - [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), - [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), - [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), - [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0), + [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), + [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), + [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), }; -struct clk div6_clks[] = { - SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), +enum { DIV4_IRDA, DIV4_ENABLE_NR }; + +struct clk div4_enable_clks[DIV4_ENABLE_NR] = { + [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0), }; -#define MSTP(_str, _parent, _reg, _bit, _flags) \ - SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) - -static struct clk mstp_clks[] = { - MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), - MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), - MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), - MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), - MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), - MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), - MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), - MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), - MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), - - MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), - MSTP("rtc0", &r_clk, MSTPCR1, 8, 0), - - MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), - MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), - MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), - MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), - MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), - MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), - MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), - MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), - MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), - MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), - MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), - MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), +enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; + +struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { + [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), + [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), +}; + +enum { DIV6_V, DIV6_NR }; + +struct clk div6_clks[DIV6_NR] = { + [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), +}; + +static struct clk mstp_clks[HWBLK_NR] = { + [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), + [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), + [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), + [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), + [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), + [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), + [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), + [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0), + [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), + + [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), + [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0), + + [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0), + [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), + [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0), + [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), + [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), + [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), + [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), + [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), + [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), + [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), + [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), + [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0), +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("rclk", &r_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("dll_clk", &dll_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]), + CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]), + CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), + + /* MSTP clocks */ + CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]), + CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]), + + CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[HWBLK_TMU]), + + CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[HWBLK_CMT]), + CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]), + CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), + + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]), + + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), + CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI]), + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]), + CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]), + CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), + CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]), + CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]), + CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), + CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), + CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]), + CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]), + CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]), }; int __init arch_clk_init(void) @@ -184,14 +242,24 @@ int __init arch_clk_init(void) for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) - ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); + ret = sh_clk_div4_enable_register(div4_enable_clks, + DIV4_ENABLE_NR, &div4_table); + + if (!ret) + ret = sh_clk_div4_reparent_register(div4_reparent_clks, + DIV4_REPARENT_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); + ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c index e67c2678b8a..ccbcab550df 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c @@ -21,7 +21,11 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/io.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/sh_clk.h> #include <asm/clock.h> +#include <cpu/sh7723.h> /* SH7723 registers */ #define FRQCR 0xa4150000 @@ -37,8 +41,6 @@ /* Fixed 32 KHz root clock for RTC and Power Management purposes */ static struct clk r_clk = { - .name = "rclk", - .id = -1, .rate = 32768, }; @@ -47,8 +49,6 @@ static struct clk r_clk = { * from the platform code. */ struct clk extal_clk = { - .name = "extal", - .id = -1, .rate = 33333333, }; @@ -65,13 +65,11 @@ static unsigned long dll_recalc(struct clk *clk) return clk->parent->rate * mult; } -static struct clk_ops dll_clk_ops = { +static struct sh_clk_ops dll_clk_ops = { .recalc = dll_recalc, }; static struct clk dll_clk = { - .name = "dll_clk", - .id = -1, .ops = &dll_clk_ops, .parent = &r_clk, .flags = CLK_ENABLE_ON_INIT, @@ -90,13 +88,11 @@ static unsigned long pll_recalc(struct clk *clk) return (clk->parent->rate * mult) / div; } -static struct clk_ops pll_clk_ops = { +static struct sh_clk_ops pll_clk_ops = { .recalc = pll_recalc, }; static struct clk pll_clk = { - .name = "pll_clk", - .id = -1, .ops = &pll_clk_ops, .flags = CLK_ENABLE_ON_INIT, }; @@ -111,89 +107,174 @@ struct clk *main_clks[] = { static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; -static struct clk_div_mult_table div4_table = { +static struct clk_div_mult_table div4_div_mult_table = { .divisors = divisors, .nr_divisors = ARRAY_SIZE(divisors), .multipliers = multipliers, .nr_multipliers = ARRAY_SIZE(multipliers), }; -enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, - DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR }; +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; -#define DIV4(_str, _reg, _bit, _mask, _flags) \ - SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), - [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), - [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), - [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), - [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), - [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0), - [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0), - [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0), - [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0), + [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), + [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), + [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), + [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0), }; -struct clk div6_clks[] = { - SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), +enum { DIV4_IRDA, DIV4_ENABLE_NR }; + +struct clk div4_enable_clks[DIV4_ENABLE_NR] = { + [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0), }; -#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \ - SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT) +enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; + +struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { + [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0), + [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0), +}; +enum { DIV6_V, DIV6_NR }; + +struct clk div6_clks[DIV6_NR] = { + [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), +}; static struct clk mstp_clks[] = { /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ - MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0), - MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0), - MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0), - MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 28, 1, 1, 0), - MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0), - MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0), - MSTP("intc0", &div4_clks[DIV4_I], MSTPCR0, 22, 1, 1, 0), - MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1), - MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0), - MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0), - MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0), - MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0), - MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0), - MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0), - MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1), - MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 11, 0, 1, 0), - MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0), - MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0), - MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0), - MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0), - MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0), - MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0), - MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0), - MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0), - MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0), - MSTP("meram0", &div4_clks[DIV4_SH], MSTPCR0, 0, 1, 1, 0), - - MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0), - MSTP("rtc0", &r_clk, MSTPCR1, 8, 0, 0, 0), - - MSTP("atapi0", &div4_clks[DIV4_SH], MSTPCR2, 28, 0, 1, 0), - MSTP("adc0", &div4_clks[DIV4_P], MSTPCR2, 27, 0, 1, 0), - MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0), - MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0), - MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0), - MSTP("icb0", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1), - MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0), - MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0), - MSTP("keysc0", &r_clk, MSTPCR2, 14, 0, 0, 0), - MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 11, 0, 1, 0), - MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 10, 0, 1, 1), - MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0, 1, 0), - MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1), - MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1), - MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1), - MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1), - MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1), - MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1), - MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1), + [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), + [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), + [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), + [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), + [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), + [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), + [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT), + [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), + [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), + [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), + [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0), + [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), + [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), + [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), + [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), + [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), + [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), + [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), + [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), + [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), + [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), + [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), + [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), + [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), + [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), + [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0), + + [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), + [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0), + + [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0), + [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0), + [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), + [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), + [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), + [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT), + [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), + [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), + [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), + [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0), + [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0), + [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), + [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), + [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), + [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), + [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), + [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), + [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), + [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("rclk", &r_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("dll_clk", &dll_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]), + CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]), + CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), + + /* MSTP clocks */ + CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]), + CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]), + CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]), + CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), + CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), + CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), + CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]), + CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), + CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), + CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), + CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[HWBLK_CMT]), + CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]), + CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]), + CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), + CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]), + CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]), + CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[HWBLK_MERAM]), + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), + CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), + CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), + CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]), + CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), + CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), + CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), + CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]), + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]), + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]), + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]), + CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]), + CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), + CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]), + CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]), + CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]), + CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), + CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]), + CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]), + CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), + + CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[HWBLK_TMU0]), + CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[HWBLK_TMU1]), + + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]), + + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]), }; int __init arch_clk_init(void) @@ -207,16 +288,26 @@ int __init arch_clk_init(void) pll_clk.parent = &extal_clk; for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); + ret |= clk_register(main_clks[k]); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) - ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); + ret = sh_clk_div4_enable_register(div4_enable_clks, + DIV4_ENABLE_NR, &div4_table); + + if (!ret) + ret = sh_clk_div4_reparent_register(div4_reparent_clks, + DIV4_REPARENT_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); + ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c index 5d5c9b95288..f579dd52819 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c @@ -21,7 +21,11 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/io.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/sh_clk.h> #include <asm/clock.h> +#include <cpu/sh7724.h> /* SH7724 registers */ #define FRQCRA 0xa4150000 @@ -40,8 +44,6 @@ /* Fixed 32 KHz root clock for RTC and Power Management purposes */ static struct clk r_clk = { - .name = "rclk", - .id = -1, .rate = 32768, }; @@ -49,9 +51,7 @@ static struct clk r_clk = { * Default rate for the root input clock, reset this with clk_set_rate() * from the platform code. */ -struct clk extal_clk = { - .name = "extal", - .id = -1, +static struct clk extal_clk = { .rate = 33333333, }; @@ -70,13 +70,11 @@ static unsigned long fll_recalc(struct clk *clk) return (clk->parent->rate * mult) / div; } -static struct clk_ops fll_clk_ops = { +static struct sh_clk_ops fll_clk_ops = { .recalc = fll_recalc, }; static struct clk fll_clk = { - .name = "fll_clk", - .id = -1, .ops = &fll_clk_ops, .parent = &r_clk, .flags = CLK_ENABLE_ON_INIT, @@ -92,13 +90,11 @@ static unsigned long pll_recalc(struct clk *clk) return clk->parent->rate * mult; } -static struct clk_ops pll_clk_ops = { +static struct sh_clk_ops pll_clk_ops = { .recalc = pll_recalc, }; static struct clk pll_clk = { - .name = "pll_clk", - .id = -1, .ops = &pll_clk_ops, .flags = CLK_ENABLE_ON_INIT, }; @@ -109,111 +105,248 @@ static unsigned long div3_recalc(struct clk *clk) return clk->parent->rate / 3; } -static struct clk_ops div3_clk_ops = { +static struct sh_clk_ops div3_clk_ops = { .recalc = div3_recalc, }; static struct clk div3_clk = { - .name = "div3_clk", - .id = -1, .ops = &div3_clk_ops, .parent = &pll_clk, }; -struct clk *main_clks[] = { +/* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */ +struct clk sh7724_fsimcka_clk = { +}; + +struct clk sh7724_fsimckb_clk = { +}; + +struct clk sh7724_dv_clki = { +}; + +static struct clk *main_clks[] = { &r_clk, &extal_clk, &fll_clk, &pll_clk, &div3_clk, + &sh7724_fsimcka_clk, + &sh7724_fsimckb_clk, + &sh7724_dv_clki, }; -static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; +static void div4_kick(struct clk *clk) +{ + unsigned long value; + + /* set KICK bit in FRQCRA to update hardware setting */ + value = __raw_readl(FRQCRA); + value |= (1 << 31); + __raw_writel(value, FRQCRA); +} + +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; -static struct clk_div_mult_table div4_table = { +static struct clk_div_mult_table div4_div_mult_table = { .divisors = divisors, .nr_divisors = ARRAY_SIZE(divisors), }; +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, + .kick = div4_kick, +}; + enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; -#define DIV4(_str, _reg, _bit, _mask, _flags) \ - SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), - [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), - [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), - [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), - [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0), -}; - -struct clk div6_clks[] = { - SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0), - SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0), - SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0), - SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0), - SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0), -}; - -#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \ - SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT) - -static struct clk mstp_clks[] = { - MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0), - MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0), - MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0), - MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0), - MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0), - MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0), - MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0), - MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0), - MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1), - MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0), - MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0), - MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0), - MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0), - MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0), - MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0), - MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1), - MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0), - MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0), - MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0), - MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0), - MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0), - MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0), - MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0), - MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0), - MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0), - - MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0), - MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0), - MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0), - MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0), - - MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0), - MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0), - MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0), - MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0), - MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0), - MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0), - MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1), - MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1), - MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1), - MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0), - MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0), - MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1), - MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1), - MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1), - MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1), - MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0), - MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1), - MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1), - MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1), - MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1), - MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1), - MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1), - MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1), + [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), + [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), + [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), +}; + +enum { DIV6_V, DIV6_I, DIV6_S, DIV6_FA, DIV6_FB, DIV6_NR }; + +/* Indices are important - they are the actual src selecting values */ +static struct clk *common_parent[] = { + [0] = &div3_clk, + [1] = NULL, +}; + +static struct clk *vclkcr_parent[8] = { + [0] = &div3_clk, + [2] = &sh7724_dv_clki, + [4] = &extal_clk, +}; + +static struct clk *fclkacr_parent[] = { + [0] = &div3_clk, + [1] = NULL, + [2] = &sh7724_fsimcka_clk, + [3] = NULL, +}; + +static struct clk *fclkbcr_parent[] = { + [0] = &div3_clk, + [1] = NULL, + [2] = &sh7724_fsimckb_clk, + [3] = NULL, +}; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_V] = SH_CLK_DIV6_EXT(VCLKCR, 0, + vclkcr_parent, ARRAY_SIZE(vclkcr_parent), 12, 3), + [DIV6_I] = SH_CLK_DIV6_EXT(IRDACLKCR, 0, + common_parent, ARRAY_SIZE(common_parent), 6, 1), + [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT, + common_parent, ARRAY_SIZE(common_parent), 6, 1), + [DIV6_FA] = SH_CLK_DIV6_EXT(FCLKACR, 0, + fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2), + [DIV6_FB] = SH_CLK_DIV6_EXT(FCLKBCR, 0, + fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2), +}; + +static struct clk mstp_clks[HWBLK_NR] = { + [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), + [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), + [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), + [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT), + [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), + [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT), + [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), + [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT), + [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), + [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), + [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), + [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0), + [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), + [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), + [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), + [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), + [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), + [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), + [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), + [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), + [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), + [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), + [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), + [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), + [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), + + [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0), + [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0), + [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), + [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), + + [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0), + [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0), + [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0), + [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), + [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), + [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), + [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0), + [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0), + [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0), + [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), + [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), + [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0), + [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0), + [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0), + [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0), + [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), + [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), + [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), + [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), + [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), + [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), + [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), + [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("rclk", &r_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("fll_clk", &fll_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + CLKDEV_CON_ID("div3_clk", &div3_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), + CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), + CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]), + CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), + CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), + + /* MSTP clocks */ + CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]), + CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]), + CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]), + CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]), + CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), + CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), + CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), + CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]), + CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), + CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), + CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), + + CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[HWBLK_TMU0]), + CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[HWBLK_TMU1]), + + CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[HWBLK_CMT]), + CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]), + CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]), + + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]), + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]), + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]), + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]), + + CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]), + CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]), + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]), + CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]), + CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]), + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[HWBLK_MMC]), + CLKDEV_DEV_ID("sh7724-ether.0", &mstp_clks[HWBLK_ETHER]), + CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), + CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), + CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), + CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), + CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[HWBLK_USB1]), + CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[HWBLK_USB0]), + CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]), + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]), + CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), + CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[HWBLK_CEU1]), + CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), + CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), + CLKDEV_DEV_ID("sh_fsi.0", &mstp_clks[HWBLK_SPU]), + CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), + CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]), + CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), + CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU0]), + CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), + CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]), }; int __init arch_clk_init(void) @@ -229,14 +362,16 @@ int __init arch_clk_init(void) for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) - ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); + ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); + ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7734.c b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c new file mode 100644 index 00000000000..1fdf1ee672d --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c @@ -0,0 +1,260 @@ +/* + * arch/sh/kernel/cpu/sh4a/clock-sh7734.c + * + * Clock framework for SH7734 + * + * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * Copyright (C) 2011, 2012 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/clkdev.h> +#include <linux/delay.h> +#include <asm/clock.h> +#include <asm/freq.h> + +static struct clk extal_clk = { + .rate = 33333333, +}; + +#define MODEMR (0xFFCC0020) +#define MODEMR_MASK (0x6) +#define MODEMR_533MHZ (0x2) + +static unsigned long pll_recalc(struct clk *clk) +{ + int mode = 12; + u32 r = __raw_readl(MODEMR); + + if ((r & MODEMR_MASK) & MODEMR_533MHZ) + mode = 16; + + return clk->parent->rate * mode; +} + +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, +}; + +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +static struct clk *main_clks[] = { + &extal_clk, + &pll_clk, +}; + +static int multipliers[] = { 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; +static int divisors[] = { 1, 3, 2, 3, 4, 6, 8, 9, 12, 16, 18, 24 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), + .multipliers = multipliers, + .nr_multipliers = ARRAY_SIZE(multipliers), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR }; + +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) + +struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT), + [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT), + [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT), + [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT), + [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT), +}; + +#define MSTPCR0 0xFFC80030 +#define MSTPCR1 0xFFC80034 +#define MSTPCR3 0xFFC8003C + +enum { + MSTP030, MSTP029, /* IIC */ + MSTP026, MSTP025, MSTP024, /* SCIF */ + MSTP023, + MSTP022, MSTP021, + MSTP019, /* HSCIF */ + MSTP016, MSTP015, MSTP014, /* TMU / TIMER */ + MSTP012, MSTP011, MSTP010, MSTP009, MSTP008, /* SSI */ + MSTP007, /* HSPI */ + MSTP115, /* ADMAC */ + MSTP114, /* GETHER */ + MSTP111, /* DMAC */ + MSTP109, /* VIDEOIN1 */ + MSTP108, /* VIDEOIN0 */ + MSTP107, /* RGPVBG */ + MSTP106, /* 2DG */ + MSTP103, /* VIEW */ + MSTP100, /* USB */ + MSTP331, /* MMC */ + MSTP330, /* MIMLB */ + MSTP323, /* SDHI0 */ + MSTP322, /* SDHI1 */ + MSTP321, /* SDHI2 */ + MSTP320, /* RQSPI */ + MSTP319, /* SRC0 */ + MSTP318, /* SRC1 */ + MSTP317, /* RSPI */ + MSTP316, /* RCAN0 */ + MSTP315, /* RCAN1 */ + MSTP314, /* FLTCL */ + MSTP313, /* ADC */ + MSTP312, /* MTU */ + MSTP304, /* IE-BUS */ + MSTP303, /* RTC */ + MSTP302, /* HIF */ + MSTP301, /* STIF0 */ + MSTP300, /* STIF1 */ + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + /* MSTPCR0 */ + [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), + [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), + [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), + [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), + [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), + [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), + [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), + [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), + [MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), + [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), + [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), + [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), + [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), + [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), + [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), + [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), + [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), + [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), + + /* MSTPCR1 */ + [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), + [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), + [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), + [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), + [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), + [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0), + [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0), + [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), + [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), + + /* MSTPCR3 */ + [MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0), + [MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0), + [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), + [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), + [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), + [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), + [MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0), + [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0), + [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0), + [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0), + [MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0), + [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0), + [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0), + [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0), + [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 4, 0), + [MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 3, 0), + [MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 2, 0), + [MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 1, 0), + [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 0, 0), +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* clocks */ + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), + CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + + /* MSTP32 clocks */ + CLKDEV_DEV_ID("i2c-sh7734.0", &mstp_clks[MSTP030]), + CLKDEV_DEV_ID("i2c-sh7734.1", &mstp_clks[MSTP029]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP026]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP024]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP023]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP022]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP021]), + CLKDEV_CON_ID("hscif", &mstp_clks[MSTP019]), + CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]), + CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]), + CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP014]), + CLKDEV_CON_ID("ssi0", &mstp_clks[MSTP012]), + CLKDEV_CON_ID("ssi1", &mstp_clks[MSTP011]), + CLKDEV_CON_ID("ssi2", &mstp_clks[MSTP010]), + CLKDEV_CON_ID("ssi3", &mstp_clks[MSTP009]), + CLKDEV_CON_ID("sss", &mstp_clks[MSTP008]), + CLKDEV_CON_ID("hspi", &mstp_clks[MSTP007]), + CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP100]), + CLKDEV_CON_ID("videoin0", &mstp_clks[MSTP109]), + CLKDEV_CON_ID("videoin1", &mstp_clks[MSTP108]), + CLKDEV_CON_ID("rgpvg", &mstp_clks[MSTP107]), + CLKDEV_CON_ID("2dg", &mstp_clks[MSTP106]), + CLKDEV_CON_ID("view", &mstp_clks[MSTP103]), + + CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP331]), + CLKDEV_CON_ID("mimlb0", &mstp_clks[MSTP330]), + CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP323]), + CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP322]), + CLKDEV_CON_ID("sdhi2", &mstp_clks[MSTP321]), + CLKDEV_CON_ID("rqspi0", &mstp_clks[MSTP320]), + CLKDEV_CON_ID("src0", &mstp_clks[MSTP319]), + CLKDEV_CON_ID("src1", &mstp_clks[MSTP318]), + CLKDEV_CON_ID("rsp0", &mstp_clks[MSTP317]), + CLKDEV_CON_ID("rcan0", &mstp_clks[MSTP316]), + CLKDEV_CON_ID("rcan1", &mstp_clks[MSTP315]), + CLKDEV_CON_ID("fltcl0", &mstp_clks[MSTP314]), + CLKDEV_CON_ID("adc0", &mstp_clks[MSTP313]), + CLKDEV_CON_ID("mtu0", &mstp_clks[MSTP312]), + CLKDEV_CON_ID("iebus0", &mstp_clks[MSTP304]), + CLKDEV_DEV_ID("sh7734-gether.0", &mstp_clks[MSTP114]), + CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP303]), + CLKDEV_CON_ID("hif0", &mstp_clks[MSTP302]), + CLKDEV_CON_ID("stif0", &mstp_clks[MSTP301]), + CLKDEV_CON_ID("stif1", &mstp_clks[MSTP300]), +}; + +int __init arch_clk_init(void) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(main_clks); i++) + ret |= clk_register(main_clks[i]); + + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), + &div4_table); + + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + return ret; +} diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c new file mode 100644 index 00000000000..9a28fdb3638 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c @@ -0,0 +1,155 @@ +/* + * arch/sh/kernel/cpu/sh4/clock-sh7757.c + * + * SH7757 support for the clock framework + * + * Copyright (C) 2009-2010 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/clkdev.h> +#include <asm/clock.h> +#include <asm/freq.h> + +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk extal_clk = { + .rate = 48000000, +}; + +static unsigned long pll_recalc(struct clk *clk) +{ + int multiplier; + + multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16; + + return clk->parent->rate * multiplier; +} + +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, +}; + +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +static struct clk *clks[] = { + &extal_clk, + &pll_clk, +}; + +static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6, + 1, 1, 1, 16, 1, 24, 1, 1 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = div2, + .nr_divisors = ARRAY_SIZE(div2), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR }; + +#define DIV4(_bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags) + +struct clk div4_clks[DIV4_NR] = { + /* + * P clock is always enable, because some P clock modules is used + * by Host PC. + */ + [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT), + [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT), +}; + +#define MSTPCR0 0xffc80030 +#define MSTPCR1 0xffc80034 +#define MSTPCR2 0xffc10028 + +enum { MSTP004, MSTP000, MSTP127, MSTP114, MSTP113, MSTP112, + MSTP111, MSTP110, MSTP103, MSTP102, MSTP220, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + /* MSTPCR0 */ + [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), + [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), + + /* MSTPCR1 */ + [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0), + [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), + [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0), + [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0), + [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), + [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0), + [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), + [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0), + + /* MSTPCR2 */ + [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0), +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + + /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP004]), + CLKDEV_CON_ID("riic0", &mstp_clks[MSTP000]), + CLKDEV_CON_ID("riic1", &mstp_clks[MSTP000]), + CLKDEV_CON_ID("riic2", &mstp_clks[MSTP000]), + CLKDEV_CON_ID("riic3", &mstp_clks[MSTP000]), + CLKDEV_CON_ID("riic4", &mstp_clks[MSTP000]), + CLKDEV_CON_ID("riic5", &mstp_clks[MSTP000]), + CLKDEV_CON_ID("riic6", &mstp_clks[MSTP000]), + CLKDEV_CON_ID("riic7", &mstp_clks[MSTP000]), + + CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP113]), + CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP114]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP112]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP111]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP110]), + + CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]), + CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]), + CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]), + CLKDEV_DEV_ID("rspi.2", &mstp_clks[MSTP127]), +}; + +int __init arch_clk_init(void) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(clks); i++) + ret |= clk_register(clks[i]); + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), + &div4_table); + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + return ret; +} + diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c index 370cd47642e..7707e35aea4 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c @@ -12,6 +12,8 @@ */ #include <linux/init.h> #include <linux/kernel.h> +#include <linux/io.h> +#include <linux/clkdev.h> #include <asm/clock.h> #include <asm/freq.h> #include <asm/io.h> @@ -22,45 +24,45 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 }; static void master_clk_init(struct clk *clk) { - clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07]; + clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; } -static struct clk_ops sh7763_master_clk_ops = { +static struct sh_clk_ops sh7763_master_clk_ops = { .init = master_clk_init, }; static unsigned long module_clk_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); + int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); return clk->parent->rate / p0fc_divisors[idx]; } -static struct clk_ops sh7763_module_clk_ops = { +static struct sh_clk_ops sh7763_module_clk_ops = { .recalc = module_clk_recalc, }; static unsigned long bus_clk_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); + int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); return clk->parent->rate / bfc_divisors[idx]; } -static struct clk_ops sh7763_bus_clk_ops = { +static struct sh_clk_ops sh7763_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static struct clk_ops sh7763_cpu_clk_ops = { +static struct sh_clk_ops sh7763_cpu_clk_ops = { .recalc = followparent_recalc, }; -static struct clk_ops *sh7763_clk_ops[] = { +static struct sh_clk_ops *sh7763_clk_ops[] = { &sh7763_master_clk_ops, &sh7763_module_clk_ops, &sh7763_bus_clk_ops, &sh7763_cpu_clk_ops, }; -void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) { if (idx < ARRAY_SIZE(sh7763_clk_ops)) *ops = sh7763_clk_ops[idx]; @@ -68,16 +70,15 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) static unsigned long shyway_clk_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); + int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); return clk->parent->rate / cfc_divisors[idx]; } -static struct clk_ops sh7763_shyway_clk_ops = { +static struct sh_clk_ops sh7763_shyway_clk_ops = { .recalc = shyway_clk_recalc, }; static struct clk sh7763_shyway_clk = { - .name = "shyway_clk", .flags = CLK_ENABLE_ON_INIT, .ops = &sh7763_shyway_clk_ops, }; @@ -90,6 +91,11 @@ static struct clk *sh7763_onchip_clocks[] = { &sh7763_shyway_clk, }; +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk), +}; + int __init arch_clk_init(void) { struct clk *clk; @@ -107,5 +113,7 @@ int __init arch_clk_init(void) clk_put(clk); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c index e0b89676920..5d36f334bb0 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c @@ -21,51 +21,51 @@ static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 }; static void master_clk_init(struct clk *clk) { - clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> 28) & 0x000f]; + clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; } -static struct clk_ops sh7770_master_clk_ops = { +static struct sh_clk_ops sh7770_master_clk_ops = { .init = master_clk_init, }; static unsigned long module_clk_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f); + int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); return clk->parent->rate / pfc_divisors[idx]; } -static struct clk_ops sh7770_module_clk_ops = { +static struct sh_clk_ops sh7770_module_clk_ops = { .recalc = module_clk_recalc, }; static unsigned long bus_clk_recalc(struct clk *clk) { - int idx = (ctrl_inl(FRQCR) & 0x000f); + int idx = (__raw_readl(FRQCR) & 0x000f); return clk->parent->rate / bfc_divisors[idx]; } -static struct clk_ops sh7770_bus_clk_ops = { +static struct sh_clk_ops sh7770_bus_clk_ops = { .recalc = bus_clk_recalc, }; static unsigned long cpu_clk_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f); + int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); return clk->parent->rate / ifc_divisors[idx]; } -static struct clk_ops sh7770_cpu_clk_ops = { +static struct sh_clk_ops sh7770_cpu_clk_ops = { .recalc = cpu_clk_recalc, }; -static struct clk_ops *sh7770_clk_ops[] = { +static struct sh_clk_ops *sh7770_clk_ops[] = { &sh7770_master_clk_ops, &sh7770_module_clk_ops, &sh7770_bus_clk_ops, &sh7770_cpu_clk_ops, }; -void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) { if (idx < ARRAY_SIZE(sh7770_clk_ops)) *ops = sh7770_clk_ops[idx]; diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c index a249d823578..793dae42a2f 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c @@ -11,6 +11,8 @@ */ #include <linux/init.h> #include <linux/kernel.h> +#include <linux/io.h> +#include <linux/clkdev.h> #include <asm/clock.h> #include <asm/freq.h> #include <asm/io.h> @@ -22,51 +24,51 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 }; static void master_clk_init(struct clk *clk) { - clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003]; + clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; } -static struct clk_ops sh7780_master_clk_ops = { +static struct sh_clk_ops sh7780_master_clk_ops = { .init = master_clk_init, }; static unsigned long module_clk_recalc(struct clk *clk) { - int idx = (ctrl_inl(FRQCR) & 0x0003); + int idx = (__raw_readl(FRQCR) & 0x0003); return clk->parent->rate / pfc_divisors[idx]; } -static struct clk_ops sh7780_module_clk_ops = { +static struct sh_clk_ops sh7780_module_clk_ops = { .recalc = module_clk_recalc, }; static unsigned long bus_clk_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007); + int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); return clk->parent->rate / bfc_divisors[idx]; } -static struct clk_ops sh7780_bus_clk_ops = { +static struct sh_clk_ops sh7780_bus_clk_ops = { .recalc = bus_clk_recalc, }; static unsigned long cpu_clk_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001); + int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); return clk->parent->rate / ifc_divisors[idx]; } -static struct clk_ops sh7780_cpu_clk_ops = { +static struct sh_clk_ops sh7780_cpu_clk_ops = { .recalc = cpu_clk_recalc, }; -static struct clk_ops *sh7780_clk_ops[] = { +static struct sh_clk_ops *sh7780_clk_ops[] = { &sh7780_master_clk_ops, &sh7780_module_clk_ops, &sh7780_bus_clk_ops, &sh7780_cpu_clk_ops, }; -void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) { if (idx < ARRAY_SIZE(sh7780_clk_ops)) *ops = sh7780_clk_ops[idx]; @@ -74,16 +76,15 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) static unsigned long shyway_clk_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007); + int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007); return clk->parent->rate / cfc_divisors[idx]; } -static struct clk_ops sh7780_shyway_clk_ops = { +static struct sh_clk_ops sh7780_shyway_clk_ops = { .recalc = shyway_clk_recalc, }; static struct clk sh7780_shyway_clk = { - .name = "shyway_clk", .flags = CLK_ENABLE_ON_INIT, .ops = &sh7780_shyway_clk_ops, }; @@ -96,6 +97,11 @@ static struct clk *sh7780_onchip_clocks[] = { &sh7780_shyway_clk, }; +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk), +}; + int __init arch_clk_init(void) { struct clk *clk; @@ -113,5 +119,7 @@ int __init arch_clk_init(void) clk_put(clk); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c index 73abfbf2f16..17d0ea55a5a 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c @@ -3,7 +3,7 @@ * * SH7785 support for the clock framework * - * Copyright (C) 2007 - 2009 Paul Mundt + * Copyright (C) 2007 - 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -14,6 +14,7 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/cpufreq.h> +#include <linux/clkdev.h> #include <asm/clock.h> #include <asm/freq.h> #include <cpu/sh7785.h> @@ -23,8 +24,6 @@ * from the platform code. */ static struct clk extal_clk = { - .name = "extal", - .id = -1, .rate = 33333333, }; @@ -37,13 +36,11 @@ static unsigned long pll_recalc(struct clk *clk) return clk->parent->rate * multiplier; } -static struct clk_ops pll_clk_ops = { +static struct sh_clk_ops pll_clk_ops = { .recalc = pll_recalc, }; static struct clk pll_clk = { - .name = "pll_clk", - .id = -1, .ops = &pll_clk_ops, .parent = &extal_clk, .flags = CLK_ENABLE_ON_INIT, @@ -57,56 +54,108 @@ static struct clk *clks[] = { static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, 24, 32, 36, 48 }; -static struct clk_div_mult_table div4_table = { +static struct clk_div_mult_table div4_div_mult_table = { .divisors = div2, .nr_divisors = ARRAY_SIZE(div2), }; +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, DIV4_DU, DIV4_P, DIV4_NR }; -#define DIV4(_str, _bit, _mask, _flags) \ - SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) +#define DIV4(_bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) struct clk div4_clks[DIV4_NR] = { - [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0), - [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0), - [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0), - [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT), - [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT), - [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT), - [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT), - [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT), + [DIV4_P] = DIV4(0, 0x0f80, 0), + [DIV4_DU] = DIV4(4, 0x0ff0, 0), + [DIV4_GA] = DIV4(8, 0x0030, 0), + [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), + [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT), + [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), }; #define MSTPCR0 0xffc80030 #define MSTPCR1 0xffc80034 -static struct clk mstp_clks[] = { +enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, + MSTP021, MSTP020, MSTP017, MSTP016, + MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002, + MSTP119, MSTP117, MSTP105, MSTP104, MSTP100, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { /* MSTPCR0 */ - SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), - SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), - SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), - SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), - SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), - SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), - SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), - SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), - SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), - SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), - SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), - SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), - SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), - SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), - SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), - SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), + [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), + [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), + [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), + [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), + [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), + [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), + [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), + [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), + [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), + [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), + [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0), + [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), + [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), + [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), + [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), + [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), /* MSTPCR1 */ - SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), - SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), - SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), - SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), - SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), + [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0), + [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0), + [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), + [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), + [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0), +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), + CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]), + CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + + /* MSTP32 clocks */ + CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]), + + CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), + CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]), + CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]), + CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), + CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]), + CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]), + + CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]), + CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]), + + CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]), + CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), + CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), + CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP117]), + CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), + CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), + CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]), }; int __init arch_clk_init(void) @@ -115,12 +164,14 @@ int __init arch_clk_init(void) for (i = 0; i < ARRAY_SIZE(clks); i++) ret |= clk_register(clks[i]); + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); if (!ret) ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), &div4_table); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c index a0e8869071a..bec2a83f1ba 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c @@ -3,11 +3,7 @@ * * SH7786 support for the clock framework * - * Copyright (C) 2008, 2009 Renesas Solutions Corp. - * Kuninori Morimoto <morimoto.kuninori@renesas.com> - * - * Based on SH7785 - * Copyright (C) 2007 Paul Mundt + * Copyright (C) 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -15,127 +11,182 @@ */ #include <linux/init.h> #include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/clkdev.h> #include <asm/clock.h> #include <asm/freq.h> -#include <asm/io.h> - -static int ifc_divisors[] = { 1, 2, 4, 1 }; -static int sfc_divisors[] = { 1, 1, 4, 1 }; -static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1, - 24, 32, 1, 1, 1, 1, 1, 1 }; -static int mfc_divisors[] = { 1, 1, 4, 1 }; -static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1, - 24, 32, 1, 48, 1, 1, 1, 1 }; -static void master_clk_init(struct clk *clk) -{ - clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f]; -} - -static struct clk_ops sh7786_master_clk_ops = { - .init = master_clk_init, +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk extal_clk = { + .rate = 33333333, }; -static unsigned long module_clk_recalc(struct clk *clk) +static unsigned long pll_recalc(struct clk *clk) { - int idx = (ctrl_inl(FRQMR1) & 0x000f); - return clk->parent->rate / pfc_divisors[idx]; -} + int multiplier; -static struct clk_ops sh7786_module_clk_ops = { - .recalc = module_clk_recalc, -}; + /* + * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1, + * while modes 3, 4, and 5 use an x32. + */ + multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32; -static unsigned long bus_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f); - return clk->parent->rate / bfc_divisors[idx]; + return clk->parent->rate * multiplier; } -static struct clk_ops sh7786_bus_clk_ops = { - .recalc = bus_clk_recalc, +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, }; -static unsigned long cpu_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003); - return clk->parent->rate / ifc_divisors[idx]; -} - -static struct clk_ops sh7786_cpu_clk_ops = { - .recalc = cpu_clk_recalc, +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, }; -static struct clk_ops *sh7786_clk_ops[] = { - &sh7786_master_clk_ops, - &sh7786_module_clk_ops, - &sh7786_bus_clk_ops, - &sh7786_cpu_clk_ops, +static struct clk *clks[] = { + &extal_clk, + &pll_clk, }; -void __init arch_init_clk_ops(struct clk_ops **ops, int idx) -{ - if (idx < ARRAY_SIZE(sh7786_clk_ops)) - *ops = sh7786_clk_ops[idx]; -} +static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, + 24, 32, 36, 48 }; -static unsigned long shyway_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003); - return clk->parent->rate / sfc_divisors[idx]; -} - -static struct clk_ops sh7786_shyway_clk_ops = { - .recalc = shyway_clk_recalc, +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = div2, + .nr_divisors = ARRAY_SIZE(div2), }; -static struct clk sh7786_shyway_clk = { - .name = "shyway_clk", - .flags = CLK_ENABLE_ON_INIT, - .ops = &sh7786_shyway_clk_ops, +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, }; -static unsigned long ddr_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003); - return clk->parent->rate / mfc_divisors[idx]; -} +enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; + +#define DIV4(_bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) -static struct clk_ops sh7786_ddr_clk_ops = { - .recalc = ddr_clk_recalc, +struct clk div4_clks[DIV4_NR] = { + [DIV4_P] = DIV4(0, 0x0b40, 0), + [DIV4_DU] = DIV4(4, 0x0010, 0), + [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT), + [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT), }; -static struct clk sh7786_ddr_clk = { - .name = "ddr_clk", - .flags = CLK_ENABLE_ON_INIT, - .ops = &sh7786_ddr_clk_ops, +#define MSTPCR0 0xffc40030 +#define MSTPCR1 0xffc40034 + +enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, + MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016, + MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008, + MSTP005, MSTP004, MSTP002, + MSTP112, MSTP110, MSTP109, MSTP108, + MSTP105, MSTP104, MSTP103, MSTP102, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + /* MSTPCR0 */ + [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), + [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), + [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), + [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), + [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), + [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), + [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), + [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), + [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), + [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), + [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), + [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), + [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), + [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), + [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), + [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), + [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), + [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), + [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), + [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), + [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), + + /* MSTPCR1 */ + [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0), + [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0), + [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0), + [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0), + [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), + [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), + [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0), + [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0), }; -/* - * Additional SH7786-specific on-chip clocks that aren't already part of the - * clock framework - */ -static struct clk *sh7786_onchip_clocks[] = { - &sh7786_shyway_clk, - &sh7786_ddr_clk, +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), + CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + + /* MSTP32 clocks */ + CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]), + + CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]), + CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]), + CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), + CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]), + CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]), + CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), + CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]), + CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]), + + CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]), + CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]), + CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP010]), + CLKDEV_ICK_ID("fck", "sh-tmu.3", &mstp_clks[MSTP011]), + + CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]), + CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]), + CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), + CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]), + CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]), + CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]), + CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]), + CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), + CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), + CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]), + CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]), }; int __init arch_clk_init(void) { - struct clk *clk; int i, ret = 0; - cpg_clk_init(); - - clk = clk_get(NULL, "master_clk"); - for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) { - struct clk *clkp = sh7786_onchip_clocks[i]; - - clkp->parent = clk; - ret |= clk_register(clkp); - } + for (i = 0; i < ARRAY_SIZE(clks); i++) + ret |= clk_register(clks[i]); + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); - clk_put(clk); + if (!ret) + ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), + &div4_table); + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c index 23c27d32d98..9a49a44f6f9 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c @@ -5,7 +5,7 @@ * * Copyright (C) 2006-2007 Renesas Technology Corp. * Copyright (C) 2006-2007 Renesas Solutions Corp. - * Copyright (C) 2006-2007 Paul Mundt + * Copyright (C) 2006-2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -13,116 +13,139 @@ */ #include <linux/init.h> #include <linux/kernel.h> +#include <linux/io.h> +#include <linux/clkdev.h> #include <asm/clock.h> #include <asm/freq.h> -#include <asm/io.h> - -static int ifc_divisors[] = { 1, 2, 4 ,6 }; -static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; -static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 }; -static int cfc_divisors[] = { 1, 1, 4, 6 }; - -#define IFC_POS 28 -#define IFC_MSK 0x0003 -#define BFC_MSK 0x000f -#define PFC_MSK 0x000f -#define CFC_MSK 0x0003 -#define BFC_POS 16 -#define PFC_POS 0 -#define CFC_POS 20 - -static void master_clk_init(struct clk *clk) -{ - clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK]; -} -static struct clk_ops shx3_master_clk_ops = { - .init = master_clk_init, +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk extal_clk = { + .rate = 16666666, }; -static unsigned long module_clk_recalc(struct clk *clk) +static unsigned long pll_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK); - return clk->parent->rate / pfc_divisors[idx]; + /* PLL1 has a fixed x72 multiplier. */ + return clk->parent->rate * 72; } -static struct clk_ops shx3_module_clk_ops = { - .recalc = module_clk_recalc, +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, }; -static unsigned long bus_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK); - return clk->parent->rate / bfc_divisors[idx]; -} +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; -static struct clk_ops shx3_bus_clk_ops = { - .recalc = bus_clk_recalc, +static struct clk *clks[] = { + &extal_clk, + &pll_clk, }; -static unsigned long cpu_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK); - return clk->parent->rate / ifc_divisors[idx]; -} +static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, + 24, 32, 36, 48 }; -static struct clk_ops shx3_cpu_clk_ops = { - .recalc = cpu_clk_recalc, +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = div2, + .nr_divisors = ARRAY_SIZE(div2), }; -static struct clk_ops *shx3_clk_ops[] = { - &shx3_master_clk_ops, - &shx3_module_clk_ops, - &shx3_bus_clk_ops, - &shx3_cpu_clk_ops, +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, }; -void __init arch_init_clk_ops(struct clk_ops **ops, int idx) -{ - if (idx < ARRAY_SIZE(shx3_clk_ops)) - *ops = shx3_clk_ops[idx]; -} +enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR }; -static unsigned long shyway_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK); - return clk->parent->rate / cfc_divisors[idx]; -} +#define DIV4(_bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) -static struct clk_ops shx3_shyway_clk_ops = { - .recalc = shyway_clk_recalc, +struct clk div4_clks[DIV4_NR] = { + [DIV4_P] = DIV4(0, 0x0f80, 0), + [DIV4_SHA] = DIV4(4, 0x0ff0, 0), + [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), + [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), }; -static struct clk shx3_shyway_clk = { - .name = "shyway_clk", - .flags = CLK_ENABLE_ON_INIT, - .ops = &shx3_shyway_clk_ops, +#define MSTPCR0 0xffc00030 +#define MSTPCR1 0xffc00034 + +enum { MSTP027, MSTP026, MSTP025, MSTP024, + MSTP009, MSTP008, MSTP003, MSTP002, + MSTP001, MSTP000, MSTP119, MSTP105, + MSTP104, MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + /* MSTPCR0 */ + [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), + [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), + [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), + [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), + [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), + [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), + [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), + [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), + [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0), + [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), + + /* MSTPCR1 */ + [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0), + [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), + [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), }; -/* - * Additional SHx3-specific on-chip clocks that aren't already part of the - * clock framework - */ -static struct clk *shx3_onchip_clocks[] = { - &shx3_shyway_clk, +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]), + CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + + /* MSTP32 clocks */ + CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]), + + CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]), + CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]), + CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]), + CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]), + + CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]), + CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]), + + CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), + CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), + CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), }; int __init arch_clk_init(void) { - struct clk *clk; int i, ret = 0; - cpg_clk_init(); - - clk = clk_get(NULL, "master_clk"); - for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { - struct clk *clkp = shx3_onchip_clocks[i]; - - clkp->parent = clk; - ret |= clk_register(clkp); - } + for (i = 0; i < ARRAY_SIZE(clks); i++) + ret |= clk_register(clks[i]); + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); - clk_put(clk); + if (!ret) + ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), + &div4_table); + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/intc-shx3.c b/arch/sh/kernel/cpu/sh4a/intc-shx3.c new file mode 100644 index 00000000000..78c971486b4 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/intc-shx3.c @@ -0,0 +1,34 @@ +/* + * Shared support for SH-X3 interrupt controllers. + * + * Copyright (C) 2009 - 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/init.h> + +#define INTACK 0xfe4100b8 +#define INTACKCLR 0xfe4100bc +#define INTC_USERIMASK 0xfe411000 + +#ifdef CONFIG_INTC_BALANCING +unsigned int irq_lookup(unsigned int irq) +{ + return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE; +} + +void irq_finish(unsigned int irq) +{ + __raw_writel(irq2evt(irq), INTACKCLR); +} +#endif + +static int __init shx3_irq_setup(void) +{ + return register_intc_userimask(INTC_USERIMASK); +} +arch_initcall(shx3_irq_setup); diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c new file mode 100644 index 00000000000..84a2c396cee --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/perf_event.c @@ -0,0 +1,302 @@ +/* + * Performance events support for SH-4A performance counters + * + * Copyright (C) 2009, 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/perf_event.h> +#include <asm/processor.h> + +#define PPC_CCBR(idx) (0xff200800 + (sizeof(u32) * idx)) +#define PPC_PMCTR(idx) (0xfc100000 + (sizeof(u32) * idx)) + +#define CCBR_CIT_MASK (0x7ff << 6) +#define CCBR_DUC (1 << 3) +#define CCBR_CMDS (1 << 1) +#define CCBR_PPCE (1 << 0) + +#ifdef CONFIG_CPU_SHX3 +/* + * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR + * and PMCTR locations remains tentatively constant. This change remains + * wholly undocumented, and was simply found through trial and error. + * + * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and + * it's unclear when this ceased to be the case. For now we always use + * the new location (if future parts keep up with this trend then + * scanning for them at runtime also remains a viable option.) + * + * The gap in the register space also suggests that there are other + * undocumented counters, so this will need to be revisited at a later + * point in time. + */ +#define PPC_PMCAT 0xfc100240 +#else +#define PPC_PMCAT 0xfc100080 +#endif + +#define PMCAT_OVF3 (1 << 27) +#define PMCAT_CNN3 (1 << 26) +#define PMCAT_CLR3 (1 << 25) +#define PMCAT_OVF2 (1 << 19) +#define PMCAT_CLR2 (1 << 17) +#define PMCAT_OVF1 (1 << 11) +#define PMCAT_CNN1 (1 << 10) +#define PMCAT_CLR1 (1 << 9) +#define PMCAT_OVF0 (1 << 3) +#define PMCAT_CLR0 (1 << 1) + +static struct sh_pmu sh4a_pmu; + +/* + * Supported raw event codes: + * + * Event Code Description + * ---------- ----------- + * + * 0x0000 number of elapsed cycles + * 0x0200 number of elapsed cycles in privileged mode + * 0x0280 number of elapsed cycles while SR.BL is asserted + * 0x0202 instruction execution + * 0x0203 instruction execution in parallel + * 0x0204 number of unconditional branches + * 0x0208 number of exceptions + * 0x0209 number of interrupts + * 0x0220 UTLB miss caused by instruction fetch + * 0x0222 UTLB miss caused by operand access + * 0x02a0 number of ITLB misses + * 0x0028 number of accesses to instruction memories + * 0x0029 number of accesses to instruction cache + * 0x002a instruction cache miss + * 0x022e number of access to instruction X/Y memory + * 0x0030 number of reads to operand memories + * 0x0038 number of writes to operand memories + * 0x0031 number of operand cache read accesses + * 0x0039 number of operand cache write accesses + * 0x0032 operand cache read miss + * 0x003a operand cache write miss + * 0x0236 number of reads to operand X/Y memory + * 0x023e number of writes to operand X/Y memory + * 0x0237 number of reads to operand U memory + * 0x023f number of writes to operand U memory + * 0x0337 number of U memory read buffer misses + * 0x02b4 number of wait cycles due to operand read access + * 0x02bc number of wait cycles due to operand write access + * 0x0033 number of wait cycles due to operand cache read miss + * 0x003b number of wait cycles due to operand cache write miss + */ + +/* + * Special reserved bits used by hardware emulators, read values will + * vary, but writes must always be 0. + */ +#define PMCAT_EMU_CLR_MASK ((1 << 24) | (1 << 16) | (1 << 8) | (1 << 0)) + +static const int sh4a_general_events[] = { + [PERF_COUNT_HW_CPU_CYCLES] = 0x0000, + [PERF_COUNT_HW_INSTRUCTIONS] = 0x0202, + [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0029, /* I-cache */ + [PERF_COUNT_HW_CACHE_MISSES] = 0x002a, /* I-cache */ + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0204, + [PERF_COUNT_HW_BRANCH_MISSES] = -1, + [PERF_COUNT_HW_BUS_CYCLES] = -1, +}; + +#define C(x) PERF_COUNT_HW_CACHE_##x + +static const int sh4a_cache_events + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = +{ + [ C(L1D) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0031, + [ C(RESULT_MISS) ] = 0x0032, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0x0039, + [ C(RESULT_MISS) ] = 0x003a, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + + [ C(L1I) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0029, + [ C(RESULT_MISS) ] = 0x002a, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + + [ C(LL) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0030, + [ C(RESULT_MISS) ] = 0, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0x0038, + [ C(RESULT_MISS) ] = 0, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + + [ C(DTLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0222, + [ C(RESULT_MISS) ] = 0x0220, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + + [ C(ITLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0x02a0, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, + + [ C(BPU) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, + + [ C(NODE) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, +}; + +static int sh4a_event_map(int event) +{ + return sh4a_general_events[event]; +} + +static u64 sh4a_pmu_read(int idx) +{ + return __raw_readl(PPC_PMCTR(idx)); +} + +static void sh4a_pmu_disable(struct hw_perf_event *hwc, int idx) +{ + unsigned int tmp; + + tmp = __raw_readl(PPC_CCBR(idx)); + tmp &= ~(CCBR_CIT_MASK | CCBR_DUC); + __raw_writel(tmp, PPC_CCBR(idx)); +} + +static void sh4a_pmu_enable(struct hw_perf_event *hwc, int idx) +{ + unsigned int tmp; + + tmp = __raw_readl(PPC_PMCAT); + tmp &= ~PMCAT_EMU_CLR_MASK; + tmp |= idx ? PMCAT_CLR1 : PMCAT_CLR0; + __raw_writel(tmp, PPC_PMCAT); + + tmp = __raw_readl(PPC_CCBR(idx)); + tmp |= (hwc->config << 6) | CCBR_CMDS | CCBR_PPCE; + __raw_writel(tmp, PPC_CCBR(idx)); + + __raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx)); +} + +static void sh4a_pmu_disable_all(void) +{ + int i; + + for (i = 0; i < sh4a_pmu.num_events; i++) + __raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i)); +} + +static void sh4a_pmu_enable_all(void) +{ + int i; + + for (i = 0; i < sh4a_pmu.num_events; i++) + __raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i)); +} + +static struct sh_pmu sh4a_pmu = { + .name = "sh4a", + .num_events = 2, + .event_map = sh4a_event_map, + .max_events = ARRAY_SIZE(sh4a_general_events), + .raw_event_mask = 0x3ff, + .cache_events = &sh4a_cache_events, + .read = sh4a_pmu_read, + .disable = sh4a_pmu_disable, + .enable = sh4a_pmu_enable, + .disable_all = sh4a_pmu_disable_all, + .enable_all = sh4a_pmu_enable_all, +}; + +static int __init sh4a_pmu_init(void) +{ + /* + * Make sure this CPU actually has perf counters. + */ + if (!(boot_cpu_data.flags & CPU_HAS_PERF_COUNTER)) { + pr_notice("HW perf events unsupported, software events only.\n"); + return -ENODEV; + } + + return register_sh_pmu(&sh4a_pmu); +} +early_initcall(sh4a_pmu_init); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c index cb9d07bd59f..271bbc86492 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c @@ -1,1783 +1,20 @@ +#include <linux/bug.h> #include <linux/init.h> #include <linux/kernel.h> -#include <linux/gpio.h> -#include <cpu/sh7722.h> +#include <linux/ioport.h> +#include <cpu/pfc.h> -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, - PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA, - PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, - PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA, - PTC7_DATA, PTC5_DATA, PTC4_DATA, PTC3_DATA, PTC2_DATA, PTC0_DATA, - PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, - PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA, - PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, PTE1_DATA, PTE0_DATA, - PTF6_DATA, PTF5_DATA, PTF4_DATA, - PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA, - PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA, - PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, - PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, - PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ1_DATA, PTJ0_DATA, - PTK6_DATA, PTK5_DATA, PTK4_DATA, - PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, - PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, - PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, - PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, - PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, - PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, - PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, - PTR4_DATA, PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, - PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, - PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, - PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, - PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA, - PTW6_DATA, PTW5_DATA, PTW4_DATA, - PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA, - PTX6_DATA, PTX5_DATA, PTX4_DATA, - PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA, - PTY6_DATA, PTY5_DATA, PTY4_DATA, - PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA, - PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA, - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN, - PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN, - PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN, - PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN, - PTC7_IN, PTC5_IN, PTC4_IN, PTC3_IN, PTC2_IN, PTC0_IN, - PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, PTD3_IN, PTD2_IN, PTD1_IN, - PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN, PTE1_IN, PTE0_IN, - PTF6_IN, PTF5_IN, PTF4_IN, PTF3_IN, PTF2_IN, PTF1_IN, - PTH6_IN, PTH5_IN, PTH1_IN, PTH0_IN, - PTJ1_IN, PTJ0_IN, - PTK6_IN, PTK5_IN, PTK4_IN, PTK3_IN, PTK2_IN, PTK0_IN, - PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, - PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, - PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN, - PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, - PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, - PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, - PTQ5_IN, PTQ4_IN, PTQ3_IN, PTQ2_IN, PTQ0_IN, - PTR2_IN, - PTS4_IN, PTS2_IN, PTS1_IN, - PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, - PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, - PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, - PTW6_IN, PTW4_IN, PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN, - PTX6_IN, PTX5_IN, PTX4_IN, PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN, - PTY5_IN, PTY4_IN, PTY3_IN, PTY2_IN, PTY0_IN, - PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN, - PINMUX_INPUT_END, - - PINMUX_INPUT_PULLDOWN_BEGIN, - PTA7_IN_PD, PTA6_IN_PD, PTA5_IN_PD, PTA4_IN_PD, - PTA3_IN_PD, PTA2_IN_PD, PTA1_IN_PD, PTA0_IN_PD, - PTE7_IN_PD, PTE6_IN_PD, PTE5_IN_PD, PTE4_IN_PD, PTE1_IN_PD, PTE0_IN_PD, - PTF6_IN_PD, PTF5_IN_PD, PTF4_IN_PD, PTF3_IN_PD, PTF2_IN_PD, PTF1_IN_PD, - PTH6_IN_PD, PTH5_IN_PD, PTH1_IN_PD, PTH0_IN_PD, - PTK6_IN_PD, PTK5_IN_PD, PTK4_IN_PD, PTK3_IN_PD, PTK2_IN_PD, PTK0_IN_PD, - PTL7_IN_PD, PTL6_IN_PD, PTL5_IN_PD, PTL4_IN_PD, - PTL3_IN_PD, PTL2_IN_PD, PTL1_IN_PD, PTL0_IN_PD, - PTM7_IN_PD, PTM6_IN_PD, PTM5_IN_PD, PTM4_IN_PD, - PTM3_IN_PD, PTM2_IN_PD, PTM1_IN_PD, PTM0_IN_PD, - PTQ5_IN_PD, PTQ4_IN_PD, PTQ3_IN_PD, PTQ2_IN_PD, - PTS4_IN_PD, PTS2_IN_PD, PTS1_IN_PD, - PTT4_IN_PD, PTT3_IN_PD, PTT2_IN_PD, PTT1_IN_PD, - PTU4_IN_PD, PTU3_IN_PD, PTU2_IN_PD, PTU1_IN_PD, PTU0_IN_PD, - PTV4_IN_PD, PTV3_IN_PD, PTV2_IN_PD, PTV1_IN_PD, PTV0_IN_PD, - PTW6_IN_PD, PTW4_IN_PD, PTW3_IN_PD, PTW2_IN_PD, PTW1_IN_PD, PTW0_IN_PD, - PTX6_IN_PD, PTX5_IN_PD, PTX4_IN_PD, - PTX3_IN_PD, PTX2_IN_PD, PTX1_IN_PD, PTX0_IN_PD, - PINMUX_INPUT_PULLDOWN_END, - - PINMUX_INPUT_PULLUP_BEGIN, - PTC7_IN_PU, PTC5_IN_PU, - PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, - PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, - PTJ1_IN_PU, PTJ0_IN_PU, - PTQ0_IN_PU, - PTR2_IN_PU, - PTX6_IN_PU, - PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY0_IN_PU, - PTZ5_IN_PU, PTZ4_IN_PU, PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, - PINMUX_INPUT_PULLUP_END, - - PINMUX_OUTPUT_BEGIN, - PTA7_OUT, PTA5_OUT, - PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, - PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT, - PTC4_OUT, PTC3_OUT, PTC2_OUT, PTC0_OUT, - PTD6_OUT, PTD5_OUT, PTD4_OUT, - PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT, - PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT, PTE1_OUT, PTE0_OUT, - PTF6_OUT, PTF5_OUT, PTF4_OUT, PTF3_OUT, PTF2_OUT, PTF0_OUT, - PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT, - PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT, - PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, - PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ1_OUT, PTJ0_OUT, - PTK6_OUT, PTK5_OUT, PTK4_OUT, PTK3_OUT, PTK1_OUT, PTK0_OUT, - PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, - PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, - PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT, - PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, - PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, - PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, - PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT, - PTR4_OUT, PTR3_OUT, PTR1_OUT, PTR0_OUT, - PTS3_OUT, PTS2_OUT, PTS0_OUT, - PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT0_OUT, - PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU0_OUT, - PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT, - PTW5_OUT, PTW4_OUT, PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT, - PTX6_OUT, PTX5_OUT, PTX4_OUT, PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT, - PTY5_OUT, PTY4_OUT, PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT, - PINMUX_OUTPUT_END, - - PINMUX_MARK_BEGIN, - SCIF0_TXD_MARK, SCIF0_RXD_MARK, - SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK, - SCIF1_TXD_MARK, SCIF1_RXD_MARK, - SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK, - SCIF2_TXD_MARK, SCIF2_RXD_MARK, - SCIF2_RTS_MARK, SCIF2_CTS_MARK, SCIF2_SCK_MARK, - SIOTXD_MARK, SIORXD_MARK, - SIOD_MARK, SIOSTRB0_MARK, SIOSTRB1_MARK, - SIOSCK_MARK, SIOMCK_MARK, - VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK, - VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK, - VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK, - VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK, - VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, VIO_FLD_MARK, - VIO_CKO_MARK, VIO_STEX_MARK, VIO_STEM_MARK, VIO_VD2_MARK, - VIO_HD2_MARK, VIO_CLK2_MARK, - LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK, - LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK, - LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK, - LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK, - LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK, - LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK, - LCDLCLK_MARK, LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK, - LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK, - LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, - LCDDON2_MARK, LCDVCPWC2_MARK, LCDVEPWC2_MARK, LCDVSYN2_MARK, - LCDCS2_MARK, - IOIS16_MARK, A25_MARK, A24_MARK, A23_MARK, A22_MARK, - BS_MARK, CS6B_CE1B_MARK, WAIT_MARK, CS6A_CE2B_MARK, - HPD63_MARK, HPD62_MARK, HPD61_MARK, HPD60_MARK, - HPD59_MARK, HPD58_MARK, HPD57_MARK, HPD56_MARK, - HPD55_MARK, HPD54_MARK, HPD53_MARK, HPD52_MARK, - HPD51_MARK, HPD50_MARK, HPD49_MARK, HPD48_MARK, - HPDQM7_MARK, HPDQM6_MARK, HPDQM5_MARK, HPDQM4_MARK, - IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, - IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK, - SDHICD_MARK, SDHIWP_MARK, SDHID3_MARK, SDHID2_MARK, - SDHID1_MARK, SDHID0_MARK, SDHICMD_MARK, SDHICLK_MARK, - SIUAOLR_MARK, SIUAOBT_MARK, SIUAISLD_MARK, SIUAILR_MARK, - SIUAIBT_MARK, SIUAOSLD_MARK, SIUMCKA_MARK, SIUFCKA_MARK, - SIUBOLR_MARK, SIUBOBT_MARK, SIUBISLD_MARK, SIUBILR_MARK, - SIUBIBT_MARK, SIUBOSLD_MARK, SIUMCKB_MARK, SIUFCKB_MARK, - AUDSYNC_MARK, AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK, - DACK_MARK, DREQ0_MARK, - DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK, - DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK, - DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK, - DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK, - DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK, - STATUS0_MARK, PDSTATUS_MARK, - SIOF0_MCK_MARK, SIOF0_SCK_MARK, - SIOF0_SYNC_MARK, SIOF0_SS1_MARK, SIOF0_SS2_MARK, - SIOF0_TXD_MARK, SIOF0_RXD_MARK, - SIOF1_MCK_MARK, SIOF1_SCK_MARK, - SIOF1_SYNC_MARK, SIOF1_SS1_MARK, SIOF1_SS2_MARK, - SIOF1_TXD_MARK, SIOF1_RXD_MARK, - SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK, - TS_SDAT_MARK, TS_SCK_MARK, TS_SDEN_MARK, TS_SPSYNC_MARK, - IRDA_IN_MARK, IRDA_OUT_MARK, - TPUTO_MARK, - FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK, - NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK, - FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK, - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK, - KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, - KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK, - PINMUX_MARK_END, - - PINMUX_FUNCTION_BEGIN, - VIO_D7_SCIF1_SCK, VIO_D6_SCIF1_RXD, VIO_D5_SCIF1_TXD, VIO_D4, - VIO_D3, VIO_D2, VIO_D1, VIO_D0_LCDLCLK, - HPD55, HPD54, HPD53, HPD52, HPD51, HPD50, HPD49, HPD48, - IOIS16, HPDQM7, HPDQM6, HPDQM5, HPDQM4, - SDHICD, SDHIWP, SDHID3, IRQ2_SDHID2, SDHID1, SDHID0, SDHICMD, SDHICLK, - A25, A24, A23, A22, IRQ5, IRQ4_BS, - PTF6, SIOSCK_SIUBOBT, SIOSTRB1_SIUBOLR, - SIOSTRB0_SIUBIBT, SIOD_SIUBILR, SIORXD_SIUBISLD, SIOTXD_SIUBOSLD, - AUDSYNC, AUDATA3, AUDATA2, AUDATA1, AUDATA0, - LCDVCPWC_LCDVCPWC2, LCDVSYN2_DACK, LCDVSYN, LCDDISP_LCDRS, - LCDHSYN_LCDCS, LCDDON_LCDDON2, LCDD17_DV_HSYNC, LCDD16_DV_VSYNC, - STATUS0, PDSTATUS, IRQ1, IRQ0, - SIUAILR_SIOF1_SS2, SIUAIBT_SIOF1_SS1, SIUAOLR_SIOF1_SYNC, - SIUAOBT_SIOF1_SCK, SIUAISLD_SIOF1_RXD, SIUAOSLD_SIOF1_TXD, PTK0, - LCDD15_DV_D15, LCDD14_DV_D14, LCDD13_DV_D13, LCDD12_DV_D12, - LCDD11_DV_D11, LCDD10_DV_D10, LCDD9_DV_D9, LCDD8_DV_D8, - LCDD7_DV_D7, LCDD6_DV_D6, LCDD5_DV_D5, LCDD4_DV_D4, - LCDD3_DV_D3, LCDD2_DV_D2, LCDD1_DV_D1, LCDD0_DV_D0, - HPD63, HPD62, HPD61, HPD60, HPD59, HPD58, HPD57, HPD56, - SIOF0_SS2_SIM_RST, SIOF0_SS1_TS_SPSYNC, SIOF0_SYNC_TS_SDEN, - SIOF0_SCK_TS_SCK, PTQ2, PTQ1, PTQ0, - LCDRD, CS6B_CE1B_LCDCS2, WAIT, LCDDCK_LCDWR, LCDVEPWC_LCDVEPWC2, - SCIF0_CTS_SIUAISPD, SCIF0_RTS_SIUAOSPD, - SCIF0_SCK_TPUTO, SCIF0_RXD, SCIF0_TXD, - FOE_VIO_VD2, FWE, FSC, DREQ0, FCDE, - NAF2_VIO_D10, NAF1_VIO_D9, NAF0_VIO_D8, - FRB_VIO_CLK2, FCE_VIO_HD2, - NAF7_VIO_D15, NAF6_VIO_D14, NAF5_VIO_D13, NAF4_VIO_D12, NAF3_VIO_D11, - VIO_FLD_SCIF2_CTS, VIO_CKO_SCIF2_RTS, VIO_STEX_SCIF2_SCK, - VIO_STEM_SCIF2_TXD, VIO_HD_SCIF2_RXD, - VIO_VD_SCIF1_CTS, VIO_CLK_SCIF1_RTS, - CS6A_CE2B, LCDD23, LCDD22, LCDD21, LCDD20, - LCDD19_DV_CLKI, LCDD18_DV_CLK, - KEYOUT5_IN5, KEYOUT4_IN6, KEYOUT3, KEYOUT2, KEYOUT1, KEYOUT0, - KEYIN4_IRQ7, KEYIN3, KEYIN2, KEYIN1, KEYIN0_IRQ6, - - PSA15_KEYIN0, PSA15_IRQ6, PSA14_KEYIN4, PSA14_IRQ7, - PSA9_IRQ4, PSA9_BS, PSA4_IRQ2, PSA4_SDHID2, - PSB15_SIOTXD, PSB15_SIUBOSLD, PSB14_SIORXD, PSB14_SIUBISLD, - PSB13_SIOD, PSB13_SIUBILR, PSB12_SIOSTRB0, PSB12_SIUBIBT, - PSB11_SIOSTRB1, PSB11_SIUBOLR, PSB10_SIOSCK, PSB10_SIUBOBT, - PSB9_SIOMCK, PSB9_SIUMCKB, PSB8_SIOF0_MCK, PSB8_IRQ3, - PSB7_SIOF0_TXD, PSB7_IRDA_OUT, PSB6_SIOF0_RXD, PSB6_IRDA_IN, - PSB5_SIOF0_SCK, PSB5_TS_SCK, PSB4_SIOF0_SYNC, PSB4_TS_SDEN, - PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, PSB2_SIOF0_SS2, PSB2_SIM_RST, - PSB1_SIUMCKA, PSB1_SIOF1_MCK, PSB0_SIUAOSLD, PSB0_SIOF1_TXD, - PSC15_SIUAISLD, PSC15_SIOF1_RXD, PSC14_SIUAOBT, PSC14_SIOF1_SCK, - PSC13_SIUAOLR, PSC13_SIOF1_SYNC, PSC12_SIUAIBT, PSC12_SIOF1_SS1, - PSC11_SIUAILR, PSC11_SIOF1_SS2, PSC0_NAF, PSC0_VIO, - PSD13_VIO, PSD13_SCIF2, PSD12_VIO, PSD12_SCIF1, - PSD11_VIO, PSD11_SCIF1, PSD10_VIO_D0, PSD10_LCDLCLK, - PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB, PSD8_SCIF0_SCK, PSD8_TPUTO, - PSD7_SCIF0_RTS, PSD7_SIUAOSPD, PSD6_SCIF0_CTS, PSD6_SIUAISPD, - PSD5_CS6B_CE1B, PSD5_LCDCS2, - PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2, - PSD2_LCDDON, PSD2_LCDDON2, PSD0_LCDD19_LCDD0, PSD0_DV, - PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D, - PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK, - PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, PSE12_LCDVSYN2, PSE12_DACK, - PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA, - PSE3_FLCTL, PSE3_VIO, PSE2_NAF2, PSE2_VIO_D10, - PSE1_NAF1, PSE1_VIO_D9, PSE0_NAF0, PSE0_VIO_D8, - - HIZA14_KEYSC, HIZA14_HIZ, - HIZA10_NAF, HIZA10_HIZ, - HIZA9_VIO, HIZA9_HIZ, - HIZA8_LCDC, HIZA8_HIZ, - HIZA7_LCDC, HIZA7_HIZ, - HIZA6_LCDC, HIZA6_HIZ, - HIZB1_VIO, HIZB1_HIZ, - HIZB0_VIO, HIZB0_HIZ, - HIZC15_IRQ7, HIZC15_HIZ, - HIZC14_IRQ6, HIZC14_HIZ, - HIZC13_IRQ5, HIZC13_HIZ, - HIZC12_IRQ4, HIZC12_HIZ, - HIZC11_IRQ3, HIZC11_HIZ, - HIZC10_IRQ2, HIZC10_HIZ, - HIZC9_IRQ1, HIZC9_HIZ, - HIZC8_IRQ0, HIZC8_HIZ, - MSELB9_VIO, MSELB9_VIO2, - MSELB8_RGB, MSELB8_SYS, - PINMUX_FUNCTION_END, -}; - -static pinmux_enum_t pinmux_data[] = { - /* PTA */ - PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT), - PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD), - PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_IN_PD, PTA5_OUT), - PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_IN_PD), - PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_IN_PD), - PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_IN_PD), - PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_IN_PD), - PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_IN_PD), - - /* PTB */ - PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), - PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), - PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), - PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), - PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), - PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), - PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), - PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), - - /* PTC */ - PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_IN_PU), - PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_IN_PU), - PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), - PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), - PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), - PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), - - /* PTD */ - PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_IN_PU), - PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN, PTD6_IN_PU), - PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN, PTD5_IN_PU), - PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN, PTD4_IN_PU), - PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN, PTD3_IN_PU), - PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN, PTD2_IN_PU), - PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN, PTD1_IN_PU), - PINMUX_DATA(PTD0_DATA, PTD0_OUT), - - /* PTE */ - PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN, PTE7_IN_PD), - PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN, PTE6_IN_PD), - PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN, PTE5_IN_PD), - PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN, PTE4_IN_PD), - PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN, PTE1_IN_PD), - PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN, PTE0_IN_PD), - - /* PTF */ - PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN, PTF6_IN_PD), - PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN, PTF5_IN_PD), - PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN, PTF4_IN_PD), - PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN, PTF3_IN_PD), - PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN, PTF2_IN_PD), - PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_IN_PD), - PINMUX_DATA(PTF0_DATA, PTF0_OUT), - - /* PTG */ - PINMUX_DATA(PTG4_DATA, PTG4_OUT), - PINMUX_DATA(PTG3_DATA, PTG3_OUT), - PINMUX_DATA(PTG2_DATA, PTG2_OUT), - PINMUX_DATA(PTG1_DATA, PTG1_OUT), - PINMUX_DATA(PTG0_DATA, PTG0_OUT), - - /* PTH */ - PINMUX_DATA(PTH7_DATA, PTH7_OUT), - PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN, PTH6_IN_PD), - PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN, PTH5_IN_PD), - PINMUX_DATA(PTH4_DATA, PTH4_OUT), - PINMUX_DATA(PTH3_DATA, PTH3_OUT), - PINMUX_DATA(PTH2_DATA, PTH2_OUT), - PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN, PTH1_IN_PD), - PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN, PTH0_IN_PD), - - /* PTJ */ - PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), - PINMUX_DATA(PTJ6_DATA, PTJ6_OUT), - PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), - PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU), - PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU), - - /* PTK */ - PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN, PTK6_IN_PD), - PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN, PTK5_IN_PD), - PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN, PTK4_IN_PD), - PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN, PTK3_IN_PD), - PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_IN_PD), - PINMUX_DATA(PTK1_DATA, PTK1_OUT), - PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN, PTK0_IN_PD), - - /* PTL */ - PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN, PTL7_IN_PD), - PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN, PTL6_IN_PD), - PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN, PTL5_IN_PD), - PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN, PTL4_IN_PD), - PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN, PTL3_IN_PD), - PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN, PTL2_IN_PD), - PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN, PTL1_IN_PD), - PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN, PTL0_IN_PD), - - /* PTM */ - PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN, PTM7_IN_PD), - PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN, PTM6_IN_PD), - PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN, PTM5_IN_PD), - PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN, PTM4_IN_PD), - PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN, PTM3_IN_PD), - PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN, PTM2_IN_PD), - PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN, PTM1_IN_PD), - PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN, PTM0_IN_PD), - - /* PTN */ - PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN), - PINMUX_DATA(PTN6_DATA, PTN6_OUT, PTN6_IN), - PINMUX_DATA(PTN5_DATA, PTN5_OUT, PTN5_IN), - PINMUX_DATA(PTN4_DATA, PTN4_OUT, PTN4_IN), - PINMUX_DATA(PTN3_DATA, PTN3_OUT, PTN3_IN), - PINMUX_DATA(PTN2_DATA, PTN2_OUT, PTN2_IN), - PINMUX_DATA(PTN1_DATA, PTN1_OUT, PTN1_IN), - PINMUX_DATA(PTN0_DATA, PTN0_OUT, PTN0_IN), - - /* PTQ */ - PINMUX_DATA(PTQ6_DATA, PTQ6_OUT), - PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN, PTQ5_IN_PD), - PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN, PTQ4_IN_PD), - PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN, PTQ3_IN_PD), - PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_IN_PD), - PINMUX_DATA(PTQ1_DATA, PTQ1_OUT), - PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN, PTQ0_IN_PU), - - /* PTR */ - PINMUX_DATA(PTR4_DATA, PTR4_OUT), - PINMUX_DATA(PTR3_DATA, PTR3_OUT), - PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), - PINMUX_DATA(PTR1_DATA, PTR1_OUT), - PINMUX_DATA(PTR0_DATA, PTR0_OUT), - - /* PTS */ - PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_IN_PD), - PINMUX_DATA(PTS3_DATA, PTS3_OUT), - PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN, PTS2_IN_PD), - PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_IN_PD), - PINMUX_DATA(PTS0_DATA, PTS0_OUT), - - /* PTT */ - PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN, PTT4_IN_PD), - PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN, PTT3_IN_PD), - PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN, PTT2_IN_PD), - PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_IN_PD), - PINMUX_DATA(PTT0_DATA, PTT0_OUT), - - /* PTU */ - PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN, PTU4_IN_PD), - PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN, PTU3_IN_PD), - PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN, PTU2_IN_PD), - PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_IN_PD), - PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN, PTU0_IN_PD), - - /* PTV */ - PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN, PTV4_IN_PD), - PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN, PTV3_IN_PD), - PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN, PTV2_IN_PD), - PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN, PTV1_IN_PD), - PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN, PTV0_IN_PD), - - /* PTW */ - PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_IN_PD), - PINMUX_DATA(PTW5_DATA, PTW5_OUT), - PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN, PTW4_IN_PD), - PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN, PTW3_IN_PD), - PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN, PTW2_IN_PD), - PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN, PTW1_IN_PD), - PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN, PTW0_IN_PD), - - /* PTX */ - PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN, PTX6_IN_PD), - PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN, PTX5_IN_PD), - PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN, PTX4_IN_PD), - PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN, PTX3_IN_PD), - PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN, PTX2_IN_PD), - PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN, PTX1_IN_PD), - PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN, PTX0_IN_PD), - - /* PTY */ - PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN, PTY5_IN_PU), - PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN, PTY4_IN_PU), - PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN, PTY3_IN_PU), - PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN, PTY2_IN_PU), - PINMUX_DATA(PTY1_DATA, PTY1_OUT), - PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN, PTY0_IN_PU), - - /* PTZ */ - PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_IN_PU), - PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_IN_PU), - PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_IN_PU), - PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_IN_PU), - PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_IN_PU), - - /* SCIF0 */ - PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD), - PINMUX_DATA(SCIF0_RXD_MARK, SCIF0_RXD), - PINMUX_DATA(SCIF0_RTS_MARK, PSD7_SCIF0_RTS, SCIF0_RTS_SIUAOSPD), - PINMUX_DATA(SCIF0_CTS_MARK, PSD6_SCIF0_CTS, SCIF0_CTS_SIUAISPD), - PINMUX_DATA(SCIF0_SCK_MARK, PSD8_SCIF0_SCK, SCIF0_SCK_TPUTO), - - /* SCIF1 */ - PINMUX_DATA(SCIF1_TXD_MARK, PSD11_SCIF1, VIO_D5_SCIF1_TXD), - PINMUX_DATA(SCIF1_RXD_MARK, PSD11_SCIF1, VIO_D6_SCIF1_RXD), - PINMUX_DATA(SCIF1_RTS_MARK, PSD12_SCIF1, VIO_CLK_SCIF1_RTS), - PINMUX_DATA(SCIF1_CTS_MARK, PSD12_SCIF1, VIO_VD_SCIF1_CTS), - PINMUX_DATA(SCIF1_SCK_MARK, PSD11_SCIF1, VIO_D7_SCIF1_SCK), - - /* SCIF2 */ - PINMUX_DATA(SCIF2_TXD_MARK, PSD13_SCIF2, VIO_STEM_SCIF2_TXD), - PINMUX_DATA(SCIF2_RXD_MARK, PSD13_SCIF2, VIO_HD_SCIF2_RXD), - PINMUX_DATA(SCIF2_RTS_MARK, PSD13_SCIF2, VIO_CKO_SCIF2_RTS), - PINMUX_DATA(SCIF2_CTS_MARK, PSD13_SCIF2, VIO_FLD_SCIF2_CTS), - PINMUX_DATA(SCIF2_SCK_MARK, PSD13_SCIF2, VIO_STEX_SCIF2_SCK), - - /* SIO */ - PINMUX_DATA(SIOTXD_MARK, PSB15_SIOTXD, SIOTXD_SIUBOSLD), - PINMUX_DATA(SIORXD_MARK, PSB14_SIORXD, SIORXD_SIUBISLD), - PINMUX_DATA(SIOD_MARK, PSB13_SIOD, SIOD_SIUBILR), - PINMUX_DATA(SIOSTRB0_MARK, PSB12_SIOSTRB0, SIOSTRB0_SIUBIBT), - PINMUX_DATA(SIOSTRB1_MARK, PSB11_SIOSTRB1, SIOSTRB1_SIUBOLR), - PINMUX_DATA(SIOSCK_MARK, PSB10_SIOSCK, SIOSCK_SIUBOBT), - PINMUX_DATA(SIOMCK_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIOMCK, PTF6), - - /* CEU */ - PINMUX_DATA(VIO_D15_MARK, PSC0_VIO, HIZA10_NAF, NAF7_VIO_D15), - PINMUX_DATA(VIO_D14_MARK, PSC0_VIO, HIZA10_NAF, NAF6_VIO_D14), - PINMUX_DATA(VIO_D13_MARK, PSC0_VIO, HIZA10_NAF, NAF5_VIO_D13), - PINMUX_DATA(VIO_D12_MARK, PSC0_VIO, HIZA10_NAF, NAF4_VIO_D12), - PINMUX_DATA(VIO_D11_MARK, PSC0_VIO, HIZA10_NAF, NAF3_VIO_D11), - PINMUX_DATA(VIO_D10_MARK, PSE2_VIO_D10, HIZB0_VIO, NAF2_VIO_D10), - PINMUX_DATA(VIO_D9_MARK, PSE1_VIO_D9, HIZB0_VIO, NAF1_VIO_D9), - PINMUX_DATA(VIO_D8_MARK, PSE0_VIO_D8, HIZB0_VIO, NAF0_VIO_D8), - PINMUX_DATA(VIO_D7_MARK, PSD11_VIO, VIO_D7_SCIF1_SCK), - PINMUX_DATA(VIO_D6_MARK, PSD11_VIO, VIO_D6_SCIF1_RXD), - PINMUX_DATA(VIO_D5_MARK, PSD11_VIO, VIO_D5_SCIF1_TXD), - PINMUX_DATA(VIO_D4_MARK, VIO_D4), - PINMUX_DATA(VIO_D3_MARK, VIO_D3), - PINMUX_DATA(VIO_D2_MARK, VIO_D2), - PINMUX_DATA(VIO_D1_MARK, VIO_D1), - PINMUX_DATA(VIO_D0_MARK, PSD10_VIO_D0, VIO_D0_LCDLCLK), - PINMUX_DATA(VIO_CLK_MARK, PSD12_VIO, MSELB9_VIO, VIO_CLK_SCIF1_RTS), - PINMUX_DATA(VIO_VD_MARK, PSD12_VIO, MSELB9_VIO, VIO_VD_SCIF1_CTS), - PINMUX_DATA(VIO_HD_MARK, PSD13_VIO, MSELB9_VIO, VIO_HD_SCIF2_RXD), - PINMUX_DATA(VIO_FLD_MARK, PSD13_VIO, HIZA9_VIO, VIO_FLD_SCIF2_CTS), - PINMUX_DATA(VIO_CKO_MARK, PSD13_VIO, HIZA9_VIO, VIO_CKO_SCIF2_RTS), - PINMUX_DATA(VIO_STEX_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEX_SCIF2_SCK), - PINMUX_DATA(VIO_STEM_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEM_SCIF2_TXD), - PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2, - HIZB0_VIO, FOE_VIO_VD2), - PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2, - HIZB1_VIO, HIZB1_VIO, FCE_VIO_HD2), - PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2, - HIZB1_VIO, FRB_VIO_CLK2), - - /* LCDC */ - PINMUX_DATA(LCDD23_MARK, HIZA8_LCDC, LCDD23), - PINMUX_DATA(LCDD22_MARK, HIZA8_LCDC, LCDD22), - PINMUX_DATA(LCDD21_MARK, HIZA8_LCDC, LCDD21), - PINMUX_DATA(LCDD20_MARK, HIZA8_LCDC, LCDD20), - PINMUX_DATA(LCDD19_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD19_DV_CLKI), - PINMUX_DATA(LCDD18_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD18_DV_CLK), - PINMUX_DATA(LCDD17_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, - LCDD17_DV_HSYNC), - PINMUX_DATA(LCDD16_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, - LCDD16_DV_VSYNC), - PINMUX_DATA(LCDD15_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD15_DV_D15), - PINMUX_DATA(LCDD14_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD14_DV_D14), - PINMUX_DATA(LCDD13_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD13_DV_D13), - PINMUX_DATA(LCDD12_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD12_DV_D12), - PINMUX_DATA(LCDD11_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD11_DV_D11), - PINMUX_DATA(LCDD10_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD10_DV_D10), - PINMUX_DATA(LCDD9_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD9_DV_D9), - PINMUX_DATA(LCDD8_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD8_DV_D8), - PINMUX_DATA(LCDD7_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD7_DV_D7), - PINMUX_DATA(LCDD6_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD6_DV_D6), - PINMUX_DATA(LCDD5_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD5_DV_D5), - PINMUX_DATA(LCDD4_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD4_DV_D4), - PINMUX_DATA(LCDD3_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD3_DV_D3), - PINMUX_DATA(LCDD2_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD2_DV_D2), - PINMUX_DATA(LCDD1_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD1_DV_D1), - PINMUX_DATA(LCDD0_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD0_DV_D0), - PINMUX_DATA(LCDLCLK_MARK, PSD10_LCDLCLK, VIO_D0_LCDLCLK), - /* Main LCD */ - PINMUX_DATA(LCDDON_MARK, PSD2_LCDDON, HIZA7_LCDC, LCDDON_LCDDON2), - PINMUX_DATA(LCDVCPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC, - HIZA6_LCDC, LCDVCPWC_LCDVCPWC2), - PINMUX_DATA(LCDVEPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC, - HIZA6_LCDC, LCDVEPWC_LCDVEPWC2), - PINMUX_DATA(LCDVSYN_MARK, HIZA7_LCDC, LCDVSYN), - /* Main LCD - RGB Mode */ - PINMUX_DATA(LCDDCK_MARK, MSELB8_RGB, HIZA8_LCDC, LCDDCK_LCDWR), - PINMUX_DATA(LCDHSYN_MARK, MSELB8_RGB, HIZA7_LCDC, LCDHSYN_LCDCS), - PINMUX_DATA(LCDDISP_MARK, MSELB8_RGB, HIZA7_LCDC, LCDDISP_LCDRS), - /* Main LCD - SYS Mode */ - PINMUX_DATA(LCDRS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDDISP_LCDRS), - PINMUX_DATA(LCDCS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDHSYN_LCDCS), - PINMUX_DATA(LCDWR_MARK, MSELB8_SYS, HIZA8_LCDC, LCDDCK_LCDWR), - PINMUX_DATA(LCDRD_MARK, HIZA7_LCDC, LCDRD), - /* Sub LCD - SYS Mode */ - PINMUX_DATA(LCDDON2_MARK, PSD2_LCDDON2, HIZA7_LCDC, LCDDON_LCDDON2), - PINMUX_DATA(LCDVCPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2, - HIZA6_LCDC, LCDVCPWC_LCDVCPWC2), - PINMUX_DATA(LCDVEPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2, - HIZA6_LCDC, LCDVEPWC_LCDVEPWC2), - PINMUX_DATA(LCDVSYN2_MARK, PSE12_LCDVSYN2, HIZA8_LCDC, LCDVSYN2_DACK), - PINMUX_DATA(LCDCS2_MARK, PSD5_LCDCS2, CS6B_CE1B_LCDCS2), - - /* BSC */ - PINMUX_DATA(IOIS16_MARK, IOIS16), - PINMUX_DATA(A25_MARK, A25), - PINMUX_DATA(A24_MARK, A24), - PINMUX_DATA(A23_MARK, A23), - PINMUX_DATA(A22_MARK, A22), - PINMUX_DATA(BS_MARK, PSA9_BS, IRQ4_BS), - PINMUX_DATA(CS6B_CE1B_MARK, PSD5_CS6B_CE1B, CS6B_CE1B_LCDCS2), - PINMUX_DATA(WAIT_MARK, WAIT), - PINMUX_DATA(CS6A_CE2B_MARK, CS6A_CE2B), - - /* SBSC */ - PINMUX_DATA(HPD63_MARK, HPD63), - PINMUX_DATA(HPD62_MARK, HPD62), - PINMUX_DATA(HPD61_MARK, HPD61), - PINMUX_DATA(HPD60_MARK, HPD60), - PINMUX_DATA(HPD59_MARK, HPD59), - PINMUX_DATA(HPD58_MARK, HPD58), - PINMUX_DATA(HPD57_MARK, HPD57), - PINMUX_DATA(HPD56_MARK, HPD56), - PINMUX_DATA(HPD55_MARK, HPD55), - PINMUX_DATA(HPD54_MARK, HPD54), - PINMUX_DATA(HPD53_MARK, HPD53), - PINMUX_DATA(HPD52_MARK, HPD52), - PINMUX_DATA(HPD51_MARK, HPD51), - PINMUX_DATA(HPD50_MARK, HPD50), - PINMUX_DATA(HPD49_MARK, HPD49), - PINMUX_DATA(HPD48_MARK, HPD48), - PINMUX_DATA(HPDQM7_MARK, HPDQM7), - PINMUX_DATA(HPDQM6_MARK, HPDQM6), - PINMUX_DATA(HPDQM5_MARK, HPDQM5), - PINMUX_DATA(HPDQM4_MARK, HPDQM4), - - /* IRQ */ - PINMUX_DATA(IRQ0_MARK, HIZC8_IRQ0, IRQ0), - PINMUX_DATA(IRQ1_MARK, HIZC9_IRQ1, IRQ1), - PINMUX_DATA(IRQ2_MARK, PSA4_IRQ2, HIZC10_IRQ2, IRQ2_SDHID2), - PINMUX_DATA(IRQ3_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_IRQ3, - HIZC11_IRQ3, PTQ0), - PINMUX_DATA(IRQ4_MARK, PSA9_IRQ4, HIZC12_IRQ4, IRQ4_BS), - PINMUX_DATA(IRQ5_MARK, HIZC13_IRQ5, IRQ5), - PINMUX_DATA(IRQ6_MARK, PSA15_IRQ6, HIZC14_IRQ6, KEYIN0_IRQ6), - PINMUX_DATA(IRQ7_MARK, PSA14_IRQ7, HIZC15_IRQ7, KEYIN4_IRQ7), - - /* SDHI */ - PINMUX_DATA(SDHICD_MARK, SDHICD), - PINMUX_DATA(SDHIWP_MARK, SDHIWP), - PINMUX_DATA(SDHID3_MARK, SDHID3), - PINMUX_DATA(SDHID2_MARK, PSA4_SDHID2, IRQ2_SDHID2), - PINMUX_DATA(SDHID1_MARK, SDHID1), - PINMUX_DATA(SDHID0_MARK, SDHID0), - PINMUX_DATA(SDHICMD_MARK, SDHICMD), - PINMUX_DATA(SDHICLK_MARK, SDHICLK), - - /* SIU - Port A */ - PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, SIUAOLR_SIOF1_SYNC), - PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, SIUAOBT_SIOF1_SCK), - PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, SIUAISLD_SIOF1_RXD), - PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, SIUAILR_SIOF1_SS2), - PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, SIUAIBT_SIOF1_SS1), - PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, SIUAOSLD_SIOF1_TXD), - PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, PSB1_SIUMCKA, PTK0), - PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, PTK0), - - /* SIU - Port B */ - PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR), - PINMUX_DATA(SIUBOBT_MARK, PSB10_SIUBOBT, SIOSCK_SIUBOBT), - PINMUX_DATA(SIUBISLD_MARK, PSB14_SIUBISLD, SIORXD_SIUBISLD), - PINMUX_DATA(SIUBILR_MARK, PSB13_SIUBILR, SIOD_SIUBILR), - PINMUX_DATA(SIUBIBT_MARK, PSB12_SIUBIBT, SIOSTRB0_SIUBIBT), - PINMUX_DATA(SIUBOSLD_MARK, PSB15_SIUBOSLD, SIOTXD_SIUBOSLD), - PINMUX_DATA(SIUMCKB_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIUMCKB, PTF6), - PINMUX_DATA(SIUFCKB_MARK, PSD9_SIUFCKB, PTF6), - - /* AUD */ - PINMUX_DATA(AUDSYNC_MARK, AUDSYNC), - PINMUX_DATA(AUDATA3_MARK, AUDATA3), - PINMUX_DATA(AUDATA2_MARK, AUDATA2), - PINMUX_DATA(AUDATA1_MARK, AUDATA1), - PINMUX_DATA(AUDATA0_MARK, AUDATA0), - - /* DMAC */ - PINMUX_DATA(DACK_MARK, PSE12_DACK, LCDVSYN2_DACK), - PINMUX_DATA(DREQ0_MARK, DREQ0), - - /* VOU */ - PINMUX_DATA(DV_CLKI_MARK, PSD0_DV, LCDD19_DV_CLKI), - PINMUX_DATA(DV_CLK_MARK, PSD0_DV, LCDD18_DV_CLK), - PINMUX_DATA(DV_HSYNC_MARK, PSD0_DV, LCDD17_DV_HSYNC), - PINMUX_DATA(DV_VSYNC_MARK, PSD0_DV, LCDD16_DV_VSYNC), - PINMUX_DATA(DV_D15_MARK, PSD0_DV, LCDD15_DV_D15), - PINMUX_DATA(DV_D14_MARK, PSD0_DV, LCDD14_DV_D14), - PINMUX_DATA(DV_D13_MARK, PSD0_DV, LCDD13_DV_D13), - PINMUX_DATA(DV_D12_MARK, PSD0_DV, LCDD12_DV_D12), - PINMUX_DATA(DV_D11_MARK, PSD0_DV, LCDD11_DV_D11), - PINMUX_DATA(DV_D10_MARK, PSD0_DV, LCDD10_DV_D10), - PINMUX_DATA(DV_D9_MARK, PSD0_DV, LCDD9_DV_D9), - PINMUX_DATA(DV_D8_MARK, PSD0_DV, LCDD8_DV_D8), - PINMUX_DATA(DV_D7_MARK, PSD0_DV, LCDD7_DV_D7), - PINMUX_DATA(DV_D6_MARK, PSD0_DV, LCDD6_DV_D6), - PINMUX_DATA(DV_D5_MARK, PSD0_DV, LCDD5_DV_D5), - PINMUX_DATA(DV_D4_MARK, PSD0_DV, LCDD4_DV_D4), - PINMUX_DATA(DV_D3_MARK, PSD0_DV, LCDD3_DV_D3), - PINMUX_DATA(DV_D2_MARK, PSD0_DV, LCDD2_DV_D2), - PINMUX_DATA(DV_D1_MARK, PSD0_DV, LCDD1_DV_D1), - PINMUX_DATA(DV_D0_MARK, PSD0_DV, LCDD0_DV_D0), - - /* CPG */ - PINMUX_DATA(STATUS0_MARK, STATUS0), - PINMUX_DATA(PDSTATUS_MARK, PDSTATUS), - - /* SIOF0 */ - PINMUX_DATA(SIOF0_MCK_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_SIOF0_MCK, PTQ0), - PINMUX_DATA(SIOF0_SCK_MARK, PSB5_SIOF0_SCK, SIOF0_SCK_TS_SCK), - PINMUX_DATA(SIOF0_SYNC_MARK, PSB4_SIOF0_SYNC, SIOF0_SYNC_TS_SDEN), - PINMUX_DATA(SIOF0_SS1_MARK, PSB3_SIOF0_SS1, SIOF0_SS1_TS_SPSYNC), - PINMUX_DATA(SIOF0_SS2_MARK, PSB2_SIOF0_SS2, SIOF0_SS2_SIM_RST), - PINMUX_DATA(SIOF0_TXD_MARK, PSE14_SIOF0_TXD_IRDA_OUT, - PSB7_SIOF0_TXD, PTQ1), - PINMUX_DATA(SIOF0_RXD_MARK, PSE13_SIOF0_RXD_IRDA_IN, - PSB6_SIOF0_RXD, PTQ2), - - /* SIOF1 */ - PINMUX_DATA(SIOF1_MCK_MARK, PSE11_SIUMCKA_SIOF1_MCK, - PSB1_SIOF1_MCK, PTK0), - PINMUX_DATA(SIOF1_SCK_MARK, PSC14_SIOF1_SCK, SIUAOBT_SIOF1_SCK), - PINMUX_DATA(SIOF1_SYNC_MARK, PSC13_SIOF1_SYNC, SIUAOLR_SIOF1_SYNC), - PINMUX_DATA(SIOF1_SS1_MARK, PSC12_SIOF1_SS1, SIUAIBT_SIOF1_SS1), - PINMUX_DATA(SIOF1_SS2_MARK, PSC11_SIOF1_SS2, SIUAILR_SIOF1_SS2), - PINMUX_DATA(SIOF1_TXD_MARK, PSB0_SIOF1_TXD, SIUAOSLD_SIOF1_TXD), - PINMUX_DATA(SIOF1_RXD_MARK, PSC15_SIOF1_RXD, SIUAISLD_SIOF1_RXD), - - /* SIM */ - PINMUX_DATA(SIM_D_MARK, PSE15_SIM_D, PTQ0), - PINMUX_DATA(SIM_CLK_MARK, PSE14_SIM_CLK, PTQ1), - PINMUX_DATA(SIM_RST_MARK, PSB2_SIM_RST, SIOF0_SS2_SIM_RST), - - /* TSIF */ - PINMUX_DATA(TS_SDAT_MARK, PSE13_TS_SDAT, PTQ2), - PINMUX_DATA(TS_SCK_MARK, PSB5_TS_SCK, SIOF0_SCK_TS_SCK), - PINMUX_DATA(TS_SDEN_MARK, PSB4_TS_SDEN, SIOF0_SYNC_TS_SDEN), - PINMUX_DATA(TS_SPSYNC_MARK, PSB3_TS_SPSYNC, SIOF0_SS1_TS_SPSYNC), - - /* IRDA */ - PINMUX_DATA(IRDA_IN_MARK, PSE13_SIOF0_RXD_IRDA_IN, PSB6_IRDA_IN, PTQ2), - PINMUX_DATA(IRDA_OUT_MARK, PSE14_SIOF0_TXD_IRDA_OUT, - PSB7_IRDA_OUT, PTQ1), - - /* TPU */ - PINMUX_DATA(TPUTO_MARK, PSD8_TPUTO, SCIF0_SCK_TPUTO), - - /* FLCTL */ - PINMUX_DATA(FCE_MARK, PSE3_FLCTL, FCE_VIO_HD2), - PINMUX_DATA(NAF7_MARK, PSC0_NAF, HIZA10_NAF, NAF7_VIO_D15), - PINMUX_DATA(NAF6_MARK, PSC0_NAF, HIZA10_NAF, NAF6_VIO_D14), - PINMUX_DATA(NAF5_MARK, PSC0_NAF, HIZA10_NAF, NAF5_VIO_D13), - PINMUX_DATA(NAF4_MARK, PSC0_NAF, HIZA10_NAF, NAF4_VIO_D12), - PINMUX_DATA(NAF3_MARK, PSC0_NAF, HIZA10_NAF, NAF3_VIO_D11), - PINMUX_DATA(NAF2_MARK, PSE2_NAF2, HIZB0_VIO, NAF2_VIO_D10), - PINMUX_DATA(NAF1_MARK, PSE1_NAF1, HIZB0_VIO, NAF1_VIO_D9), - PINMUX_DATA(NAF0_MARK, PSE0_NAF0, HIZB0_VIO, NAF0_VIO_D8), - PINMUX_DATA(FCDE_MARK, FCDE), - PINMUX_DATA(FOE_MARK, PSE3_FLCTL, HIZB0_VIO, FOE_VIO_VD2), - PINMUX_DATA(FSC_MARK, FSC), - PINMUX_DATA(FWE_MARK, FWE), - PINMUX_DATA(FRB_MARK, PSE3_FLCTL, FRB_VIO_CLK2), - - /* KEYSC */ - PINMUX_DATA(KEYIN0_MARK, PSA15_KEYIN0, HIZC14_IRQ6, KEYIN0_IRQ6), - PINMUX_DATA(KEYIN1_MARK, HIZA14_KEYSC, KEYIN1), - PINMUX_DATA(KEYIN2_MARK, HIZA14_KEYSC, KEYIN2), - PINMUX_DATA(KEYIN3_MARK, HIZA14_KEYSC, KEYIN3), - PINMUX_DATA(KEYIN4_MARK, PSA14_KEYIN4, HIZC15_IRQ7, KEYIN4_IRQ7), - PINMUX_DATA(KEYOUT0_MARK, HIZA14_KEYSC, KEYOUT0), - PINMUX_DATA(KEYOUT1_MARK, HIZA14_KEYSC, KEYOUT1), - PINMUX_DATA(KEYOUT2_MARK, HIZA14_KEYSC, KEYOUT2), - PINMUX_DATA(KEYOUT3_MARK, HIZA14_KEYSC, KEYOUT3), - PINMUX_DATA(KEYOUT4_IN6_MARK, HIZA14_KEYSC, KEYOUT4_IN6), - PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - /* PTA */ - PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), - PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), - PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), - PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), - PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), - PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), - PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), - PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), - - /* PTB */ - PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), - PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), - PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), - PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), - PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), - PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), - PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), - PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), - - /* PTC */ - PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), - PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), - PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), - PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), - PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), - PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), - - /* PTD */ - PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), - PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), - PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), - PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), - PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), - PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), - PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), - PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), - - /* PTE */ - PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), - PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), - PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), - PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), - PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), - PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), - - /* PTF */ - PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), - PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), - PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), - PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), - PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), - PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), - PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), - - /* PTG */ - PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), - PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), - PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), - PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), - PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), - - /* PTH */ - PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), - PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), - PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), - PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), - PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), - PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), - PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), - PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), - - /* PTJ */ - PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), - PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), - PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), - PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), - PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), - - /* PTK */ - PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), - PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), - PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), - PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), - PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), - PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), - PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), - - /* PTL */ - PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), - PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), - PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), - PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), - PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), - PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), - PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), - PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), - - /* PTM */ - PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), - PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), - PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), - PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), - PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), - PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), - PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), - PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), - - /* PTN */ - PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), - PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), - PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), - PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), - PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), - PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), - PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), - PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), - - /* PTQ */ - PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), - PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), - PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), - PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), - PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), - PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), - PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), - - /* PTR */ - PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), - PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), - PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), - PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), - PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), - - /* PTS */ - PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), - PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), - PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), - PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), - PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), - - /* PTT */ - PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), - PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), - PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), - PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), - PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), - - /* PTU */ - PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), - PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), - PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), - PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), - PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), - - /* PTV */ - PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), - PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), - PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), - PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), - PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), - - /* PTW */ - PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), - PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), - PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), - PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), - PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), - PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), - PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), - - /* PTX */ - PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), - PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), - PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), - PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), - PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), - PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), - PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), - - /* PTY */ - PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), - PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), - PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), - PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), - PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), - PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), - - /* PTZ */ - PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), - PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), - PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), - PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), - PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), - - /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), - - /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - - /* SCIF2 */ - PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), - - /* SIO */ - PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK), - PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK), - PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK), - PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK), - PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK), - - /* CEU */ - PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), - PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK), - PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), - - /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), - PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), - PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), - PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), - PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), - PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), - PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), - PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), - PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), - PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), - PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), - PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), - PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), - PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), - PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), - PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), - PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), - PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), - PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), - PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), - PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), - PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), - PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), - PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), - /* Main LCD */ - PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), - /* Main LCD - RGB Mode */ - PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), - PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), - /* Main LCD - SYS Mode */ - PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), - PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), - PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), - /* Sub LCD - SYS Mode */ - PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK), - - /* BSC */ - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), - - /* SBSC */ - PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK), - PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK), - PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK), - PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK), - PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK), - PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK), - PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK), - PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK), - PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK), - PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK), - PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK), - PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK), - PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK), - PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK), - PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK), - PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK), - - /* IRQ */ - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), - - /* SDHI */ - PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK), - PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK), - PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK), - PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK), - PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK), - PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK), - PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK), - - /* SIU - Port A */ - PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK), - PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK), - - /* SIU - Port B */ - PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK), - PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK), - - /* AUD */ - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), - - /* DMAC */ - PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - - /* VOU */ - PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), - PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), - PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), - PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), - PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), - PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), - PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), - PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), - PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), - PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), - PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), - PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), - PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), - PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), - PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), - PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), - - /* CPG */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), - - /* SIOF0 */ - PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), - - /* SIOF1 */ - PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), - - /* SIM */ - PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), - PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), - - /* TSIF */ - PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK), - PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK), - PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK), - PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK), - - /* IRDA */ - PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), - PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), - - /* TPU */ - PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK), - - /* FLCTL */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), - PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), - PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), - PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), - PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), - PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), - PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), - PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), - PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), - PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), - PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - - /* KEYSC */ - PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { - VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN, - VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN, - VIO_D5_SCIF1_TXD, PTA5_OUT, PTA5_IN_PD, PTA5_IN, - VIO_D4, 0, PTA4_IN_PD, PTA4_IN, - VIO_D3, 0, PTA3_IN_PD, PTA3_IN, - VIO_D2, 0, PTA2_IN_PD, PTA2_IN, - VIO_D1, 0, PTA1_IN_PD, PTA1_IN, - VIO_D0_LCDLCLK, 0, PTA0_IN_PD, PTA0_IN } - }, - { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { - HPD55, PTB7_OUT, 0, PTB7_IN, - HPD54, PTB6_OUT, 0, PTB6_IN, - HPD53, PTB5_OUT, 0, PTB5_IN, - HPD52, PTB4_OUT, 0, PTB4_IN, - HPD51, PTB3_OUT, 0, PTB3_IN, - HPD50, PTB2_OUT, 0, PTB2_IN, - HPD49, PTB1_OUT, 0, PTB1_IN, - HPD48, PTB0_OUT, 0, PTB0_IN } - }, - { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { - 0, 0, PTC7_IN_PU, PTC7_IN, - 0, 0, 0, 0, - IOIS16, 0, PTC5_IN_PU, PTC5_IN, - HPDQM7, PTC4_OUT, 0, PTC4_IN, - HPDQM6, PTC3_OUT, 0, PTC3_IN, - HPDQM5, PTC2_OUT, 0, PTC2_IN, - 0, 0, 0, 0, - HPDQM4, PTC0_OUT, 0, PTC0_IN } - }, - { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { - SDHICD, 0, PTD7_IN_PU, PTD7_IN, - SDHIWP, PTD6_OUT, PTD6_IN_PU, PTD6_IN, - SDHID3, PTD5_OUT, PTD5_IN_PU, PTD5_IN, - IRQ2_SDHID2, PTD4_OUT, PTD4_IN_PU, PTD4_IN, - SDHID1, PTD3_OUT, PTD3_IN_PU, PTD3_IN, - SDHID0, PTD2_OUT, PTD2_IN_PU, PTD2_IN, - SDHICMD, PTD1_OUT, PTD1_IN_PU, PTD1_IN, - SDHICLK, PTD0_OUT, 0, 0 } - }, - { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { - A25, PTE7_OUT, PTE7_IN_PD, PTE7_IN, - A24, PTE6_OUT, PTE6_IN_PD, PTE6_IN, - A23, PTE5_OUT, PTE5_IN_PD, PTE5_IN, - A22, PTE4_OUT, PTE4_IN_PD, PTE4_IN, - 0, 0, 0, 0, - 0, 0, 0, 0, - IRQ5, PTE1_OUT, PTE1_IN_PD, PTE1_IN, - IRQ4_BS, PTE0_OUT, PTE0_IN_PD, PTE0_IN } - }, - { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { - 0, 0, 0, 0, - PTF6, PTF6_OUT, PTF6_IN_PD, PTF6_IN, - SIOSCK_SIUBOBT, PTF5_OUT, PTF5_IN_PD, PTF5_IN, - SIOSTRB1_SIUBOLR, PTF4_OUT, PTF4_IN_PD, PTF4_IN, - SIOSTRB0_SIUBIBT, PTF3_OUT, PTF3_IN_PD, PTF3_IN, - SIOD_SIUBILR, PTF2_OUT, PTF2_IN_PD, PTF2_IN, - SIORXD_SIUBISLD, 0, PTF1_IN_PD, PTF1_IN, - SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 } - }, - { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - AUDSYNC, PTG4_OUT, 0, 0, - AUDATA3, PTG3_OUT, 0, 0, - AUDATA2, PTG2_OUT, 0, 0, - AUDATA1, PTG1_OUT, 0, 0, - AUDATA0, PTG0_OUT, 0, 0 } - }, - { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { - LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0, - LCDVSYN2_DACK, PTH6_OUT, PTH6_IN_PD, PTH6_IN, - LCDVSYN, PTH5_OUT, PTH5_IN_PD, PTH5_IN, - LCDDISP_LCDRS, PTH4_OUT, 0, 0, - LCDHSYN_LCDCS, PTH3_OUT, 0, 0, - LCDDON_LCDDON2, PTH2_OUT, 0, 0, - LCDD17_DV_HSYNC, PTH1_OUT, PTH1_IN_PD, PTH1_IN, - LCDD16_DV_VSYNC, PTH0_OUT, PTH0_IN_PD, PTH0_IN } - }, - { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { - STATUS0, PTJ7_OUT, 0, 0, - 0, PTJ6_OUT, 0, 0, - PDSTATUS, PTJ5_OUT, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - IRQ1, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, - IRQ0, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } - }, - { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { - 0, 0, 0, 0, - SIUAILR_SIOF1_SS2, PTK6_OUT, PTK6_IN_PD, PTK6_IN, - SIUAIBT_SIOF1_SS1, PTK5_OUT, PTK5_IN_PD, PTK5_IN, - SIUAOLR_SIOF1_SYNC, PTK4_OUT, PTK4_IN_PD, PTK4_IN, - SIUAOBT_SIOF1_SCK, PTK3_OUT, PTK3_IN_PD, PTK3_IN, - SIUAISLD_SIOF1_RXD, 0, PTK2_IN_PD, PTK2_IN, - SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0, - PTK0, PTK0_OUT, PTK0_IN_PD, PTK0_IN } - }, - { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { - LCDD15_DV_D15, PTL7_OUT, PTL7_IN_PD, PTL7_IN, - LCDD14_DV_D14, PTL6_OUT, PTL6_IN_PD, PTL6_IN, - LCDD13_DV_D13, PTL5_OUT, PTL5_IN_PD, PTL5_IN, - LCDD12_DV_D12, PTL4_OUT, PTL4_IN_PD, PTL4_IN, - LCDD11_DV_D11, PTL3_OUT, PTL3_IN_PD, PTL3_IN, - LCDD10_DV_D10, PTL2_OUT, PTL2_IN_PD, PTL2_IN, - LCDD9_DV_D9, PTL1_OUT, PTL1_IN_PD, PTL1_IN, - LCDD8_DV_D8, PTL0_OUT, PTL0_IN_PD, PTL0_IN } - }, - { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { - LCDD7_DV_D7, PTM7_OUT, PTM7_IN_PD, PTM7_IN, - LCDD6_DV_D6, PTM6_OUT, PTM6_IN_PD, PTM6_IN, - LCDD5_DV_D5, PTM5_OUT, PTM5_IN_PD, PTM5_IN, - LCDD4_DV_D4, PTM4_OUT, PTM4_IN_PD, PTM4_IN, - LCDD3_DV_D3, PTM3_OUT, PTM3_IN_PD, PTM3_IN, - LCDD2_DV_D2, PTM2_OUT, PTM2_IN_PD, PTM2_IN, - LCDD1_DV_D1, PTM1_OUT, PTM1_IN_PD, PTM1_IN, - LCDD0_DV_D0, PTM0_OUT, PTM0_IN_PD, PTM0_IN } - }, - { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { - HPD63, PTN7_OUT, 0, PTN7_IN, - HPD62, PTN6_OUT, 0, PTN6_IN, - HPD61, PTN5_OUT, 0, PTN5_IN, - HPD60, PTN4_OUT, 0, PTN4_IN, - HPD59, PTN3_OUT, 0, PTN3_IN, - HPD58, PTN2_OUT, 0, PTN2_IN, - HPD57, PTN1_OUT, 0, PTN1_IN, - HPD56, PTN0_OUT, 0, PTN0_IN } - }, - { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { - 0, 0, 0, 0, - SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0, - SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, PTQ5_IN_PD, PTQ5_IN, - SIOF0_SYNC_TS_SDEN, PTQ4_OUT, PTQ4_IN_PD, PTQ4_IN, - SIOF0_SCK_TS_SCK, PTQ3_OUT, PTQ3_IN_PD, PTQ3_IN, - PTQ2, 0, PTQ2_IN_PD, PTQ2_IN, - PTQ1, PTQ1_OUT, 0, 0, - PTQ0, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN } - }, - { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - LCDRD, PTR4_OUT, 0, 0, - CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0, - WAIT, 0, PTR2_IN_PU, PTR2_IN, - LCDDCK_LCDWR, PTR1_OUT, 0, 0, - LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 } - }, - { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - SCIF0_CTS_SIUAISPD, 0, PTS4_IN_PD, PTS4_IN, - SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0, - SCIF0_SCK_TPUTO, PTS2_OUT, PTS2_IN_PD, PTS2_IN, - SCIF0_RXD, 0, PTS1_IN_PD, PTS1_IN, - SCIF0_TXD, PTS0_OUT, 0, 0 } - }, - { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - FOE_VIO_VD2, PTT4_OUT, PTT4_IN_PD, PTT4_IN, - FWE, PTT3_OUT, PTT3_IN_PD, PTT3_IN, - FSC, PTT2_OUT, PTT2_IN_PD, PTT2_IN, - DREQ0, 0, PTT1_IN_PD, PTT1_IN, - FCDE, PTT0_OUT, 0, 0 } - }, - { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - NAF2_VIO_D10, PTU4_OUT, PTU4_IN_PD, PTU4_IN, - NAF1_VIO_D9, PTU3_OUT, PTU3_IN_PD, PTU3_IN, - NAF0_VIO_D8, PTU2_OUT, PTU2_IN_PD, PTU2_IN, - FRB_VIO_CLK2, 0, PTU1_IN_PD, PTU1_IN, - FCE_VIO_HD2, PTU0_OUT, PTU0_IN_PD, PTU0_IN } - }, - { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - NAF7_VIO_D15, PTV4_OUT, PTV4_IN_PD, PTV4_IN, - NAF6_VIO_D14, PTV3_OUT, PTV3_IN_PD, PTV3_IN, - NAF5_VIO_D13, PTV2_OUT, PTV2_IN_PD, PTV2_IN, - NAF4_VIO_D12, PTV1_OUT, PTV1_IN_PD, PTV1_IN, - NAF3_VIO_D11, PTV0_OUT, PTV0_IN_PD, PTV0_IN } - }, - { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { - 0, 0, 0, 0, - VIO_FLD_SCIF2_CTS, 0, PTW6_IN_PD, PTW6_IN, - VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0, - VIO_STEX_SCIF2_SCK, PTW4_OUT, PTW4_IN_PD, PTW4_IN, - VIO_STEM_SCIF2_TXD, PTW3_OUT, PTW3_IN_PD, PTW3_IN, - VIO_HD_SCIF2_RXD, PTW2_OUT, PTW2_IN_PD, PTW2_IN, - VIO_VD_SCIF1_CTS, PTW1_OUT, PTW1_IN_PD, PTW1_IN, - VIO_CLK_SCIF1_RTS, PTW0_OUT, PTW0_IN_PD, PTW0_IN } - }, - { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { - 0, 0, 0, 0, - CS6A_CE2B, PTX6_OUT, PTX6_IN_PU, PTX6_IN, - LCDD23, PTX5_OUT, PTX5_IN_PD, PTX5_IN, - LCDD22, PTX4_OUT, PTX4_IN_PD, PTX4_IN, - LCDD21, PTX3_OUT, PTX3_IN_PD, PTX3_IN, - LCDD20, PTX2_OUT, PTX2_IN_PD, PTX2_IN, - LCDD19_DV_CLKI, PTX1_OUT, PTX1_IN_PD, PTX1_IN, - LCDD18_DV_CLK, PTX0_OUT, PTX0_IN_PD, PTX0_IN } +static struct resource sh7722_pfc_resources[] = { + [0] = { + .start = 0xa4050100, + .end = 0xa405018f, + .flags = IORESOURCE_MEM, }, - { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - KEYOUT5_IN5, PTY5_OUT, PTY5_IN_PU, PTY5_IN, - KEYOUT4_IN6, PTY4_OUT, PTY4_IN_PU, PTY4_IN, - KEYOUT3, PTY3_OUT, PTY3_IN_PU, PTY3_IN, - KEYOUT2, PTY2_OUT, PTY2_IN_PU, PTY2_IN, - KEYOUT1, PTY1_OUT, 0, 0, - KEYOUT0, PTY0_OUT, PTY0_IN_PU, PTY0_IN } - }, - { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - KEYIN4_IRQ7, 0, PTZ5_IN_PU, PTZ5_IN, - KEYIN3, 0, PTZ4_IN_PU, PTZ4_IN, - KEYIN2, 0, PTZ3_IN_PU, PTZ3_IN, - KEYIN1, 0, PTZ2_IN_PU, PTZ2_IN, - KEYIN0_IRQ6, 0, PTZ1_IN_PU, PTZ1_IN, - 0, 0, 0, 0 } - }, - { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { - PSA15_KEYIN0, PSA15_IRQ6, - PSA14_KEYIN4, PSA14_IRQ7, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - PSA9_IRQ4, PSA9_BS, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - PSA4_IRQ2, PSA4_SDHID2, - 0, 0, - 0, 0, - 0, 0, - 0, 0 } - }, - { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) { - PSB15_SIOTXD, PSB15_SIUBOSLD, - PSB14_SIORXD, PSB14_SIUBISLD, - PSB13_SIOD, PSB13_SIUBILR, - PSB12_SIOSTRB0, PSB12_SIUBIBT, - PSB11_SIOSTRB1, PSB11_SIUBOLR, - PSB10_SIOSCK, PSB10_SIUBOBT, - PSB9_SIOMCK, PSB9_SIUMCKB, - PSB8_SIOF0_MCK, PSB8_IRQ3, - PSB7_SIOF0_TXD, PSB7_IRDA_OUT, - PSB6_SIOF0_RXD, PSB6_IRDA_IN, - PSB5_SIOF0_SCK, PSB5_TS_SCK, - PSB4_SIOF0_SYNC, PSB4_TS_SDEN, - PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, - PSB2_SIOF0_SS2, PSB2_SIM_RST, - PSB1_SIUMCKA, PSB1_SIOF1_MCK, - PSB0_SIUAOSLD, PSB0_SIOF1_TXD } - }, - { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) { - PSC15_SIUAISLD, PSC15_SIOF1_RXD, - PSC14_SIUAOBT, PSC14_SIOF1_SCK, - PSC13_SIUAOLR, PSC13_SIOF1_SYNC, - PSC12_SIUAIBT, PSC12_SIOF1_SS1, - PSC11_SIUAILR, PSC11_SIOF1_SS2, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - PSC0_NAF, PSC0_VIO } - }, - { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) { - 0, 0, - 0, 0, - PSD13_VIO, PSD13_SCIF2, - PSD12_VIO, PSD12_SCIF1, - PSD11_VIO, PSD11_SCIF1, - PSD10_VIO_D0, PSD10_LCDLCLK, - PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB, - PSD8_SCIF0_SCK, PSD8_TPUTO, - PSD7_SCIF0_RTS, PSD7_SIUAOSPD, - PSD6_SCIF0_CTS, PSD6_SIUAISPD, - PSD5_CS6B_CE1B, PSD5_LCDCS2, - 0, 0, - PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2, - PSD2_LCDDON, PSD2_LCDDON2, - 0, 0, - PSD0_LCDD19_LCDD0, PSD0_DV } - }, - { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) { - PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D, - PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK, - PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, - PSE12_LCDVSYN2, PSE12_DACK, - PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - PSE3_FLCTL, PSE3_VIO, - PSE2_NAF2, PSE2_VIO_D10, - PSE1_NAF1, PSE1_VIO_D9, - PSE0_NAF0, PSE0_VIO_D8 } - }, - { PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1) { - 0, 0, - HIZA14_KEYSC, HIZA14_HIZ, - 0, 0, - 0, 0, - 0, 0, - HIZA10_NAF, HIZA10_HIZ, - HIZA9_VIO, HIZA9_HIZ, - HIZA8_LCDC, HIZA8_HIZ, - HIZA7_LCDC, HIZA7_HIZ, - HIZA6_LCDC, HIZA6_HIZ, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0 } - }, - { PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - HIZB1_VIO, HIZB1_HIZ, - HIZB0_VIO, HIZB0_HIZ } - }, - { PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1) { - HIZC15_IRQ7, HIZC15_HIZ, - HIZC14_IRQ6, HIZC14_HIZ, - HIZC13_IRQ5, HIZC13_HIZ, - HIZC12_IRQ4, HIZC12_HIZ, - HIZC11_IRQ3, HIZC11_HIZ, - HIZC10_IRQ2, HIZC10_HIZ, - HIZC9_IRQ1, HIZC9_HIZ, - HIZC8_IRQ0, HIZC8_HIZ, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0 } - }, - { PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - MSELB9_VIO, MSELB9_VIO2, - MSELB8_RGB, MSELB8_SYS, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0 } - }, - {} -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { - PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, - PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } - }, - { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) { - PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, - PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } - }, - { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) { - PTC7_DATA, 0, PTC5_DATA, PTC4_DATA, - PTC3_DATA, PTC2_DATA, 0, PTC0_DATA } - }, - { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { - PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, - PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } - }, - { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) { - PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, - 0, 0, PTE1_DATA, PTE0_DATA } - }, - { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) { - 0, PTF6_DATA, PTF5_DATA, PTF4_DATA, - PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } - }, - { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) { - 0, 0, 0, PTG4_DATA, - PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } - }, - { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) { - PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, - PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } - }, - { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) { - PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0, - 0, 0, PTJ1_DATA, PTJ0_DATA } - }, - { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) { - 0, PTK6_DATA, PTK5_DATA, PTK4_DATA, - PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } - }, - { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) { - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, - PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } - }, - { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) { - PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, - PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } - }, - { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) { - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, - PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } - }, - { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) { - 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, - PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } - }, - { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) { - 0, 0, 0, PTR4_DATA, - PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } - }, - { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) { - 0, 0, 0, PTS4_DATA, - PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } - }, - { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) { - 0, 0, 0, PTT4_DATA, - PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } - }, - { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) { - 0, 0, 0, PTU4_DATA, - PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } - }, - { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) { - 0, 0, 0, PTV4_DATA, - PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } - }, - { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) { - 0, PTW6_DATA, PTW5_DATA, PTW4_DATA, - PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } - }, - { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) { - 0, PTX6_DATA, PTX5_DATA, PTX4_DATA, - PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } - }, - { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) { - 0, PTY6_DATA, PTY5_DATA, PTY4_DATA, - PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } - }, - { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) { - 0, 0, PTZ5_DATA, PTZ4_DATA, - PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } - }, - { }, -}; - -static struct pinmux_info sh7722_pinmux_info = { - .name = "sh7722_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_KEYOUT5_IN5, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), }; static int __init plat_pinmux_setup(void) { - return register_pinmux(&sh7722_pinmux_info); + return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources, + ARRAY_SIZE(sh7722_pfc_resources)); } - arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c index 88bf5ecda84..99c637d5bf7 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c @@ -8,1902 +8,23 @@ * for more details. */ +#include <linux/bug.h> #include <linux/init.h> #include <linux/kernel.h> -#include <linux/gpio.h> -#include <cpu/sh7723.h> +#include <linux/ioport.h> +#include <cpu/pfc.h> -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, - PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA, - PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, - PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA, - PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, - PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA, - PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, - PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA, - PTE5_DATA, PTE4_DATA, PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA, - PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, - PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA, - PTG5_DATA, PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA, - PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, - PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, - PTJ7_DATA, PTJ5_DATA, PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA, - PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, - PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, - PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, - PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, - PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, - PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, - PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, - PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, - PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, - PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, - PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, - PTT5_DATA, PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, - PTU5_DATA, PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, - PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, - PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA, - PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, - PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA, - PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, - PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA, - PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, - PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA, - PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, - PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA, - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN, - PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN, - PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN, - PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN, - PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN, - PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN, - PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, - PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN, - PTE5_IN, PTE4_IN, PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN, - PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN, - PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN, - PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN, - PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN, - PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN, - PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN, - PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN, - PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, - PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, - PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN, - PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, - PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, - PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, - PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN, - PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN, - PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN, - PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN, - PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN, - PTT5_IN, PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN, - PTU5_IN, PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, - PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN, - PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, - PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN, - PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN, - PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN, - PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN, - PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN, - PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN, - PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN, - PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, - PINMUX_INPUT_END, - - PINMUX_INPUT_PULLUP_BEGIN, - PTA4_IN_PU, PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, - PTB2_IN_PU, PTB1_IN_PU, - PTR2_IN_PU, - PINMUX_INPUT_PULLUP_END, - - PINMUX_OUTPUT_BEGIN, - PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, - PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, - PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, - PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT, - PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT, - PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT, - PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT, - PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT, - PTE5_OUT, PTE4_OUT, PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT, - PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT, - PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT, - PTG5_OUT, PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT, - PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT, - PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, - PTJ7_OUT, PTJ5_OUT, PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT, - PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT, - PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT, - PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, - PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, - PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT, - PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, - PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, - PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, - PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT, - PTR1_OUT, PTR0_OUT, - PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT, - PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT, - PTT5_OUT, PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT, - PTU5_OUT, PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT, - PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT, - PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT, - PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT, - PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT, - PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT, - PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT, - PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT, - PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT, - PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT, - PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT, - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN, - PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN, - PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN, - PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN, - PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN, - PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN, - PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN, - PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN, - PTE5_FN, PTE4_FN, PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN, - PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN, - PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN, - PTG5_FN, PTG4_FN, PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN, - PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN, - PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN, - PTJ7_FN, PTJ5_FN, PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN, - PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN, - PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN, - PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, - PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN, - PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN, - PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN, - PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN, - PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN, - PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN, - PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN, - PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN, - PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN, - PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN, - PTT5_FN, PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN, - PTU5_FN, PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN, - PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN, - PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN, - PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN, - PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN, - PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN, - PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN, - PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN, - PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN, - PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, - PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, - - - PSA15_PSA14_FN1, PSA15_PSA14_FN2, - PSA13_PSA12_FN1, PSA13_PSA12_FN2, - PSA11_PSA10_FN1, PSA11_PSA10_FN2, - PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, - PSA3_PSA2_FN1, PSA3_PSA2_FN2, - PSB15_PSB14_FN1, PSB15_PSB14_FN2, - PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, - PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3, - PSB7_PSB6_FN1, PSB7_PSB6_FN2, - PSB5_PSB4_FN1, PSB5_PSB4_FN2, - PSB3_PSB2_FN1, PSB3_PSB2_FN2, - PSC15_PSC14_FN1, PSC15_PSC14_FN2, - PSC13_PSC12_FN1, PSC13_PSC12_FN2, - PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, - PSC9_PSC8_FN1, PSC9_PSC8_FN2, - PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, - PSD15_PSD14_FN1, PSD15_PSD14_FN2, - PSD13_PSD12_FN1, PSD13_PSD12_FN2, - PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, - PSD9_PSD8_FN1, PSD9_PSD8_FN2, - PSD7_PSD6_FN1, PSD7_PSD6_FN2, - PSD5_PSD4_FN1, PSD5_PSD4_FN2, - PSD3_PSD2_FN1, PSD3_PSD2_FN2, - PSD1_PSD0_FN1, PSD1_PSD0_FN2, - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - SCIF0_PTT_TXD_MARK, SCIF0_PTT_RXD_MARK, - SCIF0_PTT_SCK_MARK, SCIF0_PTU_TXD_MARK, - SCIF0_PTU_RXD_MARK, SCIF0_PTU_SCK_MARK, - - SCIF1_PTS_TXD_MARK, SCIF1_PTS_RXD_MARK, - SCIF1_PTS_SCK_MARK, SCIF1_PTV_TXD_MARK, - SCIF1_PTV_RXD_MARK, SCIF1_PTV_SCK_MARK, - - SCIF2_PTT_TXD_MARK, SCIF2_PTT_RXD_MARK, - SCIF2_PTT_SCK_MARK, SCIF2_PTU_TXD_MARK, - SCIF2_PTU_RXD_MARK, SCIF2_PTU_SCK_MARK, - - SCIF3_PTS_TXD_MARK, SCIF3_PTS_RXD_MARK, - SCIF3_PTS_SCK_MARK, SCIF3_PTS_RTS_MARK, - SCIF3_PTS_CTS_MARK, SCIF3_PTV_TXD_MARK, - SCIF3_PTV_RXD_MARK, SCIF3_PTV_SCK_MARK, - SCIF3_PTV_RTS_MARK, SCIF3_PTV_CTS_MARK, - - SCIF4_PTE_TXD_MARK, SCIF4_PTE_RXD_MARK, - SCIF4_PTE_SCK_MARK, SCIF4_PTN_TXD_MARK, - SCIF4_PTN_RXD_MARK, SCIF4_PTN_SCK_MARK, - - SCIF5_PTE_TXD_MARK, SCIF5_PTE_RXD_MARK, - SCIF5_PTE_SCK_MARK, SCIF5_PTN_TXD_MARK, - SCIF5_PTN_RXD_MARK, SCIF5_PTN_SCK_MARK, - - VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK, - VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK, - VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK, - VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK, - VIO_FLD_MARK, VIO_CKO_MARK, - VIO_VD1_MARK, VIO_HD1_MARK, VIO_CLK1_MARK, - VIO_HD2_MARK, VIO_VD2_MARK, VIO_CLK2_MARK, - - LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK, - LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK, - LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK, - LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK, - LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK, - LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK, - LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK, - LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK, - LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, - LCDLCLK_PTR_MARK, LCDLCLK_PTW_MARK, - - IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, - IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK, - - AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK, - AUDCK_MARK, AUDSYNC_MARK, - - SDHI0CD_PTD_MARK, SDHI0WP_PTD_MARK, - SDHI0D3_PTD_MARK, SDHI0D2_PTD_MARK, - SDHI0D1_PTD_MARK, SDHI0D0_PTD_MARK, - SDHI0CMD_PTD_MARK, SDHI0CLK_PTD_MARK, - - SDHI0CD_PTS_MARK, SDHI0WP_PTS_MARK, - SDHI0D3_PTS_MARK, SDHI0D2_PTS_MARK, - SDHI0D1_PTS_MARK, SDHI0D0_PTS_MARK, - SDHI0CMD_PTS_MARK, SDHI0CLK_PTS_MARK, - - SDHI1CD_MARK, SDHI1WP_MARK, SDHI1D3_MARK, SDHI1D2_MARK, - SDHI1D1_MARK, SDHI1D0_MARK, SDHI1CMD_MARK, SDHI1CLK_MARK, - - SIUAFCK_MARK, SIUAILR_MARK, SIUAIBT_MARK, SIUAISLD_MARK, - SIUAOLR_MARK, SIUAOBT_MARK, SIUAOSLD_MARK, SIUAMCK_MARK, - SIUAISPD_MARK, SIUAOSPD_MARK, - - SIUBFCK_MARK, SIUBILR_MARK, SIUBIBT_MARK, SIUBISLD_MARK, - SIUBOLR_MARK, SIUBOBT_MARK, SIUBOSLD_MARK, SIUBMCK_MARK, - - IRDA_IN_MARK, IRDA_OUT_MARK, - - DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK, - DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK, - DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK, - DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK, - DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK, - - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK, - KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, - KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK, - - MSIOF0_PTF_TXD_MARK, MSIOF0_PTF_RXD_MARK, MSIOF0_PTF_MCK_MARK, - MSIOF0_PTF_TSYNC_MARK, MSIOF0_PTF_TSCK_MARK, MSIOF0_PTF_RSYNC_MARK, - MSIOF0_PTF_RSCK_MARK, MSIOF0_PTF_SS1_MARK, MSIOF0_PTF_SS2_MARK, - - MSIOF0_PTT_TXD_MARK, MSIOF0_PTT_RXD_MARK, MSIOF0_PTX_MCK_MARK, - MSIOF0_PTT_TSYNC_MARK, MSIOF0_PTT_TSCK_MARK, MSIOF0_PTT_RSYNC_MARK, - MSIOF0_PTT_RSCK_MARK, MSIOF0_PTT_SS1_MARK, MSIOF0_PTT_SS2_MARK, - - MSIOF1_TXD_MARK, MSIOF1_RXD_MARK, MSIOF1_MCK_MARK, - MSIOF1_TSYNC_MARK, MSIOF1_TSCK_MARK, MSIOF1_RSYNC_MARK, - MSIOF1_RSCK_MARK, MSIOF1_SS1_MARK, MSIOF1_SS2_MARK, - - TS0_SDAT_MARK, TS0_SCK_MARK, TS0_SDEN_MARK, TS0_SPSYNC_MARK, - - FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK, - NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK, - FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK, - - DACK1_MARK, DREQ1_MARK, DACK0_MARK, DREQ0_MARK, - - AN3_MARK, AN2_MARK, AN1_MARK, AN0_MARK, ADTRG_MARK, - - STATUS0_MARK, PDSTATUS_MARK, - - TPUTO3_MARK, TPUTO2_MARK, TPUTO1_MARK, TPUTO0_MARK, - - D31_MARK, D30_MARK, D29_MARK, D28_MARK, - D27_MARK, D26_MARK, D25_MARK, D24_MARK, - D23_MARK, D22_MARK, D21_MARK, D20_MARK, - D19_MARK, D18_MARK, D17_MARK, D16_MARK, - IOIS16_MARK, WAIT_MARK, BS_MARK, - A25_MARK, A24_MARK, A23_MARK, A22_MARK, - CS6B_CE1B_MARK, CS6A_CE2B_MARK, - CS5B_CE1A_MARK, CS5A_CE2A_MARK, - WE3_ICIOWR_MARK, WE2_ICIORD_MARK, - - IDED15_MARK, IDED14_MARK, IDED13_MARK, IDED12_MARK, - IDED11_MARK, IDED10_MARK, IDED9_MARK, IDED8_MARK, - IDED7_MARK, IDED6_MARK, IDED5_MARK, IDED4_MARK, - IDED3_MARK, IDED2_MARK, IDED1_MARK, IDED0_MARK, - DIRECTION_MARK, EXBUF_ENB_MARK, IDERST_MARK, IODACK_MARK, - IODREQ_MARK, IDEIORDY_MARK, IDEINT_MARK, IDEIOWR_MARK, - IDEIORD_MARK, IDECS1_MARK, IDECS0_MARK, IDEA2_MARK, - IDEA1_MARK, IDEA0_MARK, - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - /* PTA GPIO */ - PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), - PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), - PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), - PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), - PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), - PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), - PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), - PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), - - /* PTB GPIO */ - PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), - PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), - PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), - PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), - PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), - PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), - PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), - PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), - - /* PTC GPIO */ - PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT), - PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT), - PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT), - PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), - PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), - PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), - PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT), - PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), - - /* PTD GPIO */ - PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT), - PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT), - PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT), - PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT), - PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT), - PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT), - PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT), - PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), - - /* PTE GPIO */ - PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT), - PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), - PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), - PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT), - PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT), - PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT), - - /* PTF GPIO */ - PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT), - PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT), - PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT), - PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT), - PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT), - PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT), - PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT), - PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT), - - /* PTG GPIO */ - PINMUX_DATA(PTG5_DATA, PTG5_OUT), - PINMUX_DATA(PTG4_DATA, PTG4_OUT), - PINMUX_DATA(PTG3_DATA, PTG3_OUT), - PINMUX_DATA(PTG2_DATA, PTG2_OUT), - PINMUX_DATA(PTG1_DATA, PTG1_OUT), - PINMUX_DATA(PTG0_DATA, PTG0_OUT), - - /* PTH GPIO */ - PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT), - PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT), - PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT), - PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT), - PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT), - PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT), - PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT), - PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT), - - /* PTJ GPIO */ - PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), - PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), - PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT), - PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT), - PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT), - PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT), - - /* PTK GPIO */ - PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT), - PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT), - PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT), - PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT), - PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT), - PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT), - PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT), - PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), - - /* PTL GPIO */ - PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT), - PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), - PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), - PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), - PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT), - PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT), - PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT), - PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT), - - /* PTM GPIO */ - PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT), - PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT), - PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT), - PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT), - PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT), - PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT), - PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT), - PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), - - /* PTN GPIO */ - PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT), - PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT), - PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT), - PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT), - PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT), - PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT), - PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT), - PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT), - - /* PTQ GPIO */ - PINMUX_DATA(PTQ3_DATA, PTQ3_IN), - PINMUX_DATA(PTQ2_DATA, PTQ2_IN), - PINMUX_DATA(PTQ1_DATA, PTQ1_IN), - PINMUX_DATA(PTQ0_DATA, PTQ0_IN), - - /* PTR GPIO */ - PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT), - PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT), - PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT), - PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT), - PINMUX_DATA(PTR3_DATA, PTR3_IN), - PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), - PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT), - PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT), - - /* PTS GPIO */ - PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT), - PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT), - PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT), - PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT), - PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT), - PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT), - PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT), - PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), - - /* PTT GPIO */ - PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT), - PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), - PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), - PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT), - PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT), - PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT), - - /* PTU GPIO */ - PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT), - PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT), - PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT), - PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT), - PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT), - PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT), - - /* PTV GPIO */ - PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT), - PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT), - PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT), - PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT), - PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT), - PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT), - PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT), - PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT), - - /* PTW GPIO */ - PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT), - PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT), - PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT), - PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT), - PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT), - PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT), - PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT), - PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT), - - /* PTX GPIO */ - PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT), - PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT), - PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT), - PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT), - PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT), - PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT), - PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT), - PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT), - - /* PTY GPIO */ - PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT), - PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT), - PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT), - PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT), - PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT), - PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT), - PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT), - PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT), - - /* PTZ GPIO */ - PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT), - PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT), - PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT), - PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT), - PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT), - PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT), - PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT), - PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT), - - /* PTA FN */ - PINMUX_DATA(D23_MARK, PSA15_PSA14_FN1, PTA7_FN), - PINMUX_DATA(KEYOUT2_MARK, PSA15_PSA14_FN2, PTA7_FN), - PINMUX_DATA(D22_MARK, PSA15_PSA14_FN1, PTA6_FN), - PINMUX_DATA(KEYOUT1_MARK, PSA15_PSA14_FN2, PTA6_FN), - PINMUX_DATA(D21_MARK, PSA15_PSA14_FN1, PTA5_FN), - PINMUX_DATA(KEYOUT0_MARK, PSA15_PSA14_FN2, PTA5_FN), - PINMUX_DATA(D20_MARK, PSA15_PSA14_FN1, PTA4_FN), - PINMUX_DATA(KEYIN4_MARK, PSA15_PSA14_FN2, PTA4_FN), - PINMUX_DATA(D19_MARK, PSA15_PSA14_FN1, PTA3_FN), - PINMUX_DATA(KEYIN3_MARK, PSA15_PSA14_FN2, PTA3_FN), - PINMUX_DATA(D18_MARK, PSA15_PSA14_FN1, PTA2_FN), - PINMUX_DATA(KEYIN2_MARK, PSA15_PSA14_FN2, PTA2_FN), - PINMUX_DATA(D17_MARK, PSA15_PSA14_FN1, PTA1_FN), - PINMUX_DATA(KEYIN1_MARK, PSA15_PSA14_FN2, PTA1_FN), - PINMUX_DATA(D16_MARK, PSA15_PSA14_FN1, PTA0_FN), - PINMUX_DATA(KEYIN0_MARK, PSA15_PSA14_FN2, PTA0_FN), - - /* PTB FN */ - PINMUX_DATA(D31_MARK, PTB7_FN), - PINMUX_DATA(D30_MARK, PTB6_FN), - PINMUX_DATA(D29_MARK, PTB5_FN), - PINMUX_DATA(D28_MARK, PTB4_FN), - PINMUX_DATA(D27_MARK, PTB3_FN), - PINMUX_DATA(D26_MARK, PSA15_PSA14_FN1, PTB2_FN), - PINMUX_DATA(KEYOUT5_IN5_MARK, PSA15_PSA14_FN2, PTB2_FN), - PINMUX_DATA(D25_MARK, PSA15_PSA14_FN1, PTB1_FN), - PINMUX_DATA(KEYOUT4_IN6_MARK, PSA15_PSA14_FN2, PTB1_FN), - PINMUX_DATA(D24_MARK, PSA15_PSA14_FN1, PTB0_FN), - PINMUX_DATA(KEYOUT3_MARK, PSA15_PSA14_FN2, PTB0_FN), - - /* PTC FN */ - PINMUX_DATA(IDED15_MARK, PSA11_PSA10_FN1, PTC7_FN), - PINMUX_DATA(SDHI1CD_MARK, PSA11_PSA10_FN2, PTC7_FN), - PINMUX_DATA(IDED14_MARK, PSA11_PSA10_FN1, PTC6_FN), - PINMUX_DATA(SDHI1WP_MARK, PSA11_PSA10_FN2, PTC6_FN), - PINMUX_DATA(IDED13_MARK, PSA11_PSA10_FN1, PTC5_FN), - PINMUX_DATA(SDHI1D3_MARK, PSA11_PSA10_FN2, PTC5_FN), - PINMUX_DATA(IDED12_MARK, PSA11_PSA10_FN1, PTC4_FN), - PINMUX_DATA(SDHI1D2_MARK, PSA11_PSA10_FN2, PTC4_FN), - PINMUX_DATA(IDED11_MARK, PSA11_PSA10_FN1, PTC3_FN), - PINMUX_DATA(SDHI1D1_MARK, PSA11_PSA10_FN2, PTC3_FN), - PINMUX_DATA(IDED10_MARK, PSA11_PSA10_FN1, PTC2_FN), - PINMUX_DATA(SDHI1D0_MARK, PSA11_PSA10_FN2, PTC2_FN), - PINMUX_DATA(IDED9_MARK, PSA11_PSA10_FN1, PTC1_FN), - PINMUX_DATA(SDHI1CMD_MARK, PSA11_PSA10_FN2, PTC1_FN), - PINMUX_DATA(IDED8_MARK, PSA11_PSA10_FN1, PTC0_FN), - PINMUX_DATA(SDHI1CLK_MARK, PSA11_PSA10_FN2, PTC0_FN), - - /* PTD FN */ - PINMUX_DATA(IDED7_MARK, PSA11_PSA10_FN1, PTD7_FN), - PINMUX_DATA(SDHI0CD_PTD_MARK, PSA11_PSA10_FN2, PTD7_FN), - PINMUX_DATA(IDED6_MARK, PSA11_PSA10_FN1, PTD6_FN), - PINMUX_DATA(SDHI0WP_PTD_MARK, PSA11_PSA10_FN2, PTD6_FN), - PINMUX_DATA(IDED5_MARK, PSA11_PSA10_FN1, PTD5_FN), - PINMUX_DATA(SDHI0D3_PTD_MARK, PSA11_PSA10_FN2, PTD5_FN), - PINMUX_DATA(IDED4_MARK, PSA11_PSA10_FN1, PTD4_FN), - PINMUX_DATA(SDHI0D2_PTD_MARK, PSA11_PSA10_FN2, PTD4_FN), - PINMUX_DATA(IDED3_MARK, PSA11_PSA10_FN1, PTD3_FN), - PINMUX_DATA(SDHI0D1_PTD_MARK, PSA11_PSA10_FN2, PTD3_FN), - PINMUX_DATA(IDED2_MARK, PSA11_PSA10_FN1, PTD2_FN), - PINMUX_DATA(SDHI0D0_PTD_MARK, PSA11_PSA10_FN2, PTD2_FN), - PINMUX_DATA(IDED1_MARK, PSA11_PSA10_FN1, PTD1_FN), - PINMUX_DATA(SDHI0CMD_PTD_MARK, PSA11_PSA10_FN2, PTD1_FN), - PINMUX_DATA(IDED0_MARK, PSA11_PSA10_FN1, PTD0_FN), - PINMUX_DATA(SDHI0CLK_PTD_MARK, PSA11_PSA10_FN2, PTD0_FN), - - /* PTE FN */ - PINMUX_DATA(DIRECTION_MARK, PSA11_PSA10_FN1, PTE5_FN), - PINMUX_DATA(SCIF5_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE5_FN), - PINMUX_DATA(EXBUF_ENB_MARK, PSA11_PSA10_FN1, PTE4_FN), - PINMUX_DATA(SCIF5_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE4_FN), - PINMUX_DATA(IDERST_MARK, PSA11_PSA10_FN1, PTE3_FN), - PINMUX_DATA(SCIF5_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE3_FN), - PINMUX_DATA(IODACK_MARK, PSA11_PSA10_FN1, PTE2_FN), - PINMUX_DATA(SCIF4_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE2_FN), - PINMUX_DATA(IODREQ_MARK, PSA11_PSA10_FN1, PTE1_FN), - PINMUX_DATA(SCIF4_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE1_FN), - PINMUX_DATA(IDEIORDY_MARK, PSA11_PSA10_FN1, PTE0_FN), - PINMUX_DATA(SCIF4_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE0_FN), - - /* PTF FN */ - PINMUX_DATA(IDEINT_MARK, PTF7_FN), - PINMUX_DATA(IDEIOWR_MARK, PSA5_PSA4_FN1, PTF6_FN), - PINMUX_DATA(MSIOF0_PTF_SS2_MARK, PSA5_PSA4_FN2, PTF6_FN), - PINMUX_DATA(MSIOF0_PTF_RSYNC_MARK, PSA5_PSA4_FN3, PTF6_FN), - PINMUX_DATA(IDEIORD_MARK, PSA5_PSA4_FN1, PTF5_FN), - PINMUX_DATA(MSIOF0_PTF_SS1_MARK, PSA5_PSA4_FN2, PTF5_FN), - PINMUX_DATA(MSIOF0_PTF_RSCK_MARK, PSA5_PSA4_FN3, PTF5_FN), - PINMUX_DATA(IDECS1_MARK, PSA11_PSA10_FN1, PTF4_FN), - PINMUX_DATA(MSIOF0_PTF_TSYNC_MARK, PSA11_PSA10_FN2, PTF4_FN), - PINMUX_DATA(IDECS0_MARK, PSA11_PSA10_FN1, PTF3_FN), - PINMUX_DATA(MSIOF0_PTF_TSCK_MARK, PSA11_PSA10_FN2, PTF3_FN), - PINMUX_DATA(IDEA2_MARK, PSA11_PSA10_FN1, PTF2_FN), - PINMUX_DATA(MSIOF0_PTF_RXD_MARK, PSA11_PSA10_FN2, PTF2_FN), - PINMUX_DATA(IDEA1_MARK, PSA11_PSA10_FN1, PTF1_FN), - PINMUX_DATA(MSIOF0_PTF_TXD_MARK, PSA11_PSA10_FN2, PTF1_FN), - PINMUX_DATA(IDEA0_MARK, PSA11_PSA10_FN1, PTF0_FN), - PINMUX_DATA(MSIOF0_PTF_MCK_MARK, PSA11_PSA10_FN2, PTF0_FN), - - /* PTG FN */ - PINMUX_DATA(AUDCK_MARK, PTG5_FN), - PINMUX_DATA(AUDSYNC_MARK, PTG4_FN), - PINMUX_DATA(AUDATA3_MARK, PSA3_PSA2_FN1, PTG3_FN), - PINMUX_DATA(TPUTO3_MARK, PSA3_PSA2_FN2, PTG3_FN), - PINMUX_DATA(AUDATA2_MARK, PSA3_PSA2_FN1, PTG2_FN), - PINMUX_DATA(TPUTO2_MARK, PSA3_PSA2_FN2, PTG2_FN), - PINMUX_DATA(AUDATA1_MARK, PSA3_PSA2_FN1, PTG1_FN), - PINMUX_DATA(TPUTO1_MARK, PSA3_PSA2_FN2, PTG1_FN), - PINMUX_DATA(AUDATA0_MARK, PSA3_PSA2_FN1, PTG0_FN), - PINMUX_DATA(TPUTO0_MARK, PSA3_PSA2_FN2, PTG0_FN), - - /* PTG FN */ - PINMUX_DATA(LCDVCPWC_MARK, PTH7_FN), - PINMUX_DATA(LCDRD_MARK, PSB15_PSB14_FN1, PTH6_FN), - PINMUX_DATA(DV_CLKI_MARK, PSB15_PSB14_FN2, PTH6_FN), - PINMUX_DATA(LCDVSYN_MARK, PSB15_PSB14_FN1, PTH5_FN), - PINMUX_DATA(DV_CLK_MARK, PSB15_PSB14_FN2, PTH5_FN), - PINMUX_DATA(LCDDISP_MARK, PSB13_PSB12_LCDC_RGB, PTH4_FN), - PINMUX_DATA(LCDRS_MARK, PSB13_PSB12_LCDC_SYS, PTH4_FN), - PINMUX_DATA(LCDHSYN_MARK, PSB13_PSB12_LCDC_RGB, PTH3_FN), - PINMUX_DATA(LCDCS_MARK, PSB13_PSB12_LCDC_SYS, PTH3_FN), - PINMUX_DATA(LCDDON_MARK, PTH2_FN), - PINMUX_DATA(LCDDCK_MARK, PSB13_PSB12_LCDC_RGB, PTH1_FN), - PINMUX_DATA(LCDWR_MARK, PSB13_PSB12_LCDC_SYS, PTH1_FN), - PINMUX_DATA(LCDVEPWC_MARK, PTH0_FN), - - /* PTJ FN */ - PINMUX_DATA(STATUS0_MARK, PTJ7_FN), - PINMUX_DATA(PDSTATUS_MARK, PTJ5_FN), - PINMUX_DATA(A25_MARK, PTJ3_FN), - PINMUX_DATA(A24_MARK, PTJ2_FN), - PINMUX_DATA(A23_MARK, PTJ1_FN), - PINMUX_DATA(A22_MARK, PTJ0_FN), - - /* PTK FN */ - PINMUX_DATA(SIUAFCK_MARK, PTK7_FN), - PINMUX_DATA(SIUAILR_MARK, PSB9_PSB8_FN1, PTK6_FN), - PINMUX_DATA(MSIOF1_SS2_MARK, PSB9_PSB8_FN2, PTK6_FN), - PINMUX_DATA(MSIOF1_RSYNC_MARK, PSB9_PSB8_FN3, PTK6_FN), - PINMUX_DATA(SIUAIBT_MARK, PSB9_PSB8_FN1, PTK5_FN), - PINMUX_DATA(MSIOF1_SS1_MARK, PSB9_PSB8_FN2, PTK5_FN), - PINMUX_DATA(MSIOF1_RSCK_MARK, PSB9_PSB8_FN3, PTK5_FN), - PINMUX_DATA(SIUAISLD_MARK, PSB7_PSB6_FN1, PTK4_FN), - PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK4_FN), - PINMUX_DATA(SIUAOLR_MARK, PSB7_PSB6_FN1, PTK3_FN), - PINMUX_DATA(MSIOF1_TSYNC_MARK, PSB7_PSB6_FN2, PTK3_FN), - PINMUX_DATA(SIUAOBT_MARK, PSB7_PSB6_FN1, PTK2_FN), - PINMUX_DATA(MSIOF1_TSCK_MARK, PSB7_PSB6_FN2, PTK2_FN), - PINMUX_DATA(SIUAOSLD_MARK, PSB7_PSB6_FN1, PTK1_FN), - PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK1_FN), - PINMUX_DATA(SIUAMCK_MARK, PSB7_PSB6_FN1, PTK0_FN), - PINMUX_DATA(MSIOF1_MCK_MARK, PSB7_PSB6_FN2, PTK0_FN), - - /* PTL FN */ - PINMUX_DATA(LCDD15_MARK, PSB5_PSB4_FN1, PTL7_FN), - PINMUX_DATA(DV_D15_MARK, PSB5_PSB4_FN2, PTL7_FN), - PINMUX_DATA(LCDD14_MARK, PSB5_PSB4_FN1, PTL6_FN), - PINMUX_DATA(DV_D14_MARK, PSB5_PSB4_FN2, PTL6_FN), - PINMUX_DATA(LCDD13_MARK, PSB5_PSB4_FN1, PTL5_FN), - PINMUX_DATA(DV_D13_MARK, PSB5_PSB4_FN2, PTL5_FN), - PINMUX_DATA(LCDD12_MARK, PSB5_PSB4_FN1, PTL4_FN), - PINMUX_DATA(DV_D12_MARK, PSB5_PSB4_FN2, PTL4_FN), - PINMUX_DATA(LCDD11_MARK, PSB5_PSB4_FN1, PTL3_FN), - PINMUX_DATA(DV_D11_MARK, PSB5_PSB4_FN2, PTL3_FN), - PINMUX_DATA(LCDD10_MARK, PSB5_PSB4_FN1, PTL2_FN), - PINMUX_DATA(DV_D10_MARK, PSB5_PSB4_FN2, PTL2_FN), - PINMUX_DATA(LCDD9_MARK, PSB5_PSB4_FN1, PTL1_FN), - PINMUX_DATA(DV_D9_MARK, PSB5_PSB4_FN2, PTL1_FN), - PINMUX_DATA(LCDD8_MARK, PSB5_PSB4_FN1, PTL0_FN), - PINMUX_DATA(DV_D8_MARK, PSB5_PSB4_FN2, PTL0_FN), - - /* PTM FN */ - PINMUX_DATA(LCDD7_MARK, PSB5_PSB4_FN1, PTM7_FN), - PINMUX_DATA(DV_D7_MARK, PSB5_PSB4_FN2, PTM7_FN), - PINMUX_DATA(LCDD6_MARK, PSB5_PSB4_FN1, PTM6_FN), - PINMUX_DATA(DV_D6_MARK, PSB5_PSB4_FN2, PTM6_FN), - PINMUX_DATA(LCDD5_MARK, PSB5_PSB4_FN1, PTM5_FN), - PINMUX_DATA(DV_D5_MARK, PSB5_PSB4_FN2, PTM5_FN), - PINMUX_DATA(LCDD4_MARK, PSB5_PSB4_FN1, PTM4_FN), - PINMUX_DATA(DV_D4_MARK, PSB5_PSB4_FN2, PTM4_FN), - PINMUX_DATA(LCDD3_MARK, PSB5_PSB4_FN1, PTM3_FN), - PINMUX_DATA(DV_D3_MARK, PSB5_PSB4_FN2, PTM3_FN), - PINMUX_DATA(LCDD2_MARK, PSB5_PSB4_FN1, PTM2_FN), - PINMUX_DATA(DV_D2_MARK, PSB5_PSB4_FN2, PTM2_FN), - PINMUX_DATA(LCDD1_MARK, PSB5_PSB4_FN1, PTM1_FN), - PINMUX_DATA(DV_D1_MARK, PSB5_PSB4_FN2, PTM1_FN), - PINMUX_DATA(LCDD0_MARK, PSB5_PSB4_FN1, PTM0_FN), - PINMUX_DATA(DV_D0_MARK, PSB5_PSB4_FN2, PTM0_FN), - - /* PTN FN */ - PINMUX_DATA(LCDD23_MARK, PSB3_PSB2_FN1, PTN7_FN), - PINMUX_DATA(SCIF5_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN7_FN), - PINMUX_DATA(LCDD22_MARK, PSB3_PSB2_FN1, PTN6_FN), - PINMUX_DATA(SCIF5_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN6_FN), - PINMUX_DATA(LCDD21_MARK, PSB3_PSB2_FN1, PTN5_FN), - PINMUX_DATA(SCIF5_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN5_FN), - PINMUX_DATA(LCDD20_MARK, PSB3_PSB2_FN1, PTN4_FN), - PINMUX_DATA(SCIF4_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN4_FN), - PINMUX_DATA(LCDD19_MARK, PSB3_PSB2_FN1, PTN3_FN), - PINMUX_DATA(SCIF4_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN3_FN), - PINMUX_DATA(LCDD18_MARK, PSB3_PSB2_FN1, PTN2_FN), - PINMUX_DATA(SCIF4_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN2_FN), - PINMUX_DATA(LCDD17_MARK, PSB5_PSB4_FN1, PTN1_FN), - PINMUX_DATA(DV_VSYNC_MARK, PSB5_PSB4_FN2, PTN1_FN), - PINMUX_DATA(LCDD16_MARK, PSB5_PSB4_FN1, PTN0_FN), - PINMUX_DATA(DV_HSYNC_MARK, PSB5_PSB4_FN2, PTN0_FN), - - /* PTQ FN */ - PINMUX_DATA(AN3_MARK, PTQ3_FN), - PINMUX_DATA(AN2_MARK, PTQ2_FN), - PINMUX_DATA(AN1_MARK, PTQ1_FN), - PINMUX_DATA(AN0_MARK, PTQ0_FN), - - /* PTR FN */ - PINMUX_DATA(CS6B_CE1B_MARK, PTR7_FN), - PINMUX_DATA(CS6A_CE2B_MARK, PTR6_FN), - PINMUX_DATA(CS5B_CE1A_MARK, PTR5_FN), - PINMUX_DATA(CS5A_CE2A_MARK, PTR4_FN), - PINMUX_DATA(IOIS16_MARK, PSA13_PSA12_FN1, PTR3_FN), - PINMUX_DATA(LCDLCLK_PTR_MARK, PSA13_PSA12_FN2, PTR3_FN), - PINMUX_DATA(WAIT_MARK, PTR2_FN), - PINMUX_DATA(WE3_ICIOWR_MARK, PTR1_FN), - PINMUX_DATA(WE2_ICIORD_MARK, PTR0_FN), - - /* PTS FN */ - PINMUX_DATA(SCIF1_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS7_FN), - PINMUX_DATA(SDHI0CD_PTS_MARK, PSC15_PSC14_FN2, PTS7_FN), - PINMUX_DATA(SCIF1_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS6_FN), - PINMUX_DATA(SDHI0WP_PTS_MARK, PSC15_PSC14_FN2, PTS6_FN), - PINMUX_DATA(SCIF1_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS5_FN), - PINMUX_DATA(SDHI0D3_PTS_MARK, PSC15_PSC14_FN2, PTS5_FN), - PINMUX_DATA(SCIF3_PTS_CTS_MARK, PSC15_PSC14_FN1, PTS4_FN), - PINMUX_DATA(SDHI0D2_PTS_MARK, PSC15_PSC14_FN2, PTS4_FN), - PINMUX_DATA(SCIF3_PTS_RTS_MARK, PSC15_PSC14_FN1, PTS3_FN), - PINMUX_DATA(SDHI0D1_PTS_MARK, PSC15_PSC14_FN2, PTS3_FN), - PINMUX_DATA(SCIF3_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS2_FN), - PINMUX_DATA(SDHI0D0_PTS_MARK, PSC15_PSC14_FN2, PTS2_FN), - PINMUX_DATA(SCIF3_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS1_FN), - PINMUX_DATA(SDHI0CMD_PTS_MARK, PSC15_PSC14_FN2, PTS1_FN), - PINMUX_DATA(SCIF3_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS0_FN), - PINMUX_DATA(SDHI0CLK_PTS_MARK, PSC15_PSC14_FN2, PTS0_FN), - - /* PTT FN */ - PINMUX_DATA(SCIF0_PTT_SCK_MARK, PSC13_PSC12_FN1, PTT5_FN), - PINMUX_DATA(MSIOF0_PTT_TSCK_MARK, PSC13_PSC12_FN2, PTT5_FN), - PINMUX_DATA(SCIF0_PTT_RXD_MARK, PSC13_PSC12_FN1, PTT4_FN), - PINMUX_DATA(MSIOF0_PTT_RXD_MARK, PSC13_PSC12_FN2, PTT4_FN), - PINMUX_DATA(SCIF0_PTT_TXD_MARK, PSC13_PSC12_FN1, PTT3_FN), - PINMUX_DATA(MSIOF0_PTT_TXD_MARK, PSC13_PSC12_FN2, PTT3_FN), - PINMUX_DATA(SCIF2_PTT_SCK_MARK, PSC11_PSC10_FN1, PTT2_FN), - PINMUX_DATA(MSIOF0_PTT_TSYNC_MARK, PSC11_PSC10_FN2, PTT2_FN), - PINMUX_DATA(SCIF2_PTT_RXD_MARK, PSC11_PSC10_FN1, PTT1_FN), - PINMUX_DATA(MSIOF0_PTT_SS1_MARK, PSC11_PSC10_FN2, PTT1_FN), - PINMUX_DATA(MSIOF0_PTT_RSCK_MARK, PSC11_PSC10_FN3, PTT1_FN), - PINMUX_DATA(SCIF2_PTT_TXD_MARK, PSC11_PSC10_FN1, PTT0_FN), - PINMUX_DATA(MSIOF0_PTT_SS2_MARK, PSC11_PSC10_FN2, PTT0_FN), - PINMUX_DATA(MSIOF0_PTT_RSYNC_MARK, PSC11_PSC10_FN3, PTT0_FN), - - /* PTU FN */ - PINMUX_DATA(FCDE_MARK, PSC9_PSC8_FN1, PTU5_FN), - PINMUX_DATA(SCIF0_PTU_SCK_MARK, PSC9_PSC8_FN2, PTU5_FN), - PINMUX_DATA(FSC_MARK, PSC9_PSC8_FN1, PTU4_FN), - PINMUX_DATA(SCIF0_PTU_RXD_MARK, PSC9_PSC8_FN2, PTU4_FN), - PINMUX_DATA(FWE_MARK, PSC9_PSC8_FN1, PTU3_FN), - PINMUX_DATA(SCIF0_PTU_TXD_MARK, PSC9_PSC8_FN2, PTU3_FN), - PINMUX_DATA(FOE_MARK, PSC7_PSC6_FN1, PTU2_FN), - PINMUX_DATA(SCIF2_PTU_SCK_MARK, PSC7_PSC6_FN2, PTU2_FN), - PINMUX_DATA(VIO_VD2_MARK, PSC7_PSC6_FN3, PTU2_FN), - PINMUX_DATA(FRB_MARK, PSC7_PSC6_FN1, PTU1_FN), - PINMUX_DATA(SCIF2_PTU_RXD_MARK, PSC7_PSC6_FN2, PTU1_FN), - PINMUX_DATA(VIO_CLK2_MARK, PSC7_PSC6_FN3, PTU1_FN), - PINMUX_DATA(FCE_MARK, PSC7_PSC6_FN1, PTU0_FN), - PINMUX_DATA(SCIF2_PTU_TXD_MARK, PSC7_PSC6_FN2, PTU0_FN), - PINMUX_DATA(VIO_HD2_MARK, PSC7_PSC6_FN3, PTU0_FN), - - /* PTV FN */ - PINMUX_DATA(NAF7_MARK, PSC7_PSC6_FN1, PTV7_FN), - PINMUX_DATA(SCIF1_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV7_FN), - PINMUX_DATA(VIO_D15_MARK, PSC7_PSC6_FN3, PTV7_FN), - PINMUX_DATA(NAF6_MARK, PSC7_PSC6_FN1, PTV6_FN), - PINMUX_DATA(SCIF1_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV6_FN), - PINMUX_DATA(VIO_D14_MARK, PSC7_PSC6_FN3, PTV6_FN), - PINMUX_DATA(NAF5_MARK, PSC7_PSC6_FN1, PTV5_FN), - PINMUX_DATA(SCIF1_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV5_FN), - PINMUX_DATA(VIO_D13_MARK, PSC7_PSC6_FN3, PTV5_FN), - PINMUX_DATA(NAF4_MARK, PSC7_PSC6_FN1, PTV4_FN), - PINMUX_DATA(SCIF3_PTV_CTS_MARK, PSC7_PSC6_FN2, PTV4_FN), - PINMUX_DATA(VIO_D12_MARK, PSC7_PSC6_FN3, PTV4_FN), - PINMUX_DATA(NAF3_MARK, PSC7_PSC6_FN1, PTV3_FN), - PINMUX_DATA(SCIF3_PTV_RTS_MARK, PSC7_PSC6_FN2, PTV3_FN), - PINMUX_DATA(VIO_D11_MARK, PSC7_PSC6_FN3, PTV3_FN), - PINMUX_DATA(NAF2_MARK, PSC7_PSC6_FN1, PTV2_FN), - PINMUX_DATA(SCIF3_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV2_FN), - PINMUX_DATA(VIO_D10_MARK, PSC7_PSC6_FN3, PTV2_FN), - PINMUX_DATA(NAF1_MARK, PSC7_PSC6_FN1, PTV1_FN), - PINMUX_DATA(SCIF3_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV1_FN), - PINMUX_DATA(VIO_D9_MARK, PSC7_PSC6_FN3, PTV1_FN), - PINMUX_DATA(NAF0_MARK, PSC7_PSC6_FN1, PTV0_FN), - PINMUX_DATA(SCIF3_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV0_FN), - PINMUX_DATA(VIO_D8_MARK, PSC7_PSC6_FN3, PTV0_FN), - - /* PTW FN */ - PINMUX_DATA(IRQ7_MARK, PTW7_FN), - PINMUX_DATA(IRQ6_MARK, PTW6_FN), - PINMUX_DATA(IRQ5_MARK, PTW5_FN), - PINMUX_DATA(IRQ4_MARK, PSD15_PSD14_FN1, PTW4_FN), - PINMUX_DATA(LCDLCLK_PTW_MARK, PSD15_PSD14_FN2, PTW4_FN), - PINMUX_DATA(IRQ3_MARK, PSD13_PSD12_FN1, PTW3_FN), - PINMUX_DATA(ADTRG_MARK, PSD13_PSD12_FN2, PTW3_FN), - PINMUX_DATA(IRQ2_MARK, PSD11_PSD10_FN1, PTW2_FN), - PINMUX_DATA(BS_MARK, PSD11_PSD10_FN2, PTW2_FN), - PINMUX_DATA(VIO_CKO_MARK, PSD11_PSD10_FN3, PTW2_FN), - PINMUX_DATA(IRQ1_MARK, PSD9_PSD8_FN1, PTW1_FN), - PINMUX_DATA(SIUAISPD_MARK, PSD9_PSD8_FN2, PTW1_FN), - PINMUX_DATA(IRQ0_MARK, PSD7_PSD6_FN1, PTW0_FN), - PINMUX_DATA(SIUAOSPD_MARK, PSD7_PSD6_FN2, PTW0_FN), - - /* PTX FN */ - PINMUX_DATA(DACK1_MARK, PTX7_FN), - PINMUX_DATA(DREQ1_MARK, PSD3_PSD2_FN1, PTX6_FN), - PINMUX_DATA(MSIOF0_PTX_MCK_MARK, PSD3_PSD2_FN2, PTX6_FN), - PINMUX_DATA(DACK1_MARK, PTX5_FN), - PINMUX_DATA(IRDA_OUT_MARK, PSD5_PSD4_FN2, PTX5_FN), - PINMUX_DATA(DREQ1_MARK, PTX4_FN), - PINMUX_DATA(IRDA_IN_MARK, PSD5_PSD4_FN2, PTX4_FN), - PINMUX_DATA(TS0_SDAT_MARK, PTX3_FN), - PINMUX_DATA(TS0_SCK_MARK, PTX2_FN), - PINMUX_DATA(TS0_SDEN_MARK, PTX1_FN), - PINMUX_DATA(TS0_SPSYNC_MARK, PTX0_FN), - - /* PTY FN */ - PINMUX_DATA(VIO_D7_MARK, PTY7_FN), - PINMUX_DATA(VIO_D6_MARK, PTY6_FN), - PINMUX_DATA(VIO_D5_MARK, PTY5_FN), - PINMUX_DATA(VIO_D4_MARK, PTY4_FN), - PINMUX_DATA(VIO_D3_MARK, PTY3_FN), - PINMUX_DATA(VIO_D2_MARK, PTY2_FN), - PINMUX_DATA(VIO_D1_MARK, PTY1_FN), - PINMUX_DATA(VIO_D0_MARK, PTY0_FN), - - /* PTZ FN */ - PINMUX_DATA(SIUBOBT_MARK, PTZ7_FN), - PINMUX_DATA(SIUBOLR_MARK, PTZ6_FN), - PINMUX_DATA(SIUBOSLD_MARK, PTZ5_FN), - PINMUX_DATA(SIUBMCK_MARK, PTZ4_FN), - PINMUX_DATA(VIO_FLD_MARK, PSD1_PSD0_FN1, PTZ3_FN), - PINMUX_DATA(SIUBFCK_MARK, PSD1_PSD0_FN2, PTZ3_FN), - PINMUX_DATA(VIO_HD1_MARK, PSD1_PSD0_FN1, PTZ2_FN), - PINMUX_DATA(SIUBILR_MARK, PSD1_PSD0_FN2, PTZ2_FN), - PINMUX_DATA(VIO_VD1_MARK, PSD1_PSD0_FN1, PTZ1_FN), - PINMUX_DATA(SIUBIBT_MARK, PSD1_PSD0_FN2, PTZ1_FN), - PINMUX_DATA(VIO_CLK1_MARK, PSD1_PSD0_FN1, PTZ0_FN), - PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - /* PTA */ - PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), - PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), - PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), - PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), - PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), - PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), - PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), - PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), - - /* PTB */ - PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), - PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), - PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), - PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), - PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), - PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), - PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), - PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), - - /* PTC */ - PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), - PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), - PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), - PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), - PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), - PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), - PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), - PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), - - /* PTD */ - PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), - PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), - PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), - PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), - PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), - PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), - PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), - PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), - - /* PTE */ - PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), - PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), - PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), - PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), - PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), - PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), - - /* PTF */ - PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), - PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), - PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), - PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), - PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), - PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), - PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), - PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), - - /* PTG */ - PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), - PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), - PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), - PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), - PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), - PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), - - /* PTH */ - PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), - PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), - PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), - PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), - PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), - PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), - PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), - PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), - - /* PTJ */ - PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), - PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), - PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), - PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), - PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), - PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), - - /* PTK */ - PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), - PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), - PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), - PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), - PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), - PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), - PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), - PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), - - /* PTL */ - PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), - PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), - PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), - PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), - PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), - PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), - PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), - PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), - - /* PTM */ - PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), - PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), - PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), - PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), - PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), - PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), - PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), - PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), - - /* PTN */ - PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), - PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), - PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), - PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), - PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), - PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), - PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), - PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), - - /* PTQ */ - PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), - PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), - PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), - PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), - - /* PTR */ - PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), - PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), - PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), - PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), - PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), - PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), - PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), - PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), - - /* PTS */ - PINMUX_GPIO(GPIO_PTS7, PTS7_DATA), - PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), - PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), - PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), - PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), - PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), - PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), - PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), - - /* PTT */ - PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), - PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), - PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), - PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), - PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), - PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), - - /* PTU */ - PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), - PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), - PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), - PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), - PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), - PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), - - /* PTV */ - PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), - PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), - PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), - PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), - PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), - PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), - PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), - PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), - - /* PTW */ - PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), - PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), - PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), - PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), - PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), - PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), - PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), - PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), - - /* PTX */ - PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), - PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), - PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), - PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), - PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), - PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), - PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), - PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), - - /* PTY */ - PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), - PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), - PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), - PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), - PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), - PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), - PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), - PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), - - /* PTZ */ - PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), - PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), - PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), - PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), - PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), - PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), - PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), - PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), - - /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK), - - /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK), - - /* SCIF2 */ - PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK), - - /* SCIF3 */ - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK), - - /* SCIF4 */ - PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK), - - /* SCIF5 */ - PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK), - - /* CEU */ - PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), - - /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), - PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), - PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), - PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), - PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), - PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), - PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), - PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), - PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), - PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), - PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), - PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), - PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), - PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), - PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), - PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), - PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), - PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), - PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), - PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), - PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), - PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), - PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), - PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK), - /* Main LCD */ - PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), - /* Main LCD - RGB Mode */ - PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), - PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), - /* Main LCD - SYS Mode */ - PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), - PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), - PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), - - /* IRQ */ - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), - - /* AUD */ - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), - - /* SDHI0 (PTD) */ - PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK), - - /* SDHI0 (PTS) */ - PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK), - - /* SDHI1 */ - PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), - - /* SIUA */ - PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK), - PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK), - PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK), - PINMUX_GPIO(GPIO_FN_SIUOSPD, SIUAOSPD_MARK), - - /* SIUB */ - PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK), - PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK), - - /* IRDA */ - PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), - PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), - - /* VOU */ - PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), - PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), - PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), - PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), - PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), - PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), - PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), - PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), - PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), - PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), - PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), - PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), - PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), - PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), - PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), - PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), - - /* KEYSC */ - PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), - - /* MSIOF0 (PTF) */ - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK), - - /* MSIOF0 (PTT+PTX) */ - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK), - - /* MSIOF1 */ - PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), - - /* TSIF */ - PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK), - PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK), - PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK), - - /* FLCTL */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), - PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), - PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), - PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), - PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), - PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), - PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), - PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), - PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), - PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), - PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - - /* DMAC */ - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - - /* ADC */ - PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), - PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), - PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), - PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), - - /* CPG */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), - - /* TPU */ - PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), - - /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), - PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), - PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), - - /* ATAPI */ - PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), - PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), - PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), - PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), - PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), - PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), - PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), - PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), - PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), - PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), - PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), - PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), - PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), - PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), - PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), - PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), - PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), - PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), - PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), - PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), - PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), - PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), - PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), - PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), - PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), - PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), - PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), - PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), - }; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { - PTA7_FN, PTA7_OUT, 0, PTA7_IN, - PTA6_FN, PTA6_OUT, 0, PTA6_IN, - PTA5_FN, PTA5_OUT, 0, PTA5_IN, - PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, - PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, - PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, - PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, - PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } - }, - { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { - PTB7_FN, PTB7_OUT, 0, PTB7_IN, - PTB6_FN, PTB6_OUT, 0, PTB6_IN, - PTB5_FN, PTB5_OUT, 0, PTB5_IN, - PTB4_FN, PTB4_OUT, 0, PTB4_IN, - PTB3_FN, PTB3_OUT, 0, PTB3_IN, - PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, - PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, - PTB0_FN, PTB0_OUT, 0, PTB0_IN } - }, - { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { - PTC7_FN, PTC7_OUT, 0, PTC7_IN, - PTC6_FN, PTC6_OUT, 0, PTC6_IN, - PTC5_FN, PTC5_OUT, 0, PTC5_IN, - PTC4_FN, PTC4_OUT, 0, PTC4_IN, - PTC3_FN, PTC3_OUT, 0, PTC3_IN, - PTC2_FN, PTC2_OUT, 0, PTC2_IN, - PTC1_FN, PTC1_OUT, 0, PTC1_IN, - PTC0_FN, PTC0_OUT, 0, PTC0_IN } - }, - { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { - PTD7_FN, PTD7_OUT, 0, PTD7_IN, - PTD6_FN, PTD6_OUT, 0, PTD6_IN, - PTD5_FN, PTD5_OUT, 0, PTD5_IN, - PTD4_FN, PTD4_OUT, 0, PTD4_IN, - PTD3_FN, PTD3_OUT, 0, PTD3_IN, - PTD2_FN, PTD2_OUT, 0, PTD2_IN, - PTD1_FN, PTD1_OUT, 0, PTD1_IN, - PTD0_FN, PTD0_OUT, 0, PTD0_IN } - }, - { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - PTE5_FN, PTE5_OUT, 0, PTE5_IN, - PTE4_FN, PTE4_OUT, 0, PTE4_IN, - PTE3_FN, PTE3_OUT, 0, PTE3_IN, - PTE2_FN, PTE2_OUT, 0, PTE2_IN, - PTE1_FN, PTE1_OUT, 0, PTE1_IN, - PTE0_FN, PTE0_OUT, 0, PTE0_IN } - }, - { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { - PTF7_FN, PTF7_OUT, 0, PTF7_IN, - PTF6_FN, PTF6_OUT, 0, PTF6_IN, - PTF5_FN, PTF5_OUT, 0, PTF5_IN, - PTF4_FN, PTF4_OUT, 0, PTF4_IN, - PTF3_FN, PTF3_OUT, 0, PTF3_IN, - PTF2_FN, PTF2_OUT, 0, PTF2_IN, - PTF1_FN, PTF1_OUT, 0, PTF1_IN, - PTF0_FN, PTF0_OUT, 0, PTF0_IN } - }, - { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - PTG5_FN, PTG5_OUT, 0, 0, - PTG4_FN, PTG4_OUT, 0, 0, - PTG3_FN, PTG3_OUT, 0, 0, - PTG2_FN, PTG2_OUT, 0, 0, - PTG1_FN, PTG1_OUT, 0, 0, - PTG0_FN, PTG0_OUT, 0, 0 } - }, - { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { - PTH7_FN, PTH7_OUT, 0, PTH7_IN, - PTH6_FN, PTH6_OUT, 0, PTH6_IN, - PTH5_FN, PTH5_OUT, 0, PTH5_IN, - PTH4_FN, PTH4_OUT, 0, PTH4_IN, - PTH3_FN, PTH3_OUT, 0, PTH3_IN, - PTH2_FN, PTH2_OUT, 0, PTH2_IN, - PTH1_FN, PTH1_OUT, 0, PTH1_IN, - PTH0_FN, PTH0_OUT, 0, PTH0_IN } - }, - { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { - PTJ7_FN, PTJ7_OUT, 0, 0, - 0, 0, 0, 0, - PTJ5_FN, PTJ5_OUT, 0, 0, - 0, 0, 0, 0, - PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN, - PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN, - PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN, - PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN } - }, - { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { - PTK7_FN, PTK7_OUT, 0, PTK7_IN, - PTK6_FN, PTK6_OUT, 0, PTK6_IN, - PTK5_FN, PTK5_OUT, 0, PTK5_IN, - PTK4_FN, PTK4_OUT, 0, PTK4_IN, - PTK3_FN, PTK3_OUT, 0, PTK3_IN, - PTK2_FN, PTK2_OUT, 0, PTK2_IN, - PTK1_FN, PTK1_OUT, 0, PTK1_IN, - PTK0_FN, PTK0_OUT, 0, PTK0_IN } +static struct resource sh7723_pfc_resources[] = { + [0] = { + .start = 0xa4050100, + .end = 0xa405016f, + .flags = IORESOURCE_MEM, }, - { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { - PTL7_FN, PTL7_OUT, 0, PTL7_IN, - PTL6_FN, PTL6_OUT, 0, PTL6_IN, - PTL5_FN, PTL5_OUT, 0, PTL5_IN, - PTL4_FN, PTL4_OUT, 0, PTL4_IN, - PTL3_FN, PTL3_OUT, 0, PTL3_IN, - PTL2_FN, PTL2_OUT, 0, PTL2_IN, - PTL1_FN, PTL1_OUT, 0, PTL1_IN, - PTL0_FN, PTL0_OUT, 0, PTL0_IN } - }, - { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { - PTM7_FN, PTM7_OUT, 0, PTM7_IN, - PTM6_FN, PTM6_OUT, 0, PTM6_IN, - PTM5_FN, PTM5_OUT, 0, PTM5_IN, - PTM4_FN, PTM4_OUT, 0, PTM4_IN, - PTM3_FN, PTM3_OUT, 0, PTM3_IN, - PTM2_FN, PTM2_OUT, 0, PTM2_IN, - PTM1_FN, PTM1_OUT, 0, PTM1_IN, - PTM0_FN, PTM0_OUT, 0, PTM0_IN } - }, - { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { - PTN7_FN, PTN7_OUT, 0, PTN7_IN, - PTN6_FN, PTN6_OUT, 0, PTN6_IN, - PTN5_FN, PTN5_OUT, 0, PTN5_IN, - PTN4_FN, PTN4_OUT, 0, PTN4_IN, - PTN3_FN, PTN3_OUT, 0, PTN3_IN, - PTN2_FN, PTN2_OUT, 0, PTN2_IN, - PTN1_FN, PTN1_OUT, 0, PTN1_IN, - PTN0_FN, PTN0_OUT, 0, PTN0_IN } - }, - { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - PTQ3_FN, 0, 0, PTQ3_IN, - PTQ2_FN, 0, 0, PTQ2_IN, - PTQ1_FN, 0, 0, PTQ1_IN, - PTQ0_FN, 0, 0, PTQ0_IN } - }, - { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { - PTR7_FN, PTR7_OUT, 0, PTR7_IN, - PTR6_FN, PTR6_OUT, 0, PTR6_IN, - PTR5_FN, PTR5_OUT, 0, PTR5_IN, - PTR4_FN, PTR4_OUT, 0, PTR4_IN, - PTR3_FN, 0, 0, PTR3_IN, - PTR2_FN, 0, PTR2_IN_PU, PTR2_IN, - PTR1_FN, PTR1_OUT, 0, PTR1_IN, - PTR0_FN, PTR0_OUT, 0, PTR0_IN } - }, - { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { - PTS7_FN, PTS7_OUT, 0, PTS7_IN, - PTS6_FN, PTS6_OUT, 0, PTS6_IN, - PTS5_FN, PTS5_OUT, 0, PTS5_IN, - PTS4_FN, PTS4_OUT, 0, PTS4_IN, - PTS3_FN, PTS3_OUT, 0, PTS3_IN, - PTS2_FN, PTS2_OUT, 0, PTS2_IN, - PTS1_FN, PTS1_OUT, 0, PTS1_IN, - PTS0_FN, PTS0_OUT, 0, PTS0_IN } - }, - { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - PTT5_FN, PTT5_OUT, 0, PTT5_IN, - PTT4_FN, PTT4_OUT, 0, PTT4_IN, - PTT3_FN, PTT3_OUT, 0, PTT3_IN, - PTT2_FN, PTT2_OUT, 0, PTT2_IN, - PTT1_FN, PTT1_OUT, 0, PTT1_IN, - PTT0_FN, PTT0_OUT, 0, PTT0_IN } - }, - { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - PTU5_FN, PTU5_OUT, 0, PTU5_IN, - PTU4_FN, PTU4_OUT, 0, PTU4_IN, - PTU3_FN, PTU3_OUT, 0, PTU3_IN, - PTU2_FN, PTU2_OUT, 0, PTU2_IN, - PTU1_FN, PTU1_OUT, 0, PTU1_IN, - PTU0_FN, PTU0_OUT, 0, PTU0_IN } - }, - { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { - PTV7_FN, PTV7_OUT, 0, PTV7_IN, - PTV6_FN, PTV6_OUT, 0, PTV6_IN, - PTV5_FN, PTV5_OUT, 0, PTV5_IN, - PTV4_FN, PTV4_OUT, 0, PTV4_IN, - PTV3_FN, PTV3_OUT, 0, PTV3_IN, - PTV2_FN, PTV2_OUT, 0, PTV2_IN, - PTV1_FN, PTV1_OUT, 0, PTV1_IN, - PTV0_FN, PTV0_OUT, 0, PTV0_IN } - }, - { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { - PTW7_FN, PTW7_OUT, 0, PTW7_IN, - PTW6_FN, PTW6_OUT, 0, PTW6_IN, - PTW5_FN, PTW5_OUT, 0, PTW5_IN, - PTW4_FN, PTW4_OUT, 0, PTW4_IN, - PTW3_FN, PTW3_OUT, 0, PTW3_IN, - PTW2_FN, PTW2_OUT, 0, PTW2_IN, - PTW1_FN, PTW1_OUT, 0, PTW1_IN, - PTW0_FN, PTW0_OUT, 0, PTW0_IN } - }, - { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { - PTX7_FN, PTX7_OUT, 0, PTX7_IN, - PTX6_FN, PTX6_OUT, 0, PTX6_IN, - PTX5_FN, PTX5_OUT, 0, PTX5_IN, - PTX4_FN, PTX4_OUT, 0, PTX4_IN, - PTX3_FN, PTX3_OUT, 0, PTX3_IN, - PTX2_FN, PTX2_OUT, 0, PTX2_IN, - PTX1_FN, PTX1_OUT, 0, PTX1_IN, - PTX0_FN, PTX0_OUT, 0, PTX0_IN } - }, - { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { - PTY7_FN, PTY7_OUT, 0, PTY7_IN, - PTY6_FN, PTY6_OUT, 0, PTY6_IN, - PTY5_FN, PTY5_OUT, 0, PTY5_IN, - PTY4_FN, PTY4_OUT, 0, PTY4_IN, - PTY3_FN, PTY3_OUT, 0, PTY3_IN, - PTY2_FN, PTY2_OUT, 0, PTY2_IN, - PTY1_FN, PTY1_OUT, 0, PTY1_IN, - PTY0_FN, PTY0_OUT, 0, PTY0_IN } - }, - { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { - PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN, - PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN, - PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN, - PTZ4_FN, PTZ4_OUT, 0, PTZ4_IN, - PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN, - PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN, - PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN, - PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN } - }, - { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2) { - PSA15_PSA14_FN1, PSA15_PSA14_FN2, 0, 0, - PSA13_PSA12_FN1, PSA13_PSA12_FN2, 0, 0, - PSA11_PSA10_FN1, PSA11_PSA10_FN2, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, 0, - PSA3_PSA2_FN1, PSA3_PSA2_FN2, 0, 0, - 0, 0, 0, 0 } - }, - { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2) { - PSB15_PSB14_FN1, PSB15_PSB14_FN2, 0, 0, - PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, 0, 0, - 0, 0, 0, 0, - PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3, 0, - PSB7_PSB6_FN1, PSB7_PSB6_FN2, 0, 0, - PSB5_PSB4_FN1, PSB5_PSB4_FN2, 0, 0, - PSB3_PSB2_FN1, PSB3_PSB2_FN2, 0, 0, - 0, 0, 0, 0 } - }, - { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2) { - PSC15_PSC14_FN1, PSC15_PSC14_FN2, 0, 0, - PSC13_PSC12_FN1, PSC13_PSC12_FN2, 0, 0, - PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, 0, - PSC9_PSC8_FN1, PSC9_PSC8_FN2, 0, 0, - PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 } - }, - { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2) { - PSD15_PSD14_FN1, PSD15_PSD14_FN2, 0, 0, - PSD13_PSD12_FN1, PSD13_PSD12_FN2, 0, 0, - PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, 0, - PSD9_PSD8_FN1, PSD9_PSD8_FN2, 0, 0, - PSD7_PSD6_FN1, PSD7_PSD6_FN2, 0, 0, - PSD5_PSD4_FN1, PSD5_PSD4_FN2, 0, 0, - PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0, - PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 } - }, - {} -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { - PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, - PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } - }, - { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) { - PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, - PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } - }, - { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) { - PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, - PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA } - }, - { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { - PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, - PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } - }, - { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) { - 0, 0, PTE5_DATA, PTE4_DATA, - PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA } - }, - { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) { - PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, - PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } - }, - { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) { - 0, 0, PTG5_DATA, PTG4_DATA, - PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } - }, - { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) { - PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, - PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } - }, - { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) { - PTJ7_DATA, 0, PTJ5_DATA, 0, - PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } - }, - { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) { - PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, - PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } - }, - { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) { - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, - PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } - }, - { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) { - PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, - PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } - }, - { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) { - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, - PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } - }, - { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) { - 0, 0, 0, 0, - PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } - }, - { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) { - PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, - PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } - }, - { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) { - PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, - PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } - }, - { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) { - 0, 0, PTT5_DATA, PTT4_DATA, - PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } - }, - { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) { - 0, 0, PTU5_DATA, PTU4_DATA, - PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } - }, - { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) { - PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, - PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } - }, - { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) { - PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, - PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } - }, - { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) { - PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, - PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } - }, - { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) { - PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, - PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } - }, - { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) { - PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, - PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } - }, - { }, -}; - -static struct pinmux_info sh7723_pinmux_info = { - .name = "sh7723_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_IDEA0, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), }; static int __init plat_pinmux_setup(void) { - return register_pinmux(&sh7723_pinmux_info); + return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources, + ARRAY_SIZE(sh7723_pfc_resources)); } - arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c index 1af0f958637..63be4749e34 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c @@ -13,2218 +13,23 @@ * for more details. */ +#include <linux/bug.h> #include <linux/init.h> #include <linux/kernel.h> -#include <linux/gpio.h> -#include <cpu/sh7724.h> +#include <linux/ioport.h> +#include <cpu/pfc.h> -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, - PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA, - PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, - PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA, - PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, - PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA, - PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, - PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA, - PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, - PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA, - PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, - PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA, - PTG5_DATA, PTG4_DATA, - PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA, - PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, - PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, - PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, - PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA, - PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, - PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, - PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, - PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, - PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, - PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, - PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, - PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, - PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, - PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, - PTS6_DATA, PTS5_DATA, PTS4_DATA, - PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, - PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA, - PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, - PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, - PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, - PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, - PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA, - PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, - PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA, - PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, - PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA, - PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, - PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA, - PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, - PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA, - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN, - PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN, - PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN, - PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN, - PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN, - PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN, - PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, - PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN, - PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN, - PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN, - PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN, - PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN, - PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN, - PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN, - PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN, - PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN, - PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN, - PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, - PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, - PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN, - PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, - PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, - PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, - PTQ7_IN, PTQ6_IN, PTQ5_IN, PTQ4_IN, - PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN, - PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN, - PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN, - PTS6_IN, PTS5_IN, PTS4_IN, - PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN, - PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN, - PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN, - PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN, - PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, - PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN, - PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, - PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN, - PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN, - PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN, - PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN, - PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN, - PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN, - PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN, - PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, - PINMUX_INPUT_END, - - PINMUX_INPUT_PULLUP_BEGIN, - PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, - PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, - PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU, - PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU, - PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU, - PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU, - PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, - PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, - PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU, - PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, - PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU, - PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU, - PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, - PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, - PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, - PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU, - PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, - PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, - PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU, - PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, - PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU, - PTN7_IN_PU, PTN6_IN_PU, PTN5_IN_PU, PTN4_IN_PU, - PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU, - PTQ7_IN_PU, PTQ6_IN_PU, PTQ5_IN_PU, PTQ4_IN_PU, - PTQ3_IN_PU, PTQ2_IN_PU, PTQ1_IN_PU, PTQ0_IN_PU, - PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU, - PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU, - PTS6_IN_PU, PTS5_IN_PU, PTS4_IN_PU, - PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU, - PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU, - PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, - PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, - PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, - PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, - PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, - PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU, - PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU, - PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, - PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, - PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, - PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, - PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU, - PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU, - PINMUX_INPUT_PULLUP_END, - - PINMUX_OUTPUT_BEGIN, - PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, - PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, - PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, - PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT, - PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT, - PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT, - PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT, - PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT, - PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT, - PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT, - PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT, - PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT, - PTG5_OUT, PTG4_OUT, - PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT, - PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT, - PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, - PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, - PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT, - PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT, - PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT, - PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, - PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, - PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT, - PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, - PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, - PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, - PTQ7_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, - PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT, - PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT, - PTR1_OUT, PTR0_OUT, - PTS6_OUT, PTS5_OUT, PTS4_OUT, - PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT, - PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT, - PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT, - PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT, - PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT, - PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT, - PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT, - PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT, - PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT, - PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT, - PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT, - PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT, - PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT, - PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT, - PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT, - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN, - PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN, - PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN, - PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN, - PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN, - PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN, - PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN, - PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN, - PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN, - PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN, - PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN, - PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN, - PTG5_FN, PTG4_FN, - PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN, - PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN, - PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN, - PTJ7_FN, PTJ6_FN, PTJ5_FN, - PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN, - PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN, - PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN, - PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, - PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN, - PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN, - PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN, - PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN, - PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN, - PTQ7_FN, PTQ6_FN, PTQ5_FN, PTQ4_FN, - PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN, - PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN, - PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN, - PTS6_FN, PTS5_FN, PTS4_FN, - PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN, - PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN, - PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN, - PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN, - PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN, - PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN, - PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN, - PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN, - PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN, - PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN, - PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN, - PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN, - PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN, - PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, - PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, - - - PSA15_0, PSA15_1, - PSA14_0, PSA14_1, - PSA13_0, PSA13_1, - PSA12_0, PSA12_1, - PSA10_0, PSA10_1, - PSA9_0, PSA9_1, - PSA8_0, PSA8_1, - PSA7_0, PSA7_1, - PSA6_0, PSA6_1, - PSA5_0, PSA5_1, - PSA3_0, PSA3_1, - PSA2_0, PSA2_1, - PSA1_0, PSA1_1, - PSA0_0, PSA0_1, - - PSB14_0, PSB14_1, - PSB13_0, PSB13_1, - PSB12_0, PSB12_1, - PSB11_0, PSB11_1, - PSB10_0, PSB10_1, - PSB9_0, PSB9_1, - PSB8_0, PSB8_1, - PSB7_0, PSB7_1, - PSB6_0, PSB6_1, - PSB5_0, PSB5_1, - PSB4_0, PSB4_1, - PSB3_0, PSB3_1, - PSB2_0, PSB2_1, - PSB1_0, PSB1_1, - PSB0_0, PSB0_1, - - PSC15_0, PSC15_1, - PSC14_0, PSC14_1, - PSC13_0, PSC13_1, - PSC12_0, PSC12_1, - PSC11_0, PSC11_1, - PSC10_0, PSC10_1, - PSC9_0, PSC9_1, - PSC8_0, PSC8_1, - PSC7_0, PSC7_1, - PSC6_0, PSC6_1, - PSC5_0, PSC5_1, - PSC4_0, PSC4_1, - PSC2_0, PSC2_1, - PSC1_0, PSC1_1, - PSC0_0, PSC0_1, - - PSD15_0, PSD15_1, - PSD14_0, PSD14_1, - PSD13_0, PSD13_1, - PSD12_0, PSD12_1, - PSD11_0, PSD11_1, - PSD10_0, PSD10_1, - PSD9_0, PSD9_1, - PSD8_0, PSD8_1, - PSD7_0, PSD7_1, - PSD6_0, PSD6_1, - PSD5_0, PSD5_1, - PSD4_0, PSD4_1, - PSD3_0, PSD3_1, - PSD2_0, PSD2_1, - PSD1_0, PSD1_1, - PSD0_0, PSD0_1, - - PSE15_0, PSE15_1, - PSE14_0, PSE14_1, - PSE13_0, PSE13_1, - PSE12_0, PSE12_1, - PSE11_0, PSE11_1, - PSE10_0, PSE10_1, - PSE9_0, PSE9_1, - PSE8_0, PSE8_1, - PSE7_0, PSE7_1, - PSE6_0, PSE6_1, - PSE5_0, PSE5_1, - PSE4_0, PSE4_1, - PSE3_0, PSE3_1, - PSE2_0, PSE2_1, - PSE1_0, PSE1_1, - PSE0_0, PSE0_1, - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - /*PTA*/ - D23_MARK, KEYOUT2_MARK, IDED15_MARK, - D22_MARK, KEYOUT1_MARK, IDED14_MARK, - D21_MARK, KEYOUT0_MARK, IDED13_MARK, - D20_MARK, KEYIN4_MARK, IDED12_MARK, - D19_MARK, KEYIN3_MARK, IDED11_MARK, - D18_MARK, KEYIN2_MARK, IDED10_MARK, - D17_MARK, KEYIN1_MARK, IDED9_MARK, - D16_MARK, KEYIN0_MARK, IDED8_MARK, - - /*PTB*/ - D31_MARK, TPUTO1_MARK, IDEA1_MARK, - D30_MARK, TPUTO0_MARK, IDEA0_MARK, - D29_MARK, IODREQ_MARK, - D28_MARK, IDECS0_MARK, - D27_MARK, IDECS1_MARK, - D26_MARK, KEYOUT5_IN5_MARK, IDEIORD_MARK, - D25_MARK, KEYOUT4_IN6_MARK, IDEIOWR_MARK, - D24_MARK, KEYOUT3_MARK, IDEINT_MARK, - - /*PTC*/ - LCDD7_MARK, - LCDD6_MARK, - LCDD5_MARK, - LCDD4_MARK, - LCDD3_MARK, - LCDD2_MARK, - LCDD1_MARK, - LCDD0_MARK, - - /*PTD*/ - LCDD15_MARK, - LCDD14_MARK, - LCDD13_MARK, - LCDD12_MARK, - LCDD11_MARK, - LCDD10_MARK, - LCDD9_MARK, - LCDD8_MARK, - - /*PTE*/ - FSIMCKB_MARK, - FSIMCKA_MARK, - LCDD21_MARK, SCIF2_L_TXD_MARK, - LCDD20_MARK, SCIF4_SCK_MARK, - LCDD19_MARK, SCIF4_RXD_MARK, - LCDD18_MARK, SCIF4_TXD_MARK, - LCDD17_MARK, - LCDD16_MARK, - - /*PTF*/ - LCDVSYN_MARK, - LCDDISP_MARK, LCDRS_MARK, - LCDHSYN_MARK, LCDCS_MARK, - LCDDON_MARK, - LCDDCK_MARK, LCDWR_MARK, - LCDVEPWC_MARK, SCIF0_TXD_MARK, - LCDD23_MARK, SCIF2_L_SCK_MARK, - LCDD22_MARK, SCIF2_L_RXD_MARK, - - /*PTG*/ - AUDCK_MARK, - AUDSYNC_MARK, - AUDATA3_MARK, - AUDATA2_MARK, - AUDATA1_MARK, - AUDATA0_MARK, - - /*PTH*/ - VIO0_VD_MARK, - VIO0_CLK_MARK, - VIO0_D7_MARK, - VIO0_D6_MARK, - VIO0_D5_MARK, - VIO0_D4_MARK, - VIO0_D3_MARK, - VIO0_D2_MARK, - - /*PTJ*/ - PDSTATUS_MARK, - STATUS2_MARK, - STATUS0_MARK, - A25_MARK, BS_MARK, - A24_MARK, - A23_MARK, - A22_MARK, - - /*PTK*/ - VIO1_D5_MARK, VIO0_D13_MARK, IDED5_MARK, - VIO1_D4_MARK, VIO0_D12_MARK, IDED4_MARK, - VIO1_D3_MARK, VIO0_D11_MARK, IDED3_MARK, - VIO1_D2_MARK, VIO0_D10_MARK, IDED2_MARK, - VIO1_D1_MARK, VIO0_D9_MARK, IDED1_MARK, - VIO1_D0_MARK, VIO0_D8_MARK, IDED0_MARK, - VIO0_FLD_MARK, - VIO0_HD_MARK, - - /*PTL*/ - DV_D5_MARK, SCIF3_V_SCK_MARK, RMII_RXD0_MARK, - DV_D4_MARK, SCIF3_V_RXD_MARK, RMII_RXD1_MARK, - DV_D3_MARK, SCIF3_V_TXD_MARK, RMII_REF_CLK_MARK, - DV_D2_MARK, SCIF1_SCK_MARK, RMII_TX_EN_MARK, - DV_D1_MARK, SCIF1_RXD_MARK, RMII_TXD0_MARK, - DV_D0_MARK, SCIF1_TXD_MARK, RMII_TXD1_MARK, - DV_D15_MARK, - DV_D14_MARK, MSIOF0_MCK_MARK, - - /*PTM*/ - DV_D13_MARK, MSIOF0_TSCK_MARK, - DV_D12_MARK, MSIOF0_RXD_MARK, - DV_D11_MARK, MSIOF0_TXD_MARK, - DV_D10_MARK, MSIOF0_TSYNC_MARK, - DV_D9_MARK, MSIOF0_SS1_MARK, MSIOF0_RSCK_MARK, - DV_D8_MARK, MSIOF0_SS2_MARK, MSIOF0_RSYNC_MARK, - LCDVCPWC_MARK, SCIF0_RXD_MARK, - LCDRD_MARK, SCIF0_SCK_MARK, - - /*PTN*/ - VIO0_D1_MARK, - VIO0_D0_MARK, - DV_CLKI_MARK, - DV_CLK_MARK, SCIF2_V_SCK_MARK, - DV_VSYNC_MARK, SCIF2_V_RXD_MARK, - DV_HSYNC_MARK, SCIF2_V_TXD_MARK, - DV_D7_MARK, SCIF3_V_CTS_MARK, RMII_RX_ER_MARK, - DV_D6_MARK, SCIF3_V_RTS_MARK, RMII_CRS_DV_MARK, - - /*PTQ*/ - D7_MARK, - D6_MARK, - D5_MARK, - D4_MARK, - D3_MARK, - D2_MARK, - D1_MARK, - D0_MARK, - - /*PTR*/ - CS6B_CE1B_MARK, - CS6A_CE2B_MARK, - CS5B_CE1A_MARK, - CS5A_CE2A_MARK, - IOIS16_MARK, LCDLCLK_MARK, - WAIT_MARK, - WE3_ICIOWR_MARK, TPUTO3_MARK, TPUTI3_MARK, - WE2_ICIORD_MARK, TPUTO2_MARK, IDEA2_MARK, - - /*PTS*/ - VIO_CKO_MARK, - VIO1_FLD_MARK, TPUTI2_MARK, IDEIORDY_MARK, - VIO1_HD_MARK, SCIF5_SCK_MARK, - VIO1_VD_MARK, SCIF5_RXD_MARK, - VIO1_CLK_MARK, SCIF5_TXD_MARK, - VIO1_D7_MARK, VIO0_D15_MARK, IDED7_MARK, - VIO1_D6_MARK, VIO0_D14_MARK, IDED6_MARK, - - /*PTT*/ - D15_MARK, - D14_MARK, - D13_MARK, - D12_MARK, - D11_MARK, - D10_MARK, - D9_MARK, - D8_MARK, - - /*PTU*/ - DMAC_DACK0_MARK, - DMAC_DREQ0_MARK, - FSIOASD_MARK, - FSIIABCK_MARK, - FSIIALRCK_MARK, - FSIOABCK_MARK, - FSIOALRCK_MARK, - CLKAUDIOAO_MARK, - - /*PTV*/ - FSIIBSD_MARK, MSIOF1_SS2_MARK, MSIOF1_RSYNC_MARK, - FSIOBSD_MARK, MSIOF1_SS1_MARK, MSIOF1_RSCK_MARK, - FSIIBBCK_MARK, MSIOF1_RXD_MARK, - FSIIBLRCK_MARK, MSIOF1_TSYNC_MARK, - FSIOBBCK_MARK, MSIOF1_TSCK_MARK, - FSIOBLRCK_MARK, MSIOF1_TXD_MARK, - CLKAUDIOBO_MARK, MSIOF1_MCK_MARK, - FSIIASD_MARK, - - /*PTW*/ - MMC_D7_MARK, SDHI1CD_MARK, IODACK_MARK, - MMC_D6_MARK, SDHI1WP_MARK, IDERST_MARK, - MMC_D5_MARK, SDHI1D3_MARK, EXBUF_ENB_MARK, - MMC_D4_MARK, SDHI1D2_MARK, DIRECTION_MARK, - MMC_D3_MARK, SDHI1D1_MARK, - MMC_D2_MARK, SDHI1D0_MARK, - MMC_D1_MARK, SDHI1CMD_MARK, - MMC_D0_MARK, SDHI1CLK_MARK, - - /*PTX*/ - DMAC_DACK1_MARK, IRDA_OUT_MARK, - DMAC_DREQ1_MARK, IRDA_IN_MARK, - TSIF_TS0_SDAT_MARK, LNKSTA_MARK, - TSIF_TS0_SCK_MARK, MDIO_MARK, - TSIF_TS0_SDEN_MARK, MDC_MARK, - TSIF_TS0_SPSYNC_MARK, - MMC_CLK_MARK, - MMC_CMD_MARK, - - /*PTY*/ - SDHI0CD_MARK, - SDHI0WP_MARK, - SDHI0D3_MARK, - SDHI0D2_MARK, - SDHI0D1_MARK, - SDHI0D0_MARK, - SDHI0CMD_MARK, - SDHI0CLK_MARK, - - /*PTZ*/ - INTC_IRQ7_MARK, SCIF3_I_CTS_MARK, - INTC_IRQ6_MARK, SCIF3_I_RTS_MARK, - INTC_IRQ5_MARK, SCIF3_I_SCK_MARK, - INTC_IRQ4_MARK, SCIF3_I_RXD_MARK, - INTC_IRQ3_MARK, SCIF3_I_TXD_MARK, - INTC_IRQ2_MARK, - INTC_IRQ1_MARK, - INTC_IRQ0_MARK, - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - /* PTA GPIO */ - PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), - PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), - PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU), - PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), - PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), - PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), - PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), - PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), - - /* PTB GPIO */ - PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU), - PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU), - PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU), - PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU), - PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU), - PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), - PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), - PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU), - - /* PTC GPIO */ - PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU), - PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU), - PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU), - PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU), - PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU), - PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU), - PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU), - PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU), - - /* PTD GPIO */ - PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU), - PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU), - PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU), - PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU), - PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU), - PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU), - PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU), - PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU), - - /* PTE GPIO */ - PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT, PTE7_IN_PU), - PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT, PTE6_IN_PU), - PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT, PTE5_IN_PU), - PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU), - PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU), - PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU), - PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU), - PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU), - - /* PTF GPIO */ - PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT, PTF7_IN_PU), - PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT, PTF6_IN_PU), - PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT, PTF5_IN_PU), - PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT, PTF4_IN_PU), - PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT, PTF3_IN_PU), - PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT, PTF2_IN_PU), - PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT, PTF1_IN_PU), - PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU), - - /* PTG GPIO */ - PINMUX_DATA(PTG5_DATA, PTG5_OUT), - PINMUX_DATA(PTG4_DATA, PTG4_OUT), - PINMUX_DATA(PTG3_DATA, PTG3_OUT), - PINMUX_DATA(PTG2_DATA, PTG2_OUT), - PINMUX_DATA(PTG1_DATA, PTG1_OUT), - PINMUX_DATA(PTG0_DATA, PTG0_OUT), - - /* PTH GPIO */ - PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT, PTH7_IN_PU), - PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU), - PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU), - PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU), - PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU), - PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU), - PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU), - PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU), - - /* PTJ GPIO */ - PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), - PINMUX_DATA(PTJ6_DATA, PTJ6_OUT), - PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), - PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU), - PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU), - PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU), - PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU), - - /* PTK GPIO */ - PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT, PTK7_IN_PU), - PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT, PTK6_IN_PU), - PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT, PTK5_IN_PU), - PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT, PTK4_IN_PU), - PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU), - PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU), - PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU), - PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU), - - /* PTL GPIO */ - PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU), - PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU), - PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU), - PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU), - PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU), - PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT, PTL2_IN_PU), - PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT, PTL1_IN_PU), - PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT, PTL0_IN_PU), - - /* PTM GPIO */ - PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU), - PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU), - PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU), - PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU), - PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU), - PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU), - PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU), - PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU), - - /* PTN GPIO */ - PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT, PTN7_IN_PU), - PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT, PTN6_IN_PU), - PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT, PTN5_IN_PU), - PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT, PTN4_IN_PU), - PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT, PTN3_IN_PU), - PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT, PTN2_IN_PU), - PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT, PTN1_IN_PU), - PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT, PTN0_IN_PU), - - /* PTQ GPIO */ - PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT, PTQ7_IN_PU), - PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT, PTQ6_IN_PU), - PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT, PTQ5_IN_PU), - PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT, PTQ4_IN_PU), - PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT, PTQ3_IN_PU), - PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT, PTQ2_IN_PU), - PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT, PTQ1_IN_PU), - PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT, PTQ0_IN_PU), - - /* PTR GPIO */ - PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU), - PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU), - PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU), - PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU), - PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_IN_PU), - PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), - PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU), - PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU), - - /* PTS GPIO */ - PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT, PTS6_IN_PU), - PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT, PTS5_IN_PU), - PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU), - PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU), - PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU), - PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU), - PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU), - - /* PTT GPIO */ - PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT, PTT7_IN_PU), - PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT, PTT6_IN_PU), - PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT, PTT5_IN_PU), - PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU), - PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU), - PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU), - PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU), - PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU), - - /* PTU GPIO */ - PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT, PTU7_IN_PU), - PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT, PTU6_IN_PU), - PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT, PTU5_IN_PU), - PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU), - PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU), - PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU), - PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU), - PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU), - - /* PTV GPIO */ - PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT, PTV7_IN_PU), - PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT, PTV6_IN_PU), - PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT, PTV5_IN_PU), - PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU), - PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU), - PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU), - PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU), - PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU), - - /* PTW GPIO */ - PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT, PTW7_IN_PU), - PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT, PTW6_IN_PU), - PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT, PTW5_IN_PU), - PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT, PTW4_IN_PU), - PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT, PTW3_IN_PU), - PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT, PTW2_IN_PU), - PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT, PTW1_IN_PU), - PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT, PTW0_IN_PU), - - /* PTX GPIO */ - PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT, PTX7_IN_PU), - PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT, PTX6_IN_PU), - PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT, PTX5_IN_PU), - PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT, PTX4_IN_PU), - PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT, PTX3_IN_PU), - PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT, PTX2_IN_PU), - PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT, PTX1_IN_PU), - PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT, PTX0_IN_PU), - - /* PTY GPIO */ - PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT, PTY7_IN_PU), - PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT, PTY6_IN_PU), - PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT, PTY5_IN_PU), - PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT, PTY4_IN_PU), - PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT, PTY3_IN_PU), - PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT, PTY2_IN_PU), - PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT, PTY1_IN_PU), - PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT, PTY0_IN_PU), - - /* PTZ GPIO */ - PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT, PTZ7_IN_PU), - PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT, PTZ6_IN_PU), - PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT, PTZ5_IN_PU), - PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT, PTZ4_IN_PU), - PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT, PTZ3_IN_PU), - PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT, PTZ2_IN_PU), - PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT, PTZ1_IN_PU), - PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT, PTZ0_IN_PU), - - /* PTA FN */ - PINMUX_DATA(D23_MARK, PSA15_0, PSA14_0, PTA7_FN), - PINMUX_DATA(D22_MARK, PSA15_0, PSA14_0, PTA6_FN), - PINMUX_DATA(D21_MARK, PSA15_0, PSA14_0, PTA5_FN), - PINMUX_DATA(D20_MARK, PSA15_0, PSA14_0, PTA4_FN), - PINMUX_DATA(D19_MARK, PSA15_0, PSA14_0, PTA3_FN), - PINMUX_DATA(D18_MARK, PSA15_0, PSA14_0, PTA2_FN), - PINMUX_DATA(D17_MARK, PSA15_0, PSA14_0, PTA1_FN), - PINMUX_DATA(D16_MARK, PSA15_0, PSA14_0, PTA0_FN), - - PINMUX_DATA(KEYOUT2_MARK, PSA15_0, PSA14_1, PTA7_FN), - PINMUX_DATA(KEYOUT1_MARK, PSA15_0, PSA14_1, PTA6_FN), - PINMUX_DATA(KEYOUT0_MARK, PSA15_0, PSA14_1, PTA5_FN), - PINMUX_DATA(KEYIN4_MARK, PSA15_0, PSA14_1, PTA4_FN), - PINMUX_DATA(KEYIN3_MARK, PSA15_0, PSA14_1, PTA3_FN), - PINMUX_DATA(KEYIN2_MARK, PSA15_0, PSA14_1, PTA2_FN), - PINMUX_DATA(KEYIN1_MARK, PSA15_0, PSA14_1, PTA1_FN), - PINMUX_DATA(KEYIN0_MARK, PSA15_0, PSA14_1, PTA0_FN), - - PINMUX_DATA(IDED15_MARK, PSA15_1, PSA14_0, PTA7_FN), - PINMUX_DATA(IDED14_MARK, PSA15_1, PSA14_0, PTA6_FN), - PINMUX_DATA(IDED13_MARK, PSA15_1, PSA14_0, PTA5_FN), - PINMUX_DATA(IDED12_MARK, PSA15_1, PSA14_0, PTA4_FN), - PINMUX_DATA(IDED11_MARK, PSA15_1, PSA14_0, PTA3_FN), - PINMUX_DATA(IDED10_MARK, PSA15_1, PSA14_0, PTA2_FN), - PINMUX_DATA(IDED9_MARK, PSA15_1, PSA14_0, PTA1_FN), - PINMUX_DATA(IDED8_MARK, PSA15_1, PSA14_0, PTA0_FN), - - /* PTB FN */ - PINMUX_DATA(D31_MARK, PSE15_0, PSE14_0, PTB7_FN), - PINMUX_DATA(D30_MARK, PSE15_0, PSE14_0, PTB6_FN), - PINMUX_DATA(D29_MARK, PSE11_0, PTB5_FN), - PINMUX_DATA(D28_MARK, PSE11_0, PTB4_FN), - PINMUX_DATA(D27_MARK, PSE11_0, PTB3_FN), - PINMUX_DATA(D26_MARK, PSA15_0, PSA14_0, PTB2_FN), - PINMUX_DATA(D25_MARK, PSA15_0, PSA14_0, PTB1_FN), - PINMUX_DATA(D24_MARK, PSA15_0, PSA14_0, PTB0_FN), - - PINMUX_DATA(IDEA1_MARK, PSE15_1, PSE14_0, PTB7_FN), - PINMUX_DATA(IDEA0_MARK, PSE15_1, PSE14_0, PTB6_FN), - PINMUX_DATA(IODREQ_MARK, PSE11_1, PTB5_FN), - PINMUX_DATA(IDECS0_MARK, PSE11_1, PTB4_FN), - PINMUX_DATA(IDECS1_MARK, PSE11_1, PTB3_FN), - PINMUX_DATA(IDEIORD_MARK, PSA15_1, PSA14_0, PTB2_FN), - PINMUX_DATA(IDEIOWR_MARK, PSA15_1, PSA14_0, PTB1_FN), - PINMUX_DATA(IDEINT_MARK, PSA15_1, PSA14_0, PTB0_FN), - - PINMUX_DATA(TPUTO1_MARK, PSE15_0, PSE14_1, PTB7_FN), - PINMUX_DATA(TPUTO0_MARK, PSE15_0, PSE14_1, PTB6_FN), - - PINMUX_DATA(KEYOUT5_IN5_MARK, PSA15_0, PSA14_1, PTB2_FN), - PINMUX_DATA(KEYOUT4_IN6_MARK, PSA15_0, PSA14_1, PTB1_FN), - PINMUX_DATA(KEYOUT3_MARK, PSA15_0, PSA14_1, PTB0_FN), - - /* PTC FN */ - PINMUX_DATA(LCDD7_MARK, PSD5_0, PTC7_FN), - PINMUX_DATA(LCDD6_MARK, PSD5_0, PTC6_FN), - PINMUX_DATA(LCDD5_MARK, PSD5_0, PTC5_FN), - PINMUX_DATA(LCDD4_MARK, PSD5_0, PTC4_FN), - PINMUX_DATA(LCDD3_MARK, PSD5_0, PTC3_FN), - PINMUX_DATA(LCDD2_MARK, PSD5_0, PTC2_FN), - PINMUX_DATA(LCDD1_MARK, PSD5_0, PTC1_FN), - PINMUX_DATA(LCDD0_MARK, PSD5_0, PTC0_FN), - - /* PTD FN */ - PINMUX_DATA(LCDD15_MARK, PSD5_0, PTD7_FN), - PINMUX_DATA(LCDD14_MARK, PSD5_0, PTD6_FN), - PINMUX_DATA(LCDD13_MARK, PSD5_0, PTD5_FN), - PINMUX_DATA(LCDD12_MARK, PSD5_0, PTD4_FN), - PINMUX_DATA(LCDD11_MARK, PSD5_0, PTD3_FN), - PINMUX_DATA(LCDD10_MARK, PSD5_0, PTD2_FN), - PINMUX_DATA(LCDD9_MARK, PSD5_0, PTD1_FN), - PINMUX_DATA(LCDD8_MARK, PSD5_0, PTD0_FN), - - /* PTE FN */ - PINMUX_DATA(FSIMCKB_MARK, PTE7_FN), - PINMUX_DATA(FSIMCKA_MARK, PTE6_FN), - - PINMUX_DATA(LCDD21_MARK, PSC5_0, PSC4_0, PTE5_FN), - PINMUX_DATA(LCDD20_MARK, PSD3_0, PSD2_0, PTE4_FN), - PINMUX_DATA(LCDD19_MARK, PSA3_0, PSA2_0, PTE3_FN), - PINMUX_DATA(LCDD18_MARK, PSA3_0, PSA2_0, PTE2_FN), - PINMUX_DATA(LCDD17_MARK, PSD5_0, PTE1_FN), - PINMUX_DATA(LCDD16_MARK, PSD5_0, PTE0_FN), - - PINMUX_DATA(SCIF2_L_TXD_MARK, PSC5_0, PSC4_1, PTE5_FN), - PINMUX_DATA(SCIF4_SCK_MARK, PSD3_0, PSD2_1, PTE4_FN), - PINMUX_DATA(SCIF4_RXD_MARK, PSA3_0, PSA2_1, PTE3_FN), - PINMUX_DATA(SCIF4_TXD_MARK, PSA3_0, PSA2_1, PTE2_FN), - - /* PTF FN */ - PINMUX_DATA(LCDVSYN_MARK, PSD8_0, PTF7_FN), - PINMUX_DATA(LCDDISP_MARK, PSD10_0, PSD9_0, PTF6_FN), - PINMUX_DATA(LCDHSYN_MARK, PSD10_0, PSD9_0, PTF5_FN), - PINMUX_DATA(LCDDON_MARK, PSD8_0, PTF4_FN), - PINMUX_DATA(LCDDCK_MARK, PSD10_0, PSD9_0, PTF3_FN), - PINMUX_DATA(LCDVEPWC_MARK, PSA6_0, PTF2_FN), - PINMUX_DATA(LCDD23_MARK, PSC7_0, PSC6_0, PTF1_FN), - PINMUX_DATA(LCDD22_MARK, PSC5_0, PSC4_0, PTF0_FN), - - PINMUX_DATA(LCDRS_MARK, PSD10_0, PSD9_1, PTF6_FN), - PINMUX_DATA(LCDCS_MARK, PSD10_0, PSD9_1, PTF5_FN), - PINMUX_DATA(LCDWR_MARK, PSD10_0, PSD9_1, PTF3_FN), - - PINMUX_DATA(SCIF0_TXD_MARK, PSA6_1, PTF2_FN), - PINMUX_DATA(SCIF2_L_SCK_MARK, PSC7_0, PSC6_1, PTF1_FN), - PINMUX_DATA(SCIF2_L_RXD_MARK, PSC5_0, PSC4_1, PTF0_FN), - - /* PTG FN */ - PINMUX_DATA(AUDCK_MARK, PTG5_FN), - PINMUX_DATA(AUDSYNC_MARK, PTG4_FN), - PINMUX_DATA(AUDATA3_MARK, PTG3_FN), - PINMUX_DATA(AUDATA2_MARK, PTG2_FN), - PINMUX_DATA(AUDATA1_MARK, PTG1_FN), - PINMUX_DATA(AUDATA0_MARK, PTG0_FN), - - /* PTH FN */ - PINMUX_DATA(VIO0_VD_MARK, PTH7_FN), - PINMUX_DATA(VIO0_CLK_MARK, PTH6_FN), - PINMUX_DATA(VIO0_D7_MARK, PTH5_FN), - PINMUX_DATA(VIO0_D6_MARK, PTH4_FN), - PINMUX_DATA(VIO0_D5_MARK, PTH3_FN), - PINMUX_DATA(VIO0_D4_MARK, PTH2_FN), - PINMUX_DATA(VIO0_D3_MARK, PTH1_FN), - PINMUX_DATA(VIO0_D2_MARK, PTH0_FN), - - /* PTJ FN */ - PINMUX_DATA(PDSTATUS_MARK, PTJ7_FN), - PINMUX_DATA(STATUS2_MARK, PTJ6_FN), - PINMUX_DATA(STATUS0_MARK, PTJ5_FN), - PINMUX_DATA(A25_MARK, PSA8_0, PTJ3_FN), - PINMUX_DATA(BS_MARK, PSA8_1, PTJ3_FN), - PINMUX_DATA(A24_MARK, PTJ2_FN), - PINMUX_DATA(A23_MARK, PTJ1_FN), - PINMUX_DATA(A22_MARK, PTJ0_FN), - - /* PTK FN */ - PINMUX_DATA(VIO1_D5_MARK, PSB7_0, PSB6_0, PTK7_FN), - PINMUX_DATA(VIO1_D4_MARK, PSB7_0, PSB6_0, PTK6_FN), - PINMUX_DATA(VIO1_D3_MARK, PSB7_0, PSB6_0, PTK5_FN), - PINMUX_DATA(VIO1_D2_MARK, PSB7_0, PSB6_0, PTK4_FN), - PINMUX_DATA(VIO1_D1_MARK, PSB7_0, PSB6_0, PTK3_FN), - PINMUX_DATA(VIO1_D0_MARK, PSB7_0, PSB6_0, PTK2_FN), - - PINMUX_DATA(VIO0_D13_MARK, PSB7_0, PSB6_1, PTK7_FN), - PINMUX_DATA(VIO0_D12_MARK, PSB7_0, PSB6_1, PTK6_FN), - PINMUX_DATA(VIO0_D11_MARK, PSB7_0, PSB6_1, PTK5_FN), - PINMUX_DATA(VIO0_D10_MARK, PSB7_0, PSB6_1, PTK4_FN), - PINMUX_DATA(VIO0_D9_MARK, PSB7_0, PSB6_1, PTK3_FN), - PINMUX_DATA(VIO0_D8_MARK, PSB7_0, PSB6_1, PTK2_FN), - - PINMUX_DATA(IDED5_MARK, PSB7_1, PSB6_0, PTK7_FN), - PINMUX_DATA(IDED4_MARK, PSB7_1, PSB6_0, PTK6_FN), - PINMUX_DATA(IDED3_MARK, PSB7_1, PSB6_0, PTK5_FN), - PINMUX_DATA(IDED2_MARK, PSB7_1, PSB6_0, PTK4_FN), - PINMUX_DATA(IDED1_MARK, PSB7_1, PSB6_0, PTK3_FN), - PINMUX_DATA(IDED0_MARK, PSB7_1, PSB6_0, PTK2_FN), - - PINMUX_DATA(VIO0_FLD_MARK, PTK1_FN), - PINMUX_DATA(VIO0_HD_MARK, PTK0_FN), - - /* PTL FN */ - PINMUX_DATA(DV_D5_MARK, PSB9_0, PSB8_0, PTL7_FN), - PINMUX_DATA(DV_D4_MARK, PSB9_0, PSB8_0, PTL6_FN), - PINMUX_DATA(DV_D3_MARK, PSE7_0, PSE6_0, PTL5_FN), - PINMUX_DATA(DV_D2_MARK, PSC9_0, PSC8_0, PTL4_FN), - PINMUX_DATA(DV_D1_MARK, PSC9_0, PSC8_0, PTL3_FN), - PINMUX_DATA(DV_D0_MARK, PSC9_0, PSC8_0, PTL2_FN), - PINMUX_DATA(DV_D15_MARK, PSD4_0, PTL1_FN), - PINMUX_DATA(DV_D14_MARK, PSE5_0, PSE4_0, PTL0_FN), - - PINMUX_DATA(SCIF3_V_SCK_MARK, PSB9_0, PSB8_1, PTL7_FN), - PINMUX_DATA(SCIF3_V_RXD_MARK, PSB9_0, PSB8_1, PTL6_FN), - PINMUX_DATA(SCIF3_V_TXD_MARK, PSE7_0, PSE6_1, PTL5_FN), - PINMUX_DATA(SCIF1_SCK_MARK, PSC9_0, PSC8_1, PTL4_FN), - PINMUX_DATA(SCIF1_RXD_MARK, PSC9_0, PSC8_1, PTL3_FN), - PINMUX_DATA(SCIF1_TXD_MARK, PSC9_0, PSC8_1, PTL2_FN), - - PINMUX_DATA(RMII_RXD0_MARK, PSB9_1, PSB8_0, PTL7_FN), - PINMUX_DATA(RMII_RXD1_MARK, PSB9_1, PSB8_0, PTL6_FN), - PINMUX_DATA(RMII_REF_CLK_MARK, PSE7_1, PSE6_0, PTL5_FN), - PINMUX_DATA(RMII_TX_EN_MARK, PSC9_1, PSC8_0, PTL4_FN), - PINMUX_DATA(RMII_TXD0_MARK, PSC9_1, PSC8_0, PTL3_FN), - PINMUX_DATA(RMII_TXD1_MARK, PSC9_1, PSC8_0, PTL2_FN), - - PINMUX_DATA(MSIOF0_MCK_MARK, PSE5_0, PSE4_1, PTL0_FN), - - /* PTM FN */ - PINMUX_DATA(DV_D13_MARK, PSC13_0, PSC12_0, PTM7_FN), - PINMUX_DATA(DV_D12_MARK, PSC13_0, PSC12_0, PTM6_FN), - PINMUX_DATA(DV_D11_MARK, PSC13_0, PSC12_0, PTM5_FN), - PINMUX_DATA(DV_D10_MARK, PSC13_0, PSC12_0, PTM4_FN), - PINMUX_DATA(DV_D9_MARK, PSC11_0, PSC10_0, PTM3_FN), - PINMUX_DATA(DV_D8_MARK, PSC11_0, PSC10_0, PTM2_FN), - - PINMUX_DATA(MSIOF0_TSCK_MARK, PSC13_0, PSC12_1, PTM7_FN), - PINMUX_DATA(MSIOF0_RXD_MARK, PSC13_0, PSC12_1, PTM6_FN), - PINMUX_DATA(MSIOF0_TXD_MARK, PSC13_0, PSC12_1, PTM5_FN), - PINMUX_DATA(MSIOF0_TSYNC_MARK, PSC13_0, PSC12_1, PTM4_FN), - PINMUX_DATA(MSIOF0_SS1_MARK, PSC11_0, PSC10_1, PTM3_FN), - PINMUX_DATA(MSIOF0_RSCK_MARK, PSC11_1, PSC10_0, PTM3_FN), - PINMUX_DATA(MSIOF0_SS2_MARK, PSC11_0, PSC10_1, PTM2_FN), - PINMUX_DATA(MSIOF0_RSYNC_MARK, PSC11_1, PSC10_0, PTM2_FN), - - PINMUX_DATA(LCDVCPWC_MARK, PSA6_0, PTM1_FN), - PINMUX_DATA(LCDRD_MARK, PSA7_0, PTM0_FN), - - PINMUX_DATA(SCIF0_RXD_MARK, PSA6_1, PTM1_FN), - PINMUX_DATA(SCIF0_SCK_MARK, PSA7_1, PTM0_FN), - - /* PTN FN */ - PINMUX_DATA(VIO0_D1_MARK, PTN7_FN), - PINMUX_DATA(VIO0_D0_MARK, PTN6_FN), - - PINMUX_DATA(DV_CLKI_MARK, PSD11_0, PTN5_FN), - PINMUX_DATA(DV_CLK_MARK, PSD13_0, PSD12_0, PTN4_FN), - PINMUX_DATA(DV_VSYNC_MARK, PSD15_0, PSD14_0, PTN3_FN), - PINMUX_DATA(DV_HSYNC_MARK, PSB5_0, PSB4_0, PTN2_FN), - PINMUX_DATA(DV_D7_MARK, PSB3_0, PSB2_0, PTN1_FN), - PINMUX_DATA(DV_D6_MARK, PSB1_0, PSB0_0, PTN0_FN), - - PINMUX_DATA(SCIF2_V_SCK_MARK, PSD13_0, PSD12_1, PTN4_FN), - PINMUX_DATA(SCIF2_V_RXD_MARK, PSD15_0, PSD14_1, PTN3_FN), - PINMUX_DATA(SCIF2_V_TXD_MARK, PSB5_0, PSB4_1, PTN2_FN), - PINMUX_DATA(SCIF3_V_CTS_MARK, PSB3_0, PSB2_1, PTN1_FN), - PINMUX_DATA(SCIF3_V_RTS_MARK, PSB1_0, PSB0_1, PTN0_FN), - - PINMUX_DATA(RMII_RX_ER_MARK, PSB3_1, PSB2_0, PTN1_FN), - PINMUX_DATA(RMII_CRS_DV_MARK, PSB1_1, PSB0_0, PTN0_FN), - - /* PTQ FN */ - PINMUX_DATA(D7_MARK, PTQ7_FN), - PINMUX_DATA(D6_MARK, PTQ6_FN), - PINMUX_DATA(D5_MARK, PTQ5_FN), - PINMUX_DATA(D4_MARK, PTQ4_FN), - PINMUX_DATA(D3_MARK, PTQ3_FN), - PINMUX_DATA(D2_MARK, PTQ2_FN), - PINMUX_DATA(D1_MARK, PTQ1_FN), - PINMUX_DATA(D0_MARK, PTQ0_FN), - - /* PTR FN */ - PINMUX_DATA(CS6B_CE1B_MARK, PTR7_FN), - PINMUX_DATA(CS6A_CE2B_MARK, PTR6_FN), - PINMUX_DATA(CS5B_CE1A_MARK, PTR5_FN), - PINMUX_DATA(CS5A_CE2A_MARK, PTR4_FN), - PINMUX_DATA(IOIS16_MARK, PSA5_0, PTR3_FN), - PINMUX_DATA(WAIT_MARK, PTR2_FN), - PINMUX_DATA(WE3_ICIOWR_MARK, PSA1_0, PSA0_0, PTR1_FN), - PINMUX_DATA(WE2_ICIORD_MARK, PSD1_0, PSD0_0, PTR0_FN), - - PINMUX_DATA(LCDLCLK_MARK, PSA5_1, PTR3_FN), - - PINMUX_DATA(IDEA2_MARK, PSD1_1, PSD0_0, PTR0_FN), - - PINMUX_DATA(TPUTO3_MARK, PSA1_0, PSA0_1, PTR1_FN), - PINMUX_DATA(TPUTI3_MARK, PSA1_1, PSA0_0, PTR1_FN), - PINMUX_DATA(TPUTO2_MARK, PSD1_0, PSD0_1, PTR0_FN), - - /* PTS FN */ - PINMUX_DATA(VIO_CKO_MARK, PTS6_FN), - - PINMUX_DATA(TPUTI2_MARK, PSE9_0, PSE8_1, PTS5_FN), - - PINMUX_DATA(IDEIORDY_MARK, PSE9_1, PSE8_0, PTS5_FN), - - PINMUX_DATA(VIO1_FLD_MARK, PSE9_0, PSE8_0, PTS5_FN), - PINMUX_DATA(VIO1_HD_MARK, PSA10_0, PTS4_FN), - PINMUX_DATA(VIO1_VD_MARK, PSA9_0, PTS3_FN), - PINMUX_DATA(VIO1_CLK_MARK, PSA9_0, PTS2_FN), - PINMUX_DATA(VIO1_D7_MARK, PSB7_0, PSB6_0, PTS1_FN), - PINMUX_DATA(VIO1_D6_MARK, PSB7_0, PSB6_0, PTS0_FN), - - PINMUX_DATA(SCIF5_SCK_MARK, PSA10_1, PTS4_FN), - PINMUX_DATA(SCIF5_RXD_MARK, PSA9_1, PTS3_FN), - PINMUX_DATA(SCIF5_TXD_MARK, PSA9_1, PTS2_FN), - - PINMUX_DATA(VIO0_D15_MARK, PSB7_0, PSB6_1, PTS1_FN), - PINMUX_DATA(VIO0_D14_MARK, PSB7_0, PSB6_1, PTS0_FN), - - PINMUX_DATA(IDED7_MARK, PSB7_1, PSB6_0, PTS1_FN), - PINMUX_DATA(IDED6_MARK, PSB7_1, PSB6_0, PTS0_FN), - - /* PTT FN */ - PINMUX_DATA(D15_MARK, PTT7_FN), - PINMUX_DATA(D14_MARK, PTT6_FN), - PINMUX_DATA(D13_MARK, PTT5_FN), - PINMUX_DATA(D12_MARK, PTT4_FN), - PINMUX_DATA(D11_MARK, PTT3_FN), - PINMUX_DATA(D10_MARK, PTT2_FN), - PINMUX_DATA(D9_MARK, PTT1_FN), - PINMUX_DATA(D8_MARK, PTT0_FN), - - /* PTU FN */ - PINMUX_DATA(DMAC_DACK0_MARK, PTU7_FN), - PINMUX_DATA(DMAC_DREQ0_MARK, PTU6_FN), - - PINMUX_DATA(FSIOASD_MARK, PSE1_0, PTU5_FN), - PINMUX_DATA(FSIIABCK_MARK, PSE1_0, PTU4_FN), - PINMUX_DATA(FSIIALRCK_MARK, PSE1_0, PTU3_FN), - PINMUX_DATA(FSIOABCK_MARK, PSE1_0, PTU2_FN), - PINMUX_DATA(FSIOALRCK_MARK, PSE1_0, PTU1_FN), - PINMUX_DATA(CLKAUDIOAO_MARK, PSE0_0, PTU0_FN), - - /* PTV FN */ - PINMUX_DATA(FSIIBSD_MARK, PSD7_0, PSD6_0, PTV7_FN), - PINMUX_DATA(FSIOBSD_MARK, PSD7_0, PSD6_0, PTV6_FN), - PINMUX_DATA(FSIIBBCK_MARK, PSC15_0, PSC14_0, PTV5_FN), - PINMUX_DATA(FSIIBLRCK_MARK, PSC15_0, PSC14_0, PTV4_FN), - PINMUX_DATA(FSIOBBCK_MARK, PSC15_0, PSC14_0, PTV3_FN), - PINMUX_DATA(FSIOBLRCK_MARK, PSC15_0, PSC14_0, PTV2_FN), - PINMUX_DATA(CLKAUDIOBO_MARK, PSE3_0, PSE2_0, PTV1_FN), - PINMUX_DATA(FSIIASD_MARK, PSE10_0, PTV0_FN), - - PINMUX_DATA(MSIOF1_SS2_MARK, PSD7_0, PSD6_1, PTV7_FN), - PINMUX_DATA(MSIOF1_RSYNC_MARK, PSD7_1, PSD6_0, PTV7_FN), - PINMUX_DATA(MSIOF1_SS1_MARK, PSD7_0, PSD6_1, PTV6_FN), - PINMUX_DATA(MSIOF1_RSCK_MARK, PSD7_1, PSD6_0, PTV6_FN), - PINMUX_DATA(MSIOF1_RXD_MARK, PSC15_0, PSC14_1, PTV5_FN), - PINMUX_DATA(MSIOF1_TSYNC_MARK, PSC15_0, PSC14_1, PTV4_FN), - PINMUX_DATA(MSIOF1_TSCK_MARK, PSC15_0, PSC14_1, PTV3_FN), - PINMUX_DATA(MSIOF1_TXD_MARK, PSC15_0, PSC14_1, PTV2_FN), - PINMUX_DATA(MSIOF1_MCK_MARK, PSE3_0, PSE2_1, PTV1_FN), - - /* PTW FN */ - PINMUX_DATA(MMC_D7_MARK, PSE13_0, PSE12_0, PTW7_FN), - PINMUX_DATA(MMC_D6_MARK, PSE13_0, PSE12_0, PTW6_FN), - PINMUX_DATA(MMC_D5_MARK, PSE13_0, PSE12_0, PTW5_FN), - PINMUX_DATA(MMC_D4_MARK, PSE13_0, PSE12_0, PTW4_FN), - PINMUX_DATA(MMC_D3_MARK, PSA13_0, PTW3_FN), - PINMUX_DATA(MMC_D2_MARK, PSA13_0, PTW2_FN), - PINMUX_DATA(MMC_D1_MARK, PSA13_0, PTW1_FN), - PINMUX_DATA(MMC_D0_MARK, PSA13_0, PTW0_FN), - - PINMUX_DATA(SDHI1CD_MARK, PSE13_0, PSE12_1, PTW7_FN), - PINMUX_DATA(SDHI1WP_MARK, PSE13_0, PSE12_1, PTW6_FN), - PINMUX_DATA(SDHI1D3_MARK, PSE13_0, PSE12_1, PTW5_FN), - PINMUX_DATA(SDHI1D2_MARK, PSE13_0, PSE12_1, PTW4_FN), - PINMUX_DATA(SDHI1D1_MARK, PSA13_1, PTW3_FN), - PINMUX_DATA(SDHI1D0_MARK, PSA13_1, PTW2_FN), - PINMUX_DATA(SDHI1CMD_MARK, PSA13_1, PTW1_FN), - PINMUX_DATA(SDHI1CLK_MARK, PSA13_1, PTW0_FN), - - PINMUX_DATA(IODACK_MARK, PSE13_1, PSE12_0, PTW7_FN), - PINMUX_DATA(IDERST_MARK, PSE13_1, PSE12_0, PTW6_FN), - PINMUX_DATA(EXBUF_ENB_MARK, PSE13_1, PSE12_0, PTW5_FN), - PINMUX_DATA(DIRECTION_MARK, PSE13_1, PSE12_0, PTW4_FN), - - /* PTX FN */ - PINMUX_DATA(DMAC_DACK1_MARK, PSA12_0, PTX7_FN), - PINMUX_DATA(DMAC_DREQ1_MARK, PSA12_0, PTX6_FN), - - PINMUX_DATA(IRDA_OUT_MARK, PSA12_1, PTX7_FN), - PINMUX_DATA(IRDA_IN_MARK, PSA12_1, PTX6_FN), - - PINMUX_DATA(TSIF_TS0_SDAT_MARK, PSC0_0, PTX5_FN), - PINMUX_DATA(TSIF_TS0_SCK_MARK, PSC1_0, PTX4_FN), - PINMUX_DATA(TSIF_TS0_SDEN_MARK, PSC2_0, PTX3_FN), - PINMUX_DATA(TSIF_TS0_SPSYNC_MARK, PTX2_FN), - - PINMUX_DATA(LNKSTA_MARK, PSC0_1, PTX5_FN), - PINMUX_DATA(MDIO_MARK, PSC1_1, PTX4_FN), - PINMUX_DATA(MDC_MARK, PSC2_1, PTX3_FN), - - PINMUX_DATA(MMC_CLK_MARK, PTX1_FN), - PINMUX_DATA(MMC_CMD_MARK, PTX0_FN), - - /* PTY FN */ - PINMUX_DATA(SDHI0CD_MARK, PTY7_FN), - PINMUX_DATA(SDHI0WP_MARK, PTY6_FN), - PINMUX_DATA(SDHI0D3_MARK, PTY5_FN), - PINMUX_DATA(SDHI0D2_MARK, PTY4_FN), - PINMUX_DATA(SDHI0D1_MARK, PTY3_FN), - PINMUX_DATA(SDHI0D0_MARK, PTY2_FN), - PINMUX_DATA(SDHI0CMD_MARK, PTY1_FN), - PINMUX_DATA(SDHI0CLK_MARK, PTY0_FN), - - /* PTZ FN */ - PINMUX_DATA(INTC_IRQ7_MARK, PSB10_0, PTZ7_FN), - PINMUX_DATA(INTC_IRQ6_MARK, PSB11_0, PTZ6_FN), - PINMUX_DATA(INTC_IRQ5_MARK, PSB12_0, PTZ5_FN), - PINMUX_DATA(INTC_IRQ4_MARK, PSB13_0, PTZ4_FN), - PINMUX_DATA(INTC_IRQ3_MARK, PSB14_0, PTZ3_FN), - PINMUX_DATA(INTC_IRQ2_MARK, PTZ2_FN), - PINMUX_DATA(INTC_IRQ1_MARK, PTZ1_FN), - PINMUX_DATA(INTC_IRQ0_MARK, PTZ0_FN), - - PINMUX_DATA(SCIF3_I_CTS_MARK, PSB10_1, PTZ7_FN), - PINMUX_DATA(SCIF3_I_RTS_MARK, PSB11_1, PTZ6_FN), - PINMUX_DATA(SCIF3_I_SCK_MARK, PSB12_1, PTZ5_FN), - PINMUX_DATA(SCIF3_I_RXD_MARK, PSB13_1, PTZ4_FN), - PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - /* PTA */ - PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), - PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), - PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), - PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), - PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), - PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), - PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), - PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), - - /* PTB */ - PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), - PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), - PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), - PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), - PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), - PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), - PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), - PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), - - /* PTC */ - PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), - PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), - PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), - PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), - PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), - PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), - PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), - PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), - - /* PTD */ - PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), - PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), - PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), - PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), - PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), - PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), - PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), - PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), - - /* PTE */ - PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), - PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), - PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), - PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), - PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), - PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), - PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), - PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), - - /* PTF */ - PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), - PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), - PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), - PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), - PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), - PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), - PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), - PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), - - /* PTG */ - PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), - PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), - PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), - PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), - PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), - PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), - - /* PTH */ - PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), - PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), - PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), - PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), - PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), - PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), - PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), - PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), - - /* PTJ */ - PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), - PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), - PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), - PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), - PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), - PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), - PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), - - /* PTK */ - PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), - PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), - PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), - PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), - PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), - PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), - PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), - PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), - - /* PTL */ - PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), - PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), - PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), - PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), - PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), - PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), - PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), - PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), - - /* PTM */ - PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), - PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), - PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), - PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), - PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), - PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), - PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), - PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), - - /* PTN */ - PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), - PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), - PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), - PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), - PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), - PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), - PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), - PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), - - /* PTQ */ - PINMUX_GPIO(GPIO_PTQ7, PTQ7_DATA), - PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), - PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), - PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), - PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), - PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), - PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), - PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), - - /* PTR */ - PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), - PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), - PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), - PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), - PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), - PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), - PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), - PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), - - /* PTS */ - PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), - PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), - PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), - PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), - PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), - PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), - PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), - - /* PTT */ - PINMUX_GPIO(GPIO_PTT7, PTT7_DATA), - PINMUX_GPIO(GPIO_PTT6, PTT6_DATA), - PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), - PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), - PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), - PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), - PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), - PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), - - /* PTU */ - PINMUX_GPIO(GPIO_PTU7, PTU7_DATA), - PINMUX_GPIO(GPIO_PTU6, PTU6_DATA), - PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), - PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), - PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), - PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), - PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), - PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), - - /* PTV */ - PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), - PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), - PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), - PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), - PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), - PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), - PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), - PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), - - /* PTW */ - PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), - PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), - PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), - PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), - PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), - PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), - PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), - PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), - - /* PTX */ - PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), - PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), - PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), - PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), - PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), - PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), - PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), - PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), - - /* PTY */ - PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), - PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), - PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), - PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), - PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), - PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), - PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), - PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), - - /* PTZ */ - PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), - PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), - PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), - PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), - PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), - PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), - PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), - PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), - - /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), - PINMUX_GPIO(GPIO_FN_D7, D7_MARK), - PINMUX_GPIO(GPIO_FN_D6, D6_MARK), - PINMUX_GPIO(GPIO_FN_D5, D5_MARK), - PINMUX_GPIO(GPIO_FN_D4, D4_MARK), - PINMUX_GPIO(GPIO_FN_D3, D3_MARK), - PINMUX_GPIO(GPIO_FN_D2, D2_MARK), - PINMUX_GPIO(GPIO_FN_D1, D1_MARK), - PINMUX_GPIO(GPIO_FN_D0, D0_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), - PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), - PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - - /* KEYSC */ - PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), - - /* ATAPI */ - PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), - PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), - PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), - PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), - PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), - PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), - PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), - PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), - PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), - PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), - PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), - PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), - PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), - PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), - PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), - PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), - PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), - PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), - PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), - PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), - PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), - PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), - PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), - PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), - PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), - PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), - PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), - PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), - - /* TPU */ - PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), - PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK), - PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK), - - /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), - PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), - PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), - PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), - PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), - PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), - PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), - PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), - PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), - PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), - PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), - PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), - PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), - PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), - PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), - PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), - PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), - PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), - PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), - PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), - PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), - PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), - PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), - PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), - PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), - PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), - PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), - PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), - PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), - - /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), - - /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - - /* SCIF2 */ - PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK), - - /* SCIF3 */ - PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK), - - /* SCIF4 */ - PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), - - /* SCIF5 */ - PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), - - /* FSI */ - PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK), - PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK), - PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK), - PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK), - PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK), - PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK), - PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK), - PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK), - PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK), - PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK), - - /* AUD */ - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), - - /* VIO */ - PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), - - /* VIO0 */ - PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK), - - /* VIO1 */ - PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK), - - /* Eth */ - PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK), - PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK), - PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK), - PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK), - PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK), - - /* System */ - PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), - PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - - /* VOU */ - PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), - PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), - PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), - PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), - PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), - PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), - PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), - PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), - PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), - PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), - PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), - PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), - PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), - PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), - PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), - PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), - - /* MSIOF0 */ - PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK), - - /* MSIOF1 */ - PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), - - /* DMAC */ - PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK), - - /* SDHI0 */ - PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK), - - /* SDHI1 */ - PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), - - /* MMC */ - PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), - - /* IrDA */ - PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), - PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), - - /* TSIF */ - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK), - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK), - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK), - - /* IRQ */ - PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK), - }; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { - PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, - PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, - PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN, - PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, - PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, - PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, - PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, - PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } +static struct resource sh7724_pfc_resources[] = { + [0] = { + .start = 0xa4050100, + .end = 0xa405016f, + .flags = IORESOURCE_MEM, }, - { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { - PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN, - PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN, - PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN, - PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN, - PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN, - PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, - PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, - PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN } - }, - { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { - PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN, - PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN, - PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN, - PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN, - PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN, - PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN, - PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN, - PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN } - }, - { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { - PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN, - PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN, - PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN, - PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN, - PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN, - PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN, - PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN, - PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN } - }, - { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { - PTE7_FN, PTE7_OUT, PTE7_IN_PU, PTE7_IN, - PTE6_FN, PTE6_OUT, PTE6_IN_PU, PTE6_IN, - PTE5_FN, PTE5_OUT, PTE5_IN_PU, PTE5_IN, - PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN, - PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN, - PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN, - PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN, - PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN } - }, - { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { - PTF7_FN, PTF7_OUT, PTF7_IN_PU, PTF7_IN, - PTF6_FN, PTF6_OUT, PTF6_IN_PU, PTF6_IN, - PTF5_FN, PTF5_OUT, PTF5_IN_PU, PTF5_IN, - PTF4_FN, PTF4_OUT, PTF4_IN_PU, PTF4_IN, - PTF3_FN, PTF3_OUT, PTF3_IN_PU, PTF3_IN, - PTF2_FN, PTF2_OUT, PTF2_IN_PU, PTF2_IN, - PTF1_FN, PTF1_OUT, PTF1_IN_PU, PTF1_IN, - PTF0_FN, PTF0_OUT, PTF0_IN_PU, PTF0_IN } - }, - { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - PTG5_FN, PTG5_OUT, 0, 0, - PTG4_FN, PTG4_OUT, 0, 0, - PTG3_FN, PTG3_OUT, 0, 0, - PTG2_FN, PTG2_OUT, 0, 0, - PTG1_FN, PTG1_OUT, 0, 0, - PTG0_FN, PTG0_OUT, 0, 0 } - }, - { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { - PTH7_FN, PTH7_OUT, PTH7_IN_PU, PTH7_IN, - PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN, - PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN, - PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN, - PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN, - PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN, - PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN, - PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN } - }, - { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { - PTJ7_FN, PTJ7_OUT, 0, 0, - PTJ6_FN, PTJ6_OUT, 0, 0, - PTJ5_FN, PTJ5_OUT, 0, 0, - 0, 0, 0, 0, - PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN, - PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN, - PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, - PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } - }, - { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { - PTK7_FN, PTK7_OUT, PTK7_IN_PU, PTK7_IN, - PTK6_FN, PTK6_OUT, PTK6_IN_PU, PTK6_IN, - PTK5_FN, PTK5_OUT, PTK5_IN_PU, PTK5_IN, - PTK4_FN, PTK4_OUT, PTK4_IN_PU, PTK4_IN, - PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN, - PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN, - PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN, - PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN } - }, - { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { - PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN, - PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN, - PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN, - PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN, - PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN, - PTL2_FN, PTL2_OUT, PTL2_IN_PU, PTL2_IN, - PTL1_FN, PTL1_OUT, PTL1_IN_PU, PTL1_IN, - PTL0_FN, PTL0_OUT, PTL0_IN_PU, PTL0_IN } - }, - { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { - PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN, - PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN, - PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN, - PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN, - PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN, - PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN, - PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN, - PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN } - }, - { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { - PTN7_FN, PTN7_OUT, PTN7_IN_PU, PTN7_IN, - PTN6_FN, PTN6_OUT, PTN6_IN_PU, PTN6_IN, - PTN5_FN, PTN5_OUT, PTN5_IN_PU, PTN5_IN, - PTN4_FN, PTN4_OUT, PTN4_IN_PU, PTN4_IN, - PTN3_FN, PTN3_OUT, PTN3_IN_PU, PTN3_IN, - PTN2_FN, PTN2_OUT, PTN2_IN_PU, PTN2_IN, - PTN1_FN, PTN1_OUT, PTN1_IN_PU, PTN1_IN, - PTN0_FN, PTN0_OUT, PTN0_IN_PU, PTN0_IN } - }, - { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { - PTQ7_FN, PTQ7_OUT, PTQ7_IN_PU, PTQ7_IN, - PTQ6_FN, PTQ6_OUT, PTQ6_IN_PU, PTQ6_IN, - PTQ5_FN, PTQ5_OUT, PTQ5_IN_PU, PTQ5_IN, - PTQ4_FN, PTQ4_OUT, PTQ4_IN_PU, PTQ4_IN, - PTQ3_FN, PTQ3_OUT, PTQ3_IN_PU, PTQ3_IN, - PTQ2_FN, PTQ2_OUT, PTQ2_IN_PU, PTQ2_IN, - PTQ1_FN, PTQ1_OUT, PTQ1_IN_PU, PTQ1_IN, - PTQ0_FN, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN } - }, - { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { - PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN, - PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN, - PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN, - PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN, - PTR3_FN, 0, PTR3_IN_PU, PTR3_IN, - PTR2_FN, 0, PTR2_IN_PU, PTR2_IN, - PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN, - PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN } - }, - { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { - 0, 0, 0, 0, - PTS6_FN, PTS6_OUT, PTS6_IN_PU, PTS6_IN, - PTS5_FN, PTS5_OUT, PTS5_IN_PU, PTS5_IN, - PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN, - PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN, - PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN, - PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN, - PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN } - }, - { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { - PTT7_FN, PTT7_OUT, PTT7_IN_PU, PTT7_IN, - PTT6_FN, PTT6_OUT, PTT6_IN_PU, PTT6_IN, - PTT5_FN, PTT5_OUT, PTT5_IN_PU, PTT5_IN, - PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN, - PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN, - PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN, - PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN, - PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN } - }, - { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { - PTU7_FN, PTU7_OUT, PTU7_IN_PU, PTU7_IN, - PTU6_FN, PTU6_OUT, PTU6_IN_PU, PTU6_IN, - PTU5_FN, PTU5_OUT, PTU5_IN_PU, PTU5_IN, - PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN, - PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN, - PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN, - PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN, - PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN } - }, - { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { - PTV7_FN, PTV7_OUT, PTV7_IN_PU, PTV7_IN, - PTV6_FN, PTV6_OUT, PTV6_IN_PU, PTV6_IN, - PTV5_FN, PTV5_OUT, PTV5_IN_PU, PTV5_IN, - PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN, - PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN, - PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN, - PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN, - PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN } - }, - { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { - PTW7_FN, PTW7_OUT, PTW7_IN_PU, PTW7_IN, - PTW6_FN, PTW6_OUT, PTW6_IN_PU, PTW6_IN, - PTW5_FN, PTW5_OUT, PTW5_IN_PU, PTW5_IN, - PTW4_FN, PTW4_OUT, PTW4_IN_PU, PTW4_IN, - PTW3_FN, PTW3_OUT, PTW3_IN_PU, PTW3_IN, - PTW2_FN, PTW2_OUT, PTW2_IN_PU, PTW2_IN, - PTW1_FN, PTW1_OUT, PTW1_IN_PU, PTW1_IN, - PTW0_FN, PTW0_OUT, PTW0_IN_PU, PTW0_IN } - }, - { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { - PTX7_FN, PTX7_OUT, PTX7_IN_PU, PTX7_IN, - PTX6_FN, PTX6_OUT, PTX6_IN_PU, PTX6_IN, - PTX5_FN, PTX5_OUT, PTX5_IN_PU, PTX5_IN, - PTX4_FN, PTX4_OUT, PTX4_IN_PU, PTX4_IN, - PTX3_FN, PTX3_OUT, PTX3_IN_PU, PTX3_IN, - PTX2_FN, PTX2_OUT, PTX2_IN_PU, PTX2_IN, - PTX1_FN, PTX1_OUT, PTX1_IN_PU, PTX1_IN, - PTX0_FN, PTX0_OUT, PTX0_IN_PU, PTX0_IN } - }, - { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { - PTY7_FN, PTY7_OUT, PTY7_IN_PU, PTY7_IN, - PTY6_FN, PTY6_OUT, PTY6_IN_PU, PTY6_IN, - PTY5_FN, PTY5_OUT, PTY5_IN_PU, PTY5_IN, - PTY4_FN, PTY4_OUT, PTY4_IN_PU, PTY4_IN, - PTY3_FN, PTY3_OUT, PTY3_IN_PU, PTY3_IN, - PTY2_FN, PTY2_OUT, PTY2_IN_PU, PTY2_IN, - PTY1_FN, PTY1_OUT, PTY1_IN_PU, PTY1_IN, - PTY0_FN, PTY0_OUT, PTY0_IN_PU, PTY0_IN } - }, - { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { - PTZ7_FN, PTZ7_OUT, PTZ7_IN_PU, PTZ7_IN, - PTZ6_FN, PTZ6_OUT, PTZ6_IN_PU, PTZ6_IN, - PTZ5_FN, PTZ5_OUT, PTZ5_IN_PU, PTZ5_IN, - PTZ4_FN, PTZ4_OUT, PTZ4_IN_PU, PTZ4_IN, - PTZ3_FN, PTZ3_OUT, PTZ3_IN_PU, PTZ3_IN, - PTZ2_FN, PTZ2_OUT, PTZ2_IN_PU, PTZ2_IN, - PTZ1_FN, PTZ1_OUT, PTZ1_IN_PU, PTZ1_IN, - PTZ0_FN, PTZ0_OUT, PTZ0_IN_PU, PTZ0_IN } - }, - { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { - PSA15_0, PSA15_1, - PSA14_0, PSA14_1, - PSA13_0, PSA13_1, - PSA12_0, PSA12_1, - 0, 0, - PSA10_0, PSA10_1, - PSA9_0, PSA9_1, - PSA8_0, PSA8_1, - PSA7_0, PSA7_1, - PSA6_0, PSA6_1, - PSA5_0, PSA5_1, - 0, 0, - PSA3_0, PSA3_1, - PSA2_0, PSA2_1, - PSA1_0, PSA1_1, - PSA0_0, PSA0_1} - }, - { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) { - 0, 0, - PSB14_0, PSB14_1, - PSB13_0, PSB13_1, - PSB12_0, PSB12_1, - PSB11_0, PSB11_1, - PSB10_0, PSB10_1, - PSB9_0, PSB9_1, - PSB8_0, PSB8_1, - PSB7_0, PSB7_1, - PSB6_0, PSB6_1, - PSB5_0, PSB5_1, - PSB4_0, PSB4_1, - PSB3_0, PSB3_1, - PSB2_0, PSB2_1, - PSB1_0, PSB1_1, - PSB0_0, PSB0_1} - }, - { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) { - PSC15_0, PSC15_1, - PSC14_0, PSC14_1, - PSC13_0, PSC13_1, - PSC12_0, PSC12_1, - PSC11_0, PSC11_1, - PSC10_0, PSC10_1, - PSC9_0, PSC9_1, - PSC8_0, PSC8_1, - PSC7_0, PSC7_1, - PSC6_0, PSC6_1, - PSC5_0, PSC5_1, - PSC4_0, PSC4_1, - 0, 0, - PSC2_0, PSC2_1, - PSC1_0, PSC1_1, - PSC0_0, PSC0_1} - }, - { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) { - PSD15_0, PSD15_1, - PSD14_0, PSD14_1, - PSD13_0, PSD13_1, - PSD12_0, PSD12_1, - PSD11_0, PSD11_1, - PSD10_0, PSD10_1, - PSD9_0, PSD9_1, - PSD8_0, PSD8_1, - PSD7_0, PSD7_1, - PSD6_0, PSD6_1, - PSD5_0, PSD5_1, - PSD4_0, PSD4_1, - PSD3_0, PSD3_1, - PSD2_0, PSD2_1, - PSD1_0, PSD1_1, - PSD0_0, PSD0_1} - }, - { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) { - PSE15_0, PSE15_1, - PSE14_0, PSE14_1, - PSE13_0, PSE13_1, - PSE12_0, PSE12_1, - PSE11_0, PSE11_1, - PSE10_0, PSE10_1, - PSE9_0, PSE9_1, - PSE8_0, PSE8_1, - PSE7_0, PSE7_1, - PSE6_0, PSE6_1, - PSE5_0, PSE5_1, - PSE4_0, PSE4_1, - PSE3_0, PSE3_1, - PSE2_0, PSE2_1, - PSE1_0, PSE1_1, - PSE0_0, PSE0_1} - }, - {} -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { - PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, - PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } - }, - { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) { - PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, - PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } - }, - { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) { - PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, - PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA } - }, - { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { - PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, - PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } - }, - { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) { - PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, - PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA } - }, - { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) { - PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, - PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } - }, - { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) { - 0, 0, PTG5_DATA, PTG4_DATA, - PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } - }, - { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) { - PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, - PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } - }, - { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) { - PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0, - PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } - }, - { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) { - PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, - PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } - }, - { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) { - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, - PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } - }, - { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) { - PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, - PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } - }, - { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) { - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, - PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } - }, - { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) { - PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, - PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } - }, - { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) { - PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, - PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } - }, - { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) { - 0, PTS6_DATA, PTS5_DATA, PTS4_DATA, - PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } - }, - { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) { - PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA, - PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } - }, - { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) { - PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, - PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } - }, - { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) { - PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, - PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } - }, - { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) { - PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, - PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } - }, - { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) { - PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, - PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } - }, - { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) { - PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, - PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } - }, - { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) { - PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, - PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } - }, - { }, -}; - -static struct pinmux_info sh7724_pinmux_info = { - .name = "sh7724_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_INTC_IRQ0, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), }; static int __init plat_pinmux_setup(void) { - return register_pinmux(&sh7724_pinmux_info); + return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources, + ARRAY_SIZE(sh7724_pfc_resources)); } arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c new file mode 100644 index 00000000000..ea2db632a76 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c @@ -0,0 +1,35 @@ +/* + * SH7734 processor support - PFC hardware block + * + * Copyright (C) 2012 Renesas Solutions Corp. + * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/bug.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/ioport.h> +#include <cpu/pfc.h> + +static struct resource sh7734_pfc_resources[] = { + [0] = { /* PFC */ + .start = 0xFFFC0000, + .end = 0xFFFC011C, + .flags = IORESOURCE_MEM, + }, + [1] = { /* GPIO */ + .start = 0xFFC40000, + .end = 0xFFC4502B, + .flags = IORESOURCE_MEM, + } +}; + +static int __init plat_pinmux_setup(void) +{ + return sh_pfc_register("pfc-sh7734", sh7734_pfc_resources, + ARRAY_SIZE(sh7734_pfc_resources)); +} +arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c new file mode 100644 index 00000000000..567745d4422 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c @@ -0,0 +1,35 @@ +/* + * SH7757 (B0 step) Pinmux + * + * Copyright (C) 2009-2010 Renesas Solutions Corp. + * + * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * Based on SH7723 Pinmux + * Copyright (C) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/bug.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/ioport.h> +#include <cpu/pfc.h> + +static struct resource sh7757_pfc_resources[] = { + [0] = { + .start = 0xffec0000, + .end = 0xffec008f, + .flags = IORESOURCE_MEM, + }, +}; + +static int __init plat_pinmux_setup(void) +{ + return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources, + ARRAY_SIZE(sh7757_pfc_resources)); +} +arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c index 5ebc25fd9b2..e336ab8b512 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c @@ -8,1303 +8,23 @@ * for more details. */ +#include <linux/bug.h> #include <linux/init.h> #include <linux/kernel.h> -#include <linux/gpio.h> -#include <cpu/sh7785.h> +#include <linux/ioport.h> +#include <cpu/pfc.h> -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, - PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, - PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, - PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, - PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, - PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, - PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, - PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, - PE5_DATA, PE4_DATA, PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, - PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, - PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, - PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, - PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, - PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, - PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, - PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, - PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA, - PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA, - PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA, - PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA, - PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA, - PM1_DATA, PM0_DATA, - PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA, - PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA, - PP5_DATA, PP4_DATA, PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA, - PQ4_DATA, PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA, - PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA, - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - PA7_IN, PA6_IN, PA5_IN, PA4_IN, - PA3_IN, PA2_IN, PA1_IN, PA0_IN, - PB7_IN, PB6_IN, PB5_IN, PB4_IN, - PB3_IN, PB2_IN, PB1_IN, PB0_IN, - PC7_IN, PC6_IN, PC5_IN, PC4_IN, - PC3_IN, PC2_IN, PC1_IN, PC0_IN, - PD7_IN, PD6_IN, PD5_IN, PD4_IN, - PD3_IN, PD2_IN, PD1_IN, PD0_IN, - PE5_IN, PE4_IN, PE3_IN, PE2_IN, PE1_IN, PE0_IN, - PF7_IN, PF6_IN, PF5_IN, PF4_IN, - PF3_IN, PF2_IN, PF1_IN, PF0_IN, - PG7_IN, PG6_IN, PG5_IN, PG4_IN, - PG3_IN, PG2_IN, PG1_IN, PG0_IN, - PH7_IN, PH6_IN, PH5_IN, PH4_IN, - PH3_IN, PH2_IN, PH1_IN, PH0_IN, - PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN, - PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN, - PK7_IN, PK6_IN, PK5_IN, PK4_IN, - PK3_IN, PK2_IN, PK1_IN, PK0_IN, - PL7_IN, PL6_IN, PL5_IN, PL4_IN, - PL3_IN, PL2_IN, PL1_IN, PL0_IN, - PM1_IN, PM0_IN, - PN7_IN, PN6_IN, PN5_IN, PN4_IN, - PN3_IN, PN2_IN, PN1_IN, PN0_IN, - PP5_IN, PP4_IN, PP3_IN, PP2_IN, PP1_IN, PP0_IN, - PQ4_IN, PQ3_IN, PQ2_IN, PQ1_IN, PQ0_IN, - PR3_IN, PR2_IN, PR1_IN, PR0_IN, - PINMUX_INPUT_END, - - PINMUX_INPUT_PULLUP_BEGIN, - PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, - PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, - PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, - PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, - PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, - PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, - PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, - PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, - PE5_IN_PU, PE4_IN_PU, PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU, - PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, - PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, - PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU, - PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU, - PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU, - PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, - PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU, - PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU, PJ0_IN_PU, - PK7_IN_PU, PK6_IN_PU, PK5_IN_PU, PK4_IN_PU, - PK3_IN_PU, PK2_IN_PU, PK1_IN_PU, PK0_IN_PU, - PL7_IN_PU, PL6_IN_PU, PL5_IN_PU, PL4_IN_PU, - PL3_IN_PU, PL2_IN_PU, PL1_IN_PU, PL0_IN_PU, - PM1_IN_PU, PM0_IN_PU, - PN7_IN_PU, PN6_IN_PU, PN5_IN_PU, PN4_IN_PU, - PN3_IN_PU, PN2_IN_PU, PN1_IN_PU, PN0_IN_PU, - PP5_IN_PU, PP4_IN_PU, PP3_IN_PU, PP2_IN_PU, PP1_IN_PU, PP0_IN_PU, - PQ4_IN_PU, PQ3_IN_PU, PQ2_IN_PU, PQ1_IN_PU, PQ0_IN_PU, - PR3_IN_PU, PR2_IN_PU, PR1_IN_PU, PR0_IN_PU, - PINMUX_INPUT_PULLUP_END, - - PINMUX_OUTPUT_BEGIN, - PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, - PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, - PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, - PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT, - PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, - PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, - PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, - PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, - PE5_OUT, PE4_OUT, PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT, - PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, - PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, - PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT, - PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT, - PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT, - PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT, - PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT, - PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT, - PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT, - PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT, - PL7_OUT, PL6_OUT, PL5_OUT, PL4_OUT, - PL3_OUT, PL2_OUT, PL1_OUT, PL0_OUT, - PM1_OUT, PM0_OUT, - PN7_OUT, PN6_OUT, PN5_OUT, PN4_OUT, - PN3_OUT, PN2_OUT, PN1_OUT, PN0_OUT, - PP5_OUT, PP4_OUT, PP3_OUT, PP2_OUT, PP1_OUT, PP0_OUT, - PQ4_OUT, PQ3_OUT, PQ2_OUT, PQ1_OUT, PQ0_OUT, - PR3_OUT, PR2_OUT, PR1_OUT, PR0_OUT, - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - PA7_FN, PA6_FN, PA5_FN, PA4_FN, - PA3_FN, PA2_FN, PA1_FN, PA0_FN, - PB7_FN, PB6_FN, PB5_FN, PB4_FN, - PB3_FN, PB2_FN, PB1_FN, PB0_FN, - PC7_FN, PC6_FN, PC5_FN, PC4_FN, - PC3_FN, PC2_FN, PC1_FN, PC0_FN, - PD7_FN, PD6_FN, PD5_FN, PD4_FN, - PD3_FN, PD2_FN, PD1_FN, PD0_FN, - PE5_FN, PE4_FN, PE3_FN, PE2_FN, PE1_FN, PE0_FN, - PF7_FN, PF6_FN, PF5_FN, PF4_FN, - PF3_FN, PF2_FN, PF1_FN, PF0_FN, - PG7_FN, PG6_FN, PG5_FN, PG4_FN, - PG3_FN, PG2_FN, PG1_FN, PG0_FN, - PH7_FN, PH6_FN, PH5_FN, PH4_FN, - PH3_FN, PH2_FN, PH1_FN, PH0_FN, - PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN, - PJ3_FN, PJ2_FN, PJ1_FN, PJ0_FN, - PK7_FN, PK6_FN, PK5_FN, PK4_FN, - PK3_FN, PK2_FN, PK1_FN, PK0_FN, - PL7_FN, PL6_FN, PL5_FN, PL4_FN, - PL3_FN, PL2_FN, PL1_FN, PL0_FN, - PM1_FN, PM0_FN, - PN7_FN, PN6_FN, PN5_FN, PN4_FN, - PN3_FN, PN2_FN, PN1_FN, PN0_FN, - PP5_FN, PP4_FN, PP3_FN, PP2_FN, PP1_FN, PP0_FN, - PQ4_FN, PQ3_FN, PQ2_FN, PQ1_FN, PQ0_FN, - PR3_FN, PR2_FN, PR1_FN, PR0_FN, - P1MSEL15_0, P1MSEL15_1, - P1MSEL14_0, P1MSEL14_1, - P1MSEL13_0, P1MSEL13_1, - P1MSEL12_0, P1MSEL12_1, - P1MSEL11_0, P1MSEL11_1, - P1MSEL10_0, P1MSEL10_1, - P1MSEL9_0, P1MSEL9_1, - P1MSEL8_0, P1MSEL8_1, - P1MSEL7_0, P1MSEL7_1, - P1MSEL6_0, P1MSEL6_1, - P1MSEL5_0, - P1MSEL4_0, P1MSEL4_1, - P1MSEL3_0, P1MSEL3_1, - P1MSEL2_0, P1MSEL2_1, - P1MSEL1_0, P1MSEL1_1, - P1MSEL0_0, P1MSEL0_1, - P2MSEL2_0, P2MSEL2_1, - P2MSEL1_0, P2MSEL1_1, - P2MSEL0_0, P2MSEL0_1, - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - D63_AD31_MARK, - D62_AD30_MARK, - D61_AD29_MARK, - D60_AD28_MARK, - D59_AD27_MARK, - D58_AD26_MARK, - D57_AD25_MARK, - D56_AD24_MARK, - D55_AD23_MARK, - D54_AD22_MARK, - D53_AD21_MARK, - D52_AD20_MARK, - D51_AD19_MARK, - D50_AD18_MARK, - D49_AD17_DB5_MARK, - D48_AD16_DB4_MARK, - D47_AD15_DB3_MARK, - D46_AD14_DB2_MARK, - D45_AD13_DB1_MARK, - D44_AD12_DB0_MARK, - D43_AD11_DG5_MARK, - D42_AD10_DG4_MARK, - D41_AD9_DG3_MARK, - D40_AD8_DG2_MARK, - D39_AD7_DG1_MARK, - D38_AD6_DG0_MARK, - D37_AD5_DR5_MARK, - D36_AD4_DR4_MARK, - D35_AD3_DR3_MARK, - D34_AD2_DR2_MARK, - D33_AD1_DR1_MARK, - D32_AD0_DR0_MARK, - REQ1_MARK, - REQ2_MARK, - REQ3_MARK, - GNT1_MARK, - GNT2_MARK, - GNT3_MARK, - MMCCLK_MARK, - D31_MARK, - D30_MARK, - D29_MARK, - D28_MARK, - D27_MARK, - D26_MARK, - D25_MARK, - D24_MARK, - D23_MARK, - D22_MARK, - D21_MARK, - D20_MARK, - D19_MARK, - D18_MARK, - D17_MARK, - D16_MARK, - SCIF1_SCK_MARK, - SCIF1_RXD_MARK, - SCIF1_TXD_MARK, - SCIF0_CTS_MARK, - INTD_MARK, - FCE_MARK, - SCIF0_RTS_MARK, - HSPI_CS_MARK, - FSE_MARK, - SCIF0_SCK_MARK, - HSPI_CLK_MARK, - FRE_MARK, - SCIF0_RXD_MARK, - HSPI_RX_MARK, - FRB_MARK, - SCIF0_TXD_MARK, - HSPI_TX_MARK, - FWE_MARK, - SCIF5_TXD_MARK, - HAC1_SYNC_MARK, - SSI1_WS_MARK, - SIOF_TXD_PJ_MARK, - HAC0_SDOUT_MARK, - SSI0_SDATA_MARK, - SIOF_RXD_PJ_MARK, - HAC0_SDIN_MARK, - SSI0_SCK_MARK, - SIOF_SYNC_PJ_MARK, - HAC0_SYNC_MARK, - SSI0_WS_MARK, - SIOF_MCLK_PJ_MARK, - HAC_RES_MARK, - SIOF_SCK_PJ_MARK, - HAC0_BITCLK_MARK, - SSI0_CLK_MARK, - HAC1_BITCLK_MARK, - SSI1_CLK_MARK, - TCLK_MARK, - IOIS16_MARK, - STATUS0_MARK, - DRAK0_PK3_MARK, - STATUS1_MARK, - DRAK1_PK2_MARK, - DACK2_MARK, - SCIF2_TXD_MARK, - MMCCMD_MARK, - SIOF_TXD_PK_MARK, - DACK3_MARK, - SCIF2_SCK_MARK, - MMCDAT_MARK, - SIOF_SCK_PK_MARK, - DREQ0_MARK, - DREQ1_MARK, - DRAK0_PK1_MARK, - DRAK1_PK0_MARK, - DREQ2_MARK, - INTB_MARK, - DREQ3_MARK, - INTC_MARK, - DRAK2_MARK, - CE2A_MARK, - IRL4_MARK, - FD4_MARK, - IRL5_MARK, - FD5_MARK, - IRL6_MARK, - FD6_MARK, - IRL7_MARK, - FD7_MARK, - DRAK3_MARK, - CE2B_MARK, - BREQ_BSACK_MARK, - BACK_BSREQ_MARK, - SCIF5_RXD_MARK, - HAC1_SDIN_MARK, - SSI1_SCK_MARK, - SCIF5_SCK_MARK, - HAC1_SDOUT_MARK, - SSI1_SDATA_MARK, - SCIF3_TXD_MARK, - FCLE_MARK, - SCIF3_RXD_MARK, - FALE_MARK, - SCIF3_SCK_MARK, - FD0_MARK, - SCIF4_TXD_MARK, - FD1_MARK, - SCIF4_RXD_MARK, - FD2_MARK, - SCIF4_SCK_MARK, - FD3_MARK, - DEVSEL_DCLKOUT_MARK, - STOP_CDE_MARK, - LOCK_ODDF_MARK, - TRDY_DISPL_MARK, - IRDY_HSYNC_MARK, - PCIFRAME_VSYNC_MARK, - INTA_MARK, - GNT0_GNTIN_MARK, - REQ0_REQOUT_MARK, - PERR_MARK, - SERR_MARK, - WE7_CBE3_MARK, - WE6_CBE2_MARK, - WE5_CBE1_MARK, - WE4_CBE0_MARK, - SCIF2_RXD_MARK, - SIOF_RXD_MARK, - MRESETOUT_MARK, - IRQOUT_MARK, - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - - /* PA GPIO */ - PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), - PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), - PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), - PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), - PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), - PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), - PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), - PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), - - /* PB GPIO */ - PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), - PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), - PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), - PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), - PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), - PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), - PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), - PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), - - /* PC GPIO */ - PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), - PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), - PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), - PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), - PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), - PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), - PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), - PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), - - /* PD GPIO */ - PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), - PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), - PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), - PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), - PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), - PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), - PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), - PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), - - /* PE GPIO */ - PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU), - PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU), - PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU), - PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU), - PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU), - PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU), - - /* PF GPIO */ - PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), - PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), - PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), - PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), - PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), - PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), - PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), - PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), - - /* PG GPIO */ - PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), - PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), - PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), - PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU), - PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU), - PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU), - PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU), - PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU), - - /* PH GPIO */ - PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU), - PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU), - PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), - PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), - PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), - PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), - PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), - PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), - - /* PJ GPIO */ - PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU), - PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU), - PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU), - PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU), - PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU), - PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU), - PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU), - PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT, PJ0_IN_PU), - - /* PK GPIO */ - PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT, PK7_IN_PU), - PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT, PK6_IN_PU), - PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT, PK5_IN_PU), - PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT, PK4_IN_PU), - PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT, PK3_IN_PU), - PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT, PK2_IN_PU), - PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT, PK1_IN_PU), - PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT, PK0_IN_PU), - - /* PL GPIO */ - PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT, PL7_IN_PU), - PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT, PL6_IN_PU), - PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT, PL5_IN_PU), - PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT, PL4_IN_PU), - PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT, PL3_IN_PU), - PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT, PL2_IN_PU), - PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT, PL1_IN_PU), - PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT, PL0_IN_PU), - - /* PM GPIO */ - PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT, PM1_IN_PU), - PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT, PM0_IN_PU), - - /* PN GPIO */ - PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT, PN7_IN_PU), - PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT, PN6_IN_PU), - PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT, PN5_IN_PU), - PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT, PN4_IN_PU), - PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT, PN3_IN_PU), - PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT, PN2_IN_PU), - PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT, PN1_IN_PU), - PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT, PN0_IN_PU), - - /* PP GPIO */ - PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT, PP5_IN_PU), - PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT, PP4_IN_PU), - PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT, PP3_IN_PU), - PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT, PP2_IN_PU), - PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT, PP1_IN_PU), - PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT, PP0_IN_PU), - - /* PQ GPIO */ - PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT, PQ4_IN_PU), - PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT, PQ3_IN_PU), - PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT, PQ2_IN_PU), - PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT, PQ1_IN_PU), - PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT, PQ0_IN_PU), - - /* PR GPIO */ - PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT, PR3_IN_PU), - PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT, PR2_IN_PU), - PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT, PR1_IN_PU), - PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT, PR0_IN_PU), - - /* PA FN */ - PINMUX_DATA(D63_AD31_MARK, PA7_FN), - PINMUX_DATA(D62_AD30_MARK, PA6_FN), - PINMUX_DATA(D61_AD29_MARK, PA5_FN), - PINMUX_DATA(D60_AD28_MARK, PA4_FN), - PINMUX_DATA(D59_AD27_MARK, PA3_FN), - PINMUX_DATA(D58_AD26_MARK, PA2_FN), - PINMUX_DATA(D57_AD25_MARK, PA1_FN), - PINMUX_DATA(D56_AD24_MARK, PA0_FN), - - /* PB FN */ - PINMUX_DATA(D55_AD23_MARK, PB7_FN), - PINMUX_DATA(D54_AD22_MARK, PB6_FN), - PINMUX_DATA(D53_AD21_MARK, PB5_FN), - PINMUX_DATA(D52_AD20_MARK, PB4_FN), - PINMUX_DATA(D51_AD19_MARK, PB3_FN), - PINMUX_DATA(D50_AD18_MARK, PB2_FN), - PINMUX_DATA(D49_AD17_DB5_MARK, PB1_FN), - PINMUX_DATA(D48_AD16_DB4_MARK, PB0_FN), - - /* PC FN */ - PINMUX_DATA(D47_AD15_DB3_MARK, PC7_FN), - PINMUX_DATA(D46_AD14_DB2_MARK, PC6_FN), - PINMUX_DATA(D45_AD13_DB1_MARK, PC5_FN), - PINMUX_DATA(D44_AD12_DB0_MARK, PC4_FN), - PINMUX_DATA(D43_AD11_DG5_MARK, PC3_FN), - PINMUX_DATA(D42_AD10_DG4_MARK, PC2_FN), - PINMUX_DATA(D41_AD9_DG3_MARK, PC1_FN), - PINMUX_DATA(D40_AD8_DG2_MARK, PC0_FN), - - /* PD FN */ - PINMUX_DATA(D39_AD7_DG1_MARK, PD7_FN), - PINMUX_DATA(D38_AD6_DG0_MARK, PD6_FN), - PINMUX_DATA(D37_AD5_DR5_MARK, PD5_FN), - PINMUX_DATA(D36_AD4_DR4_MARK, PD4_FN), - PINMUX_DATA(D35_AD3_DR3_MARK, PD3_FN), - PINMUX_DATA(D34_AD2_DR2_MARK, PD2_FN), - PINMUX_DATA(D33_AD1_DR1_MARK, PD1_FN), - PINMUX_DATA(D32_AD0_DR0_MARK, PD0_FN), - - /* PE FN */ - PINMUX_DATA(REQ1_MARK, PE5_FN), - PINMUX_DATA(REQ2_MARK, PE4_FN), - PINMUX_DATA(REQ3_MARK, P2MSEL0_0, PE3_FN), - PINMUX_DATA(GNT1_MARK, PE2_FN), - PINMUX_DATA(GNT2_MARK, PE1_FN), - PINMUX_DATA(GNT3_MARK, P2MSEL0_0, PE0_FN), - PINMUX_DATA(MMCCLK_MARK, P2MSEL0_1, PE0_FN), - - /* PF FN */ - PINMUX_DATA(D31_MARK, PF7_FN), - PINMUX_DATA(D30_MARK, PF6_FN), - PINMUX_DATA(D29_MARK, PF5_FN), - PINMUX_DATA(D28_MARK, PF4_FN), - PINMUX_DATA(D27_MARK, PF3_FN), - PINMUX_DATA(D26_MARK, PF2_FN), - PINMUX_DATA(D25_MARK, PF1_FN), - PINMUX_DATA(D24_MARK, PF0_FN), - - /* PF FN */ - PINMUX_DATA(D23_MARK, PG7_FN), - PINMUX_DATA(D22_MARK, PG6_FN), - PINMUX_DATA(D21_MARK, PG5_FN), - PINMUX_DATA(D20_MARK, PG4_FN), - PINMUX_DATA(D19_MARK, PG3_FN), - PINMUX_DATA(D18_MARK, PG2_FN), - PINMUX_DATA(D17_MARK, PG1_FN), - PINMUX_DATA(D16_MARK, PG0_FN), - - /* PH FN */ - PINMUX_DATA(SCIF1_SCK_MARK, PH7_FN), - PINMUX_DATA(SCIF1_RXD_MARK, PH6_FN), - PINMUX_DATA(SCIF1_TXD_MARK, PH5_FN), - PINMUX_DATA(SCIF0_CTS_MARK, PH4_FN), - PINMUX_DATA(INTD_MARK, P1MSEL7_1, PH4_FN), - PINMUX_DATA(FCE_MARK, P1MSEL8_1, P1MSEL7_0, PH4_FN), - PINMUX_DATA(SCIF0_RTS_MARK, P1MSEL8_0, P1MSEL7_0, PH3_FN), - PINMUX_DATA(HSPI_CS_MARK, P1MSEL8_0, P1MSEL7_1, PH3_FN), - PINMUX_DATA(FSE_MARK, P1MSEL8_1, P1MSEL7_0, PH3_FN), - PINMUX_DATA(SCIF0_SCK_MARK, P1MSEL8_0, P1MSEL7_0, PH2_FN), - PINMUX_DATA(HSPI_CLK_MARK, P1MSEL8_0, P1MSEL7_1, PH2_FN), - PINMUX_DATA(FRE_MARK, P1MSEL8_1, P1MSEL7_0, PH2_FN), - PINMUX_DATA(SCIF0_RXD_MARK, P1MSEL8_0, P1MSEL7_0, PH1_FN), - PINMUX_DATA(HSPI_RX_MARK, P1MSEL8_0, P1MSEL7_1, PH1_FN), - PINMUX_DATA(FRB_MARK, P1MSEL8_1, P1MSEL7_0, PH1_FN), - PINMUX_DATA(SCIF0_TXD_MARK, P1MSEL8_0, P1MSEL7_0, PH0_FN), - PINMUX_DATA(HSPI_TX_MARK, P1MSEL8_0, P1MSEL7_1, PH0_FN), - PINMUX_DATA(FWE_MARK, P1MSEL8_1, P1MSEL7_0, PH0_FN), - - /* PJ FN */ - PINMUX_DATA(SCIF5_TXD_MARK, P1MSEL2_0, P1MSEL1_0, PJ7_FN), - PINMUX_DATA(HAC1_SYNC_MARK, P1MSEL2_0, P1MSEL1_1, PJ7_FN), - PINMUX_DATA(SSI1_WS_MARK, P1MSEL2_1, P1MSEL1_0, PJ7_FN), - PINMUX_DATA(SIOF_TXD_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ6_FN), - PINMUX_DATA(HAC0_SDOUT_MARK, P1MSEL4_0, P1MSEL3_1, PJ6_FN), - PINMUX_DATA(SSI0_SDATA_MARK, P1MSEL4_1, P1MSEL3_0, PJ6_FN), - PINMUX_DATA(SIOF_RXD_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ5_FN), - PINMUX_DATA(HAC0_SDIN_MARK, P1MSEL4_0, P1MSEL3_1, PJ5_FN), - PINMUX_DATA(SSI0_SCK_MARK, P1MSEL4_1, P1MSEL3_0, PJ5_FN), - PINMUX_DATA(SIOF_SYNC_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ4_FN), - PINMUX_DATA(HAC0_SYNC_MARK, P1MSEL4_0, P1MSEL3_1, PJ4_FN), - PINMUX_DATA(SSI0_WS_MARK, P1MSEL4_1, P1MSEL3_0, PJ4_FN), - PINMUX_DATA(SIOF_MCLK_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ3_FN), - PINMUX_DATA(HAC_RES_MARK, P1MSEL4_0, P1MSEL3_1, PJ3_FN), - PINMUX_DATA(SIOF_SCK_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ2_FN), - PINMUX_DATA(HAC0_BITCLK_MARK, P1MSEL4_0, P1MSEL3_1, PJ2_FN), - PINMUX_DATA(SSI0_CLK_MARK, P1MSEL4_1, P1MSEL3_0, PJ2_FN), - PINMUX_DATA(HAC1_BITCLK_MARK, P1MSEL2_0, PJ1_FN), - PINMUX_DATA(SSI1_CLK_MARK, P1MSEL2_1, P1MSEL1_0, PJ1_FN), - PINMUX_DATA(TCLK_MARK, P1MSEL9_0, PJ0_FN), - PINMUX_DATA(IOIS16_MARK, P1MSEL9_1, PJ0_FN), - - /* PK FN */ - PINMUX_DATA(STATUS0_MARK, P1MSEL15_0, PK7_FN), - PINMUX_DATA(DRAK0_PK3_MARK, P1MSEL15_1, PK7_FN), - PINMUX_DATA(STATUS1_MARK, P1MSEL15_0, PK6_FN), - PINMUX_DATA(DRAK1_PK2_MARK, P1MSEL15_1, PK6_FN), - PINMUX_DATA(DACK2_MARK, P1MSEL12_0, P1MSEL11_0, PK5_FN), - PINMUX_DATA(SCIF2_TXD_MARK, P1MSEL12_1, P1MSEL11_0, PK5_FN), - PINMUX_DATA(MMCCMD_MARK, P1MSEL12_1, P1MSEL11_1, PK5_FN), - PINMUX_DATA(SIOF_TXD_PK_MARK, P2MSEL1_1, - P1MSEL12_0, P1MSEL11_1, PK5_FN), - PINMUX_DATA(DACK3_MARK, P1MSEL12_0, P1MSEL11_0, PK4_FN), - PINMUX_DATA(SCIF2_SCK_MARK, P1MSEL12_1, P1MSEL11_0, PK4_FN), - PINMUX_DATA(MMCDAT_MARK, P1MSEL12_1, P1MSEL11_1, PK4_FN), - PINMUX_DATA(SIOF_SCK_PK_MARK, P2MSEL1_1, - P1MSEL12_0, P1MSEL11_1, PK4_FN), - PINMUX_DATA(DREQ0_MARK, PK3_FN), - PINMUX_DATA(DREQ1_MARK, PK2_FN), - PINMUX_DATA(DRAK0_PK1_MARK, PK1_FN), - PINMUX_DATA(DRAK1_PK0_MARK, PK0_FN), - - /* PL FN */ - PINMUX_DATA(DREQ2_MARK, P1MSEL13_0, PL7_FN), - PINMUX_DATA(INTB_MARK, P1MSEL13_1, PL7_FN), - PINMUX_DATA(DREQ3_MARK, P1MSEL13_0, PL6_FN), - PINMUX_DATA(INTC_MARK, P1MSEL13_1, PL6_FN), - PINMUX_DATA(DRAK2_MARK, P1MSEL10_0, PL5_FN), - PINMUX_DATA(CE2A_MARK, P1MSEL10_1, PL5_FN), - PINMUX_DATA(IRL4_MARK, P1MSEL14_0, PL4_FN), - PINMUX_DATA(FD4_MARK, P1MSEL14_1, PL4_FN), - PINMUX_DATA(IRL5_MARK, P1MSEL14_0, PL3_FN), - PINMUX_DATA(FD5_MARK, P1MSEL14_1, PL3_FN), - PINMUX_DATA(IRL6_MARK, P1MSEL14_0, PL2_FN), - PINMUX_DATA(FD6_MARK, P1MSEL14_1, PL2_FN), - PINMUX_DATA(IRL7_MARK, P1MSEL14_0, PL1_FN), - PINMUX_DATA(FD7_MARK, P1MSEL14_1, PL1_FN), - PINMUX_DATA(DRAK3_MARK, P1MSEL10_0, PL0_FN), - PINMUX_DATA(CE2B_MARK, P1MSEL10_1, PL0_FN), - - /* PM FN */ - PINMUX_DATA(BREQ_BSACK_MARK, PM1_FN), - PINMUX_DATA(BACK_BSREQ_MARK, PM0_FN), - - /* PN FN */ - PINMUX_DATA(SCIF5_RXD_MARK, P1MSEL2_0, P1MSEL1_0, PN7_FN), - PINMUX_DATA(HAC1_SDIN_MARK, P1MSEL2_0, P1MSEL1_1, PN7_FN), - PINMUX_DATA(SSI1_SCK_MARK, P1MSEL2_1, P1MSEL1_0, PN7_FN), - PINMUX_DATA(SCIF5_SCK_MARK, P1MSEL2_0, P1MSEL1_0, PN6_FN), - PINMUX_DATA(HAC1_SDOUT_MARK, P1MSEL2_0, P1MSEL1_1, PN6_FN), - PINMUX_DATA(SSI1_SDATA_MARK, P1MSEL2_1, P1MSEL1_0, PN6_FN), - PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL0_0, PN5_FN), - PINMUX_DATA(FCLE_MARK, P1MSEL0_1, PN5_FN), - PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL0_0, PN4_FN), - PINMUX_DATA(FALE_MARK, P1MSEL0_1, PN4_FN), - PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL0_0, PN3_FN), - PINMUX_DATA(FD0_MARK, P1MSEL0_1, PN3_FN), - PINMUX_DATA(SCIF4_TXD_MARK, P1MSEL0_0, PN2_FN), - PINMUX_DATA(FD1_MARK, P1MSEL0_1, PN2_FN), - PINMUX_DATA(SCIF4_RXD_MARK, P1MSEL0_0, PN1_FN), - PINMUX_DATA(FD2_MARK, P1MSEL0_1, PN1_FN), - PINMUX_DATA(SCIF4_SCK_MARK, P1MSEL0_0, PN0_FN), - PINMUX_DATA(FD3_MARK, P1MSEL0_1, PN0_FN), - - /* PP FN */ - PINMUX_DATA(DEVSEL_DCLKOUT_MARK, PP5_FN), - PINMUX_DATA(STOP_CDE_MARK, PP4_FN), - PINMUX_DATA(LOCK_ODDF_MARK, PP3_FN), - PINMUX_DATA(TRDY_DISPL_MARK, PP2_FN), - PINMUX_DATA(IRDY_HSYNC_MARK, PP1_FN), - PINMUX_DATA(PCIFRAME_VSYNC_MARK, PP0_FN), - - /* PQ FN */ - PINMUX_DATA(INTA_MARK, PQ4_FN), - PINMUX_DATA(GNT0_GNTIN_MARK, PQ3_FN), - PINMUX_DATA(REQ0_REQOUT_MARK, PQ2_FN), - PINMUX_DATA(PERR_MARK, PQ1_FN), - PINMUX_DATA(SERR_MARK, PQ0_FN), - - /* PR FN */ - PINMUX_DATA(WE7_CBE3_MARK, PR3_FN), - PINMUX_DATA(WE6_CBE2_MARK, PR2_FN), - PINMUX_DATA(WE5_CBE1_MARK, PR1_FN), - PINMUX_DATA(WE4_CBE0_MARK, PR0_FN), - - /* MISC FN */ - PINMUX_DATA(SCIF2_RXD_MARK, P1MSEL6_0, P1MSEL5_0), - PINMUX_DATA(SIOF_RXD_MARK, P2MSEL1_1, P1MSEL6_1, P1MSEL5_0), - PINMUX_DATA(MRESETOUT_MARK, P2MSEL2_0), - PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - /* PA */ - PINMUX_GPIO(GPIO_PA7, PA7_DATA), - PINMUX_GPIO(GPIO_PA6, PA6_DATA), - PINMUX_GPIO(GPIO_PA5, PA5_DATA), - PINMUX_GPIO(GPIO_PA4, PA4_DATA), - PINMUX_GPIO(GPIO_PA3, PA3_DATA), - PINMUX_GPIO(GPIO_PA2, PA2_DATA), - PINMUX_GPIO(GPIO_PA1, PA1_DATA), - PINMUX_GPIO(GPIO_PA0, PA0_DATA), - - /* PB */ - PINMUX_GPIO(GPIO_PB7, PB7_DATA), - PINMUX_GPIO(GPIO_PB6, PB6_DATA), - PINMUX_GPIO(GPIO_PB5, PB5_DATA), - PINMUX_GPIO(GPIO_PB4, PB4_DATA), - PINMUX_GPIO(GPIO_PB3, PB3_DATA), - PINMUX_GPIO(GPIO_PB2, PB2_DATA), - PINMUX_GPIO(GPIO_PB1, PB1_DATA), - PINMUX_GPIO(GPIO_PB0, PB0_DATA), - - /* PC */ - PINMUX_GPIO(GPIO_PC7, PC7_DATA), - PINMUX_GPIO(GPIO_PC6, PC6_DATA), - PINMUX_GPIO(GPIO_PC5, PC5_DATA), - PINMUX_GPIO(GPIO_PC4, PC4_DATA), - PINMUX_GPIO(GPIO_PC3, PC3_DATA), - PINMUX_GPIO(GPIO_PC2, PC2_DATA), - PINMUX_GPIO(GPIO_PC1, PC1_DATA), - PINMUX_GPIO(GPIO_PC0, PC0_DATA), - - /* PD */ - PINMUX_GPIO(GPIO_PD7, PD7_DATA), - PINMUX_GPIO(GPIO_PD6, PD6_DATA), - PINMUX_GPIO(GPIO_PD5, PD5_DATA), - PINMUX_GPIO(GPIO_PD4, PD4_DATA), - PINMUX_GPIO(GPIO_PD3, PD3_DATA), - PINMUX_GPIO(GPIO_PD2, PD2_DATA), - PINMUX_GPIO(GPIO_PD1, PD1_DATA), - PINMUX_GPIO(GPIO_PD0, PD0_DATA), - - /* PE */ - PINMUX_GPIO(GPIO_PE5, PE5_DATA), - PINMUX_GPIO(GPIO_PE4, PE4_DATA), - PINMUX_GPIO(GPIO_PE3, PE3_DATA), - PINMUX_GPIO(GPIO_PE2, PE2_DATA), - PINMUX_GPIO(GPIO_PE1, PE1_DATA), - PINMUX_GPIO(GPIO_PE0, PE0_DATA), - - /* PF */ - PINMUX_GPIO(GPIO_PF7, PF7_DATA), - PINMUX_GPIO(GPIO_PF6, PF6_DATA), - PINMUX_GPIO(GPIO_PF5, PF5_DATA), - PINMUX_GPIO(GPIO_PF4, PF4_DATA), - PINMUX_GPIO(GPIO_PF3, PF3_DATA), - PINMUX_GPIO(GPIO_PF2, PF2_DATA), - PINMUX_GPIO(GPIO_PF1, PF1_DATA), - PINMUX_GPIO(GPIO_PF0, PF0_DATA), - - /* PG */ - PINMUX_GPIO(GPIO_PG7, PG7_DATA), - PINMUX_GPIO(GPIO_PG6, PG6_DATA), - PINMUX_GPIO(GPIO_PG5, PG5_DATA), - PINMUX_GPIO(GPIO_PG4, PG4_DATA), - PINMUX_GPIO(GPIO_PG3, PG3_DATA), - PINMUX_GPIO(GPIO_PG2, PG2_DATA), - PINMUX_GPIO(GPIO_PG1, PG1_DATA), - PINMUX_GPIO(GPIO_PG0, PG0_DATA), - - /* PH */ - PINMUX_GPIO(GPIO_PH7, PH7_DATA), - PINMUX_GPIO(GPIO_PH6, PH6_DATA), - PINMUX_GPIO(GPIO_PH5, PH5_DATA), - PINMUX_GPIO(GPIO_PH4, PH4_DATA), - PINMUX_GPIO(GPIO_PH3, PH3_DATA), - PINMUX_GPIO(GPIO_PH2, PH2_DATA), - PINMUX_GPIO(GPIO_PH1, PH1_DATA), - PINMUX_GPIO(GPIO_PH0, PH0_DATA), - - /* PJ */ - PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), - PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), - PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), - PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), - PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), - PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), - PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), - PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), - - /* PK */ - PINMUX_GPIO(GPIO_PK7, PK7_DATA), - PINMUX_GPIO(GPIO_PK6, PK6_DATA), - PINMUX_GPIO(GPIO_PK5, PK5_DATA), - PINMUX_GPIO(GPIO_PK4, PK4_DATA), - PINMUX_GPIO(GPIO_PK3, PK3_DATA), - PINMUX_GPIO(GPIO_PK2, PK2_DATA), - PINMUX_GPIO(GPIO_PK1, PK1_DATA), - PINMUX_GPIO(GPIO_PK0, PK0_DATA), - - /* PL */ - PINMUX_GPIO(GPIO_PL7, PL7_DATA), - PINMUX_GPIO(GPIO_PL6, PL6_DATA), - PINMUX_GPIO(GPIO_PL5, PL5_DATA), - PINMUX_GPIO(GPIO_PL4, PL4_DATA), - PINMUX_GPIO(GPIO_PL3, PL3_DATA), - PINMUX_GPIO(GPIO_PL2, PL2_DATA), - PINMUX_GPIO(GPIO_PL1, PL1_DATA), - PINMUX_GPIO(GPIO_PL0, PL0_DATA), - - /* PM */ - PINMUX_GPIO(GPIO_PM1, PM1_DATA), - PINMUX_GPIO(GPIO_PM0, PM0_DATA), - - /* PN */ - PINMUX_GPIO(GPIO_PN7, PN7_DATA), - PINMUX_GPIO(GPIO_PN6, PN6_DATA), - PINMUX_GPIO(GPIO_PN5, PN5_DATA), - PINMUX_GPIO(GPIO_PN4, PN4_DATA), - PINMUX_GPIO(GPIO_PN3, PN3_DATA), - PINMUX_GPIO(GPIO_PN2, PN2_DATA), - PINMUX_GPIO(GPIO_PN1, PN1_DATA), - PINMUX_GPIO(GPIO_PN0, PN0_DATA), - - /* PP */ - PINMUX_GPIO(GPIO_PP5, PP5_DATA), - PINMUX_GPIO(GPIO_PP4, PP4_DATA), - PINMUX_GPIO(GPIO_PP3, PP3_DATA), - PINMUX_GPIO(GPIO_PP2, PP2_DATA), - PINMUX_GPIO(GPIO_PP1, PP1_DATA), - PINMUX_GPIO(GPIO_PP0, PP0_DATA), - - /* PQ */ - PINMUX_GPIO(GPIO_PQ4, PQ4_DATA), - PINMUX_GPIO(GPIO_PQ3, PQ3_DATA), - PINMUX_GPIO(GPIO_PQ2, PQ2_DATA), - PINMUX_GPIO(GPIO_PQ1, PQ1_DATA), - PINMUX_GPIO(GPIO_PQ0, PQ0_DATA), - - /* PR */ - PINMUX_GPIO(GPIO_PR3, PR3_DATA), - PINMUX_GPIO(GPIO_PR2, PR2_DATA), - PINMUX_GPIO(GPIO_PR1, PR1_DATA), - PINMUX_GPIO(GPIO_PR0, PR0_DATA), - - /* FN */ - PINMUX_GPIO(GPIO_FN_D63_AD31, D63_AD31_MARK), - PINMUX_GPIO(GPIO_FN_D62_AD30, D62_AD30_MARK), - PINMUX_GPIO(GPIO_FN_D61_AD29, D61_AD29_MARK), - PINMUX_GPIO(GPIO_FN_D60_AD28, D60_AD28_MARK), - PINMUX_GPIO(GPIO_FN_D59_AD27, D59_AD27_MARK), - PINMUX_GPIO(GPIO_FN_D58_AD26, D58_AD26_MARK), - PINMUX_GPIO(GPIO_FN_D57_AD25, D57_AD25_MARK), - PINMUX_GPIO(GPIO_FN_D56_AD24, D56_AD24_MARK), - PINMUX_GPIO(GPIO_FN_D55_AD23, D55_AD23_MARK), - PINMUX_GPIO(GPIO_FN_D54_AD22, D54_AD22_MARK), - PINMUX_GPIO(GPIO_FN_D53_AD21, D53_AD21_MARK), - PINMUX_GPIO(GPIO_FN_D52_AD20, D52_AD20_MARK), - PINMUX_GPIO(GPIO_FN_D51_AD19, D51_AD19_MARK), - PINMUX_GPIO(GPIO_FN_D50_AD18, D50_AD18_MARK), - PINMUX_GPIO(GPIO_FN_D49_AD17_DB5, D49_AD17_DB5_MARK), - PINMUX_GPIO(GPIO_FN_D48_AD16_DB4, D48_AD16_DB4_MARK), - PINMUX_GPIO(GPIO_FN_D47_AD15_DB3, D47_AD15_DB3_MARK), - PINMUX_GPIO(GPIO_FN_D46_AD14_DB2, D46_AD14_DB2_MARK), - PINMUX_GPIO(GPIO_FN_D45_AD13_DB1, D45_AD13_DB1_MARK), - PINMUX_GPIO(GPIO_FN_D44_AD12_DB0, D44_AD12_DB0_MARK), - PINMUX_GPIO(GPIO_FN_D43_AD11_DG5, D43_AD11_DG5_MARK), - PINMUX_GPIO(GPIO_FN_D42_AD10_DG4, D42_AD10_DG4_MARK), - PINMUX_GPIO(GPIO_FN_D41_AD9_DG3, D41_AD9_DG3_MARK), - PINMUX_GPIO(GPIO_FN_D40_AD8_DG2, D40_AD8_DG2_MARK), - PINMUX_GPIO(GPIO_FN_D39_AD7_DG1, D39_AD7_DG1_MARK), - PINMUX_GPIO(GPIO_FN_D38_AD6_DG0, D38_AD6_DG0_MARK), - PINMUX_GPIO(GPIO_FN_D37_AD5_DR5, D37_AD5_DR5_MARK), - PINMUX_GPIO(GPIO_FN_D36_AD4_DR4, D36_AD4_DR4_MARK), - PINMUX_GPIO(GPIO_FN_D35_AD3_DR3, D35_AD3_DR3_MARK), - PINMUX_GPIO(GPIO_FN_D34_AD2_DR2, D34_AD2_DR2_MARK), - PINMUX_GPIO(GPIO_FN_D33_AD1_DR1, D33_AD1_DR1_MARK), - PINMUX_GPIO(GPIO_FN_D32_AD0_DR0, D32_AD0_DR0_MARK), - PINMUX_GPIO(GPIO_FN_REQ1, REQ1_MARK), - PINMUX_GPIO(GPIO_FN_REQ2, REQ2_MARK), - PINMUX_GPIO(GPIO_FN_REQ3, REQ3_MARK), - PINMUX_GPIO(GPIO_FN_GNT1, GNT1_MARK), - PINMUX_GPIO(GPIO_FN_GNT2, GNT2_MARK), - PINMUX_GPIO(GPIO_FN_GNT3, GNT3_MARK), - PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_INTD, INTD_MARK), - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), - PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), - PINMUX_GPIO(GPIO_FN_FRE, FRE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_TXD_PJ, SIOF_TXD_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_RXD_PJ, SIOF_RXD_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_SYNC_PJ, SIOF_SYNC_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_MCLK_PJ, SIOF_MCLK_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_SCK_PJ, SIOF_SCK_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0_PK3, DRAK0_PK3_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1_PK2, DRAK1_PK2_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_TXD_PK, SIOF_TXD_PK_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT, MMCDAT_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_SCK_PK, SIOF_SCK_PK_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0_PK1, DRAK0_PK1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1_PK0, DRAK1_PK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_INTB, INTB_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), - PINMUX_GPIO(GPIO_FN_INTC, INTC_MARK), - PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), - PINMUX_GPIO(GPIO_FN_FD4, FD4_MARK), - PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), - PINMUX_GPIO(GPIO_FN_FD5, FD5_MARK), - PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), - PINMUX_GPIO(GPIO_FN_FD6, FD6_MARK), - PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), - PINMUX_GPIO(GPIO_FN_FD7, FD7_MARK), - PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_BREQ_BSACK, BREQ_BSACK_MARK), - PINMUX_GPIO(GPIO_FN_BACK_BSREQ, BACK_BSREQ_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), - PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), - PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FD0, FD0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), - PINMUX_GPIO(GPIO_FN_FD1, FD1_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), - PINMUX_GPIO(GPIO_FN_FD2, FD2_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FD3, FD3_MARK), - PINMUX_GPIO(GPIO_FN_DEVSEL_DCLKOUT, DEVSEL_DCLKOUT_MARK), - PINMUX_GPIO(GPIO_FN_STOP_CDE, STOP_CDE_MARK), - PINMUX_GPIO(GPIO_FN_LOCK_ODDF, LOCK_ODDF_MARK), - PINMUX_GPIO(GPIO_FN_TRDY_DISPL, TRDY_DISPL_MARK), - PINMUX_GPIO(GPIO_FN_IRDY_HSYNC, IRDY_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_PCIFRAME_VSYNC, PCIFRAME_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_INTA, INTA_MARK), - PINMUX_GPIO(GPIO_FN_GNT0_GNTIN, GNT0_GNTIN_MARK), - PINMUX_GPIO(GPIO_FN_REQ0_REQOUT, REQ0_REQOUT_MARK), - PINMUX_GPIO(GPIO_FN_PERR, PERR_MARK), - PINMUX_GPIO(GPIO_FN_SERR, SERR_MARK), - PINMUX_GPIO(GPIO_FN_WE7_CBE3, WE7_CBE3_MARK), - PINMUX_GPIO(GPIO_FN_WE6_CBE2, WE6_CBE2_MARK), - PINMUX_GPIO(GPIO_FN_WE5_CBE1, WE5_CBE1_MARK), - PINMUX_GPIO(GPIO_FN_WE4_CBE0, WE4_CBE0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_RXD, SIOF_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MRESETOUT, MRESETOUT_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) { - PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, - PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, - PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, - PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, - PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, - PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, - PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, - PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU } - }, - { PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) { - PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, - PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, - PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, - PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, - PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, - PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, - PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, - PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU } - }, - { PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2) { - PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, - PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, - PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, - PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, - PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, - PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, - PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, - PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU } - }, - { PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2) { - PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, - PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, - PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, - PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, - PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, - PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, - PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, - PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU } - }, - { PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU, - PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU, - PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU, - PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU, - PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU, - PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU } - }, - { PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2) { - PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, - PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, - PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, - PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, - PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, - PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, - PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, - PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU } - }, - { PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2) { - PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, - PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, - PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, - PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU, - PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU, - PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU, - PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU, - PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU } - }, - { PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2) { - PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU, - PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU, - PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, - PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, - PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, - PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, - PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, - PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU } - }, - { PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2) { - PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU, - PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU, - PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU, - PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU, - PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU, - PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU, - PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU, - PJ0_FN, PJ0_OUT, PJ0_IN, PJ0_IN_PU } - }, - { PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2) { - PK7_FN, PK7_OUT, PK7_IN, PK7_IN_PU, - PK6_FN, PK6_OUT, PK6_IN, PK6_IN_PU, - PK5_FN, PK5_OUT, PK5_IN, PK5_IN_PU, - PK4_FN, PK4_OUT, PK4_IN, PK4_IN_PU, - PK3_FN, PK3_OUT, PK3_IN, PK3_IN_PU, - PK2_FN, PK2_OUT, PK2_IN, PK2_IN_PU, - PK1_FN, PK1_OUT, PK1_IN, PK1_IN_PU, - PK0_FN, PK0_OUT, PK0_IN, PK0_IN_PU } - }, - { PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2) { - PL7_FN, PL7_OUT, PL7_IN, PL7_IN_PU, - PL6_FN, PL6_OUT, PL6_IN, PL6_IN_PU, - PL5_FN, PL5_OUT, PL5_IN, PL5_IN_PU, - PL4_FN, PL4_OUT, PL4_IN, PL4_IN_PU, - PL3_FN, PL3_OUT, PL3_IN, PL3_IN_PU, - PL2_FN, PL2_OUT, PL2_IN, PL2_IN_PU, - PL1_FN, PL1_OUT, PL1_IN, PL1_IN_PU, - PL0_FN, PL0_OUT, PL0_IN, PL0_IN_PU } - }, - { PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - PM1_FN, PM1_OUT, PM1_IN, PM1_IN_PU, - PM0_FN, PM0_OUT, PM0_IN, PM0_IN_PU } - }, - { PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2) { - PN7_FN, PN7_OUT, PN7_IN, PN7_IN_PU, - PN6_FN, PN6_OUT, PN6_IN, PN6_IN_PU, - PN5_FN, PN5_OUT, PN5_IN, PN5_IN_PU, - PN4_FN, PN4_OUT, PN4_IN, PN4_IN_PU, - PN3_FN, PN3_OUT, PN3_IN, PN3_IN_PU, - PN2_FN, PN2_OUT, PN2_IN, PN2_IN_PU, - PN1_FN, PN1_OUT, PN1_IN, PN1_IN_PU, - PN0_FN, PN0_OUT, PN0_IN, PN0_IN_PU } - }, - { PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - PP5_FN, PP5_OUT, PP5_IN, PP5_IN_PU, - PP4_FN, PP4_OUT, PP4_IN, PP4_IN_PU, - PP3_FN, PP3_OUT, PP3_IN, PP3_IN_PU, - PP2_FN, PP2_OUT, PP2_IN, PP2_IN_PU, - PP1_FN, PP1_OUT, PP1_IN, PP1_IN_PU, - PP0_FN, PP0_OUT, PP0_IN, PP0_IN_PU } - }, - { PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - PQ4_FN, PQ4_OUT, PQ4_IN, PQ4_IN_PU, - PQ3_FN, PQ3_OUT, PQ3_IN, PQ3_IN_PU, - PQ2_FN, PQ2_OUT, PQ2_IN, PQ2_IN_PU, - PQ1_FN, PQ1_OUT, PQ1_IN, PQ1_IN_PU, - PQ0_FN, PQ0_OUT, PQ0_IN, PQ0_IN_PU } - }, - { PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - PR3_FN, PR3_OUT, PR3_IN, PR3_IN_PU, - PR2_FN, PR2_OUT, PR2_IN, PR2_IN_PU, - PR1_FN, PR1_OUT, PR1_IN, PR1_IN_PU, - PR0_FN, PR0_OUT, PR0_IN, PR0_IN_PU } - }, - { PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1) { - P1MSEL15_0, P1MSEL15_1, - P1MSEL14_0, P1MSEL14_1, - P1MSEL13_0, P1MSEL13_1, - P1MSEL12_0, P1MSEL12_1, - P1MSEL11_0, P1MSEL11_1, - P1MSEL10_0, P1MSEL10_1, - P1MSEL9_0, P1MSEL9_1, - P1MSEL8_0, P1MSEL8_1, - P1MSEL7_0, P1MSEL7_1, - P1MSEL6_0, P1MSEL6_1, - P1MSEL5_0, 0, - P1MSEL4_0, P1MSEL4_1, - P1MSEL3_0, P1MSEL3_1, - P1MSEL2_0, P1MSEL2_1, - P1MSEL1_0, P1MSEL1_1, - P1MSEL0_0, P1MSEL0_1 } +static struct resource sh7785_pfc_resources[] = { + [0] = { + .start = 0xffe70000, + .end = 0xffe7008f, + .flags = IORESOURCE_MEM, }, - { PINMUX_CFG_REG("P2MSELR", 0xffe70082, 16, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - P2MSEL2_0, P2MSEL2_1, - P2MSEL1_0, P2MSEL1_1, - P2MSEL0_0, P2MSEL0_1 } - }, - {} -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("PADR", 0xffe70020, 8) { - PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, - PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } - }, - { PINMUX_DATA_REG("PBDR", 0xffe70022, 8) { - PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, - PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA } - }, - { PINMUX_DATA_REG("PCDR", 0xffe70024, 8) { - PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, - PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } - }, - { PINMUX_DATA_REG("PDDR", 0xffe70026, 8) { - PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, - PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } - }, - { PINMUX_DATA_REG("PEDR", 0xffe70028, 8) { - 0, 0, PE5_DATA, PE4_DATA, - PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } - }, - { PINMUX_DATA_REG("PFDR", 0xffe7002a, 8) { - PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, - PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } - }, - { PINMUX_DATA_REG("PGDR", 0xffe7002c, 8) { - PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, - PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA } - }, - { PINMUX_DATA_REG("PHDR", 0xffe7002e, 8) { - PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, - PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA } - }, - { PINMUX_DATA_REG("PJDR", 0xffe70030, 8) { - PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, - PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA } - }, - { PINMUX_DATA_REG("PKDR", 0xffe70032, 8) { - PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA, - PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA } - }, - { PINMUX_DATA_REG("PLDR", 0xffe70034, 8) { - PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA, - PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA } - }, - { PINMUX_DATA_REG("PMDR", 0xffe70036, 8) { - 0, 0, 0, 0, - 0, 0, PM1_DATA, PM0_DATA } - }, - { PINMUX_DATA_REG("PNDR", 0xffe70038, 8) { - PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA, - PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA } - }, - { PINMUX_DATA_REG("PPDR", 0xffe7003a, 8) { - 0, 0, PP5_DATA, PP4_DATA, - PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA } - }, - { PINMUX_DATA_REG("PQDR", 0xffe7003c, 8) { - 0, 0, 0, PQ4_DATA, - PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA } - }, - { PINMUX_DATA_REG("PRDR", 0xffe7003e, 8) { - 0, 0, 0, 0, - PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA } - }, - { }, -}; - -static struct pinmux_info sh7785_pinmux_info = { - .name = "sh7785_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_IRQOUT, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), }; static int __init plat_pinmux_setup(void) { - return register_pinmux(&sh7785_pinmux_info); + return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources, + ARRAY_SIZE(sh7785_pfc_resources)); } - arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c index 4229e0724c8..9a459556a2f 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c @@ -13,831 +13,23 @@ * for more details. */ +#include <linux/bug.h> #include <linux/init.h> #include <linux/kernel.h> -#include <linux/gpio.h> -#include <cpu/sh7786.h> +#include <linux/ioport.h> +#include <cpu/pfc.h> -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, - PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, - PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, - PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, - PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, - PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, - PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, - PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, - PE7_DATA, PE6_DATA, - PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, - PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, - PG7_DATA, PG6_DATA, PG5_DATA, - PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, - PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, - PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, - PJ3_DATA, PJ2_DATA, PJ1_DATA, - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - PA7_IN, PA6_IN, PA5_IN, PA4_IN, - PA3_IN, PA2_IN, PA1_IN, PA0_IN, - PB7_IN, PB6_IN, PB5_IN, PB4_IN, - PB3_IN, PB2_IN, PB1_IN, PB0_IN, - PC7_IN, PC6_IN, PC5_IN, PC4_IN, - PC3_IN, PC2_IN, PC1_IN, PC0_IN, - PD7_IN, PD6_IN, PD5_IN, PD4_IN, - PD3_IN, PD2_IN, PD1_IN, PD0_IN, - PE7_IN, PE6_IN, - PF7_IN, PF6_IN, PF5_IN, PF4_IN, - PF3_IN, PF2_IN, PF1_IN, PF0_IN, - PG7_IN, PG6_IN, PG5_IN, - PH7_IN, PH6_IN, PH5_IN, PH4_IN, - PH3_IN, PH2_IN, PH1_IN, PH0_IN, - PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN, - PJ3_IN, PJ2_IN, PJ1_IN, - PINMUX_INPUT_END, - - PINMUX_INPUT_PULLUP_BEGIN, - PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, - PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, - PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, - PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, - PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, - PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, - PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, - PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, - PE7_IN_PU, PE6_IN_PU, - PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, - PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, - PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, - PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU, - PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, - PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU, - PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU, - PINMUX_INPUT_PULLUP_END, - - PINMUX_OUTPUT_BEGIN, - PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, - PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, - PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, - PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT, - PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, - PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, - PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, - PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, - PE7_OUT, PE6_OUT, - PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, - PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, - PG7_OUT, PG6_OUT, PG5_OUT, - PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT, - PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT, - PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT, - PJ3_OUT, PJ2_OUT, PJ1_OUT, - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - PA7_FN, PA6_FN, PA5_FN, PA4_FN, - PA3_FN, PA2_FN, PA1_FN, PA0_FN, - PB7_FN, PB6_FN, PB5_FN, PB4_FN, - PB3_FN, PB2_FN, PB1_FN, PB0_FN, - PC7_FN, PC6_FN, PC5_FN, PC4_FN, - PC3_FN, PC2_FN, PC1_FN, PC0_FN, - PD7_FN, PD6_FN, PD5_FN, PD4_FN, - PD3_FN, PD2_FN, PD1_FN, PD0_FN, - PE7_FN, PE6_FN, - PF7_FN, PF6_FN, PF5_FN, PF4_FN, - PF3_FN, PF2_FN, PF1_FN, PF0_FN, - PG7_FN, PG6_FN, PG5_FN, - PH7_FN, PH6_FN, PH5_FN, PH4_FN, - PH3_FN, PH2_FN, PH1_FN, PH0_FN, - PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN, - PJ3_FN, PJ2_FN, PJ1_FN, - P1MSEL14_0, P1MSEL14_1, - P1MSEL13_0, P1MSEL13_1, - P1MSEL12_0, P1MSEL12_1, - P1MSEL11_0, P1MSEL11_1, - P1MSEL10_0, P1MSEL10_1, - P1MSEL9_0, P1MSEL9_1, - P1MSEL8_0, P1MSEL8_1, - P1MSEL7_0, P1MSEL7_1, - P1MSEL6_0, P1MSEL6_1, - P1MSEL5_0, P1MSEL5_1, - P1MSEL4_0, P1MSEL4_1, - P1MSEL3_0, P1MSEL3_1, - P1MSEL2_0, P1MSEL2_1, - P1MSEL1_0, P1MSEL1_1, - P1MSEL0_0, P1MSEL0_1, - - P2MSEL15_0, P2MSEL15_1, - P2MSEL14_0, P2MSEL14_1, - P2MSEL13_0, P2MSEL13_1, - P2MSEL12_0, P2MSEL12_1, - P2MSEL11_0, P2MSEL11_1, - P2MSEL10_0, P2MSEL10_1, - P2MSEL9_0, P2MSEL9_1, - P2MSEL8_0, P2MSEL8_1, - P2MSEL7_0, P2MSEL7_1, - P2MSEL6_0, P2MSEL6_1, - P2MSEL5_0, P2MSEL5_1, - P2MSEL4_0, P2MSEL4_1, - P2MSEL3_0, P2MSEL3_1, - P2MSEL2_0, P2MSEL2_1, - P2MSEL1_0, P2MSEL1_1, - P2MSEL0_0, P2MSEL0_1, - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK, - VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK, - DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK, - DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK, - DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK, - ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK, - ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK, - ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK, - ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK, - ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK, - HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK, - SCIF0_CTS_MARK, SCIF0_RTS_MARK, - SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK, - SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK, - SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK, - SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK, - SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK, - BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK, - FALE_MARK, FRB_MARK, FSTATUS_MARK, - FSE_MARK, FCLE_MARK, - DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK, - DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK, - DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK, - USB_OVC1_MARK, USB_OVC0_MARK, - USB_PENC1_MARK, USB_PENC0_MARK, - HAC_RES_MARK, - HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK, - HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK, - SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK, - SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK, - SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK, - SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK, - SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK, - SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK, - SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK, - SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK, - TCLK_MARK, - IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK, - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - - /* PA GPIO */ - PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), - PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), - PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), - PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), - PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), - PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), - PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), - PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), - - /* PB GPIO */ - PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), - PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), - PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), - PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), - PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), - PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), - PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), - PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), - - /* PC GPIO */ - PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), - PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), - PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), - PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), - PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), - PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), - PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), - PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), - - /* PD GPIO */ - PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), - PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), - PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), - PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), - PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), - PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), - PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), - PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), - - /* PE GPIO */ - PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU), - PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU), - - /* PF GPIO */ - PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), - PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), - PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), - PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), - PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), - PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), - PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), - PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), - - /* PG GPIO */ - PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), - PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), - PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), - - /* PH GPIO */ - PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU), - PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU), - PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), - PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), - PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), - PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), - PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), - PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), - - /* PJ GPIO */ - PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU), - PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU), - PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU), - PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU), - PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU), - PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU), - PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU), - - /* PA FN */ - PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN), - PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN), - PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN), - PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN), - PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN), - PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN), - PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN), - PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN), - PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN), - PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN), - PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN), - PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN), - PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN), - PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN), - PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN), - PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN), - - /* PB FN */ - PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN), - PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN), - PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN), - PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN), - PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN), - PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN), - PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN), - PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN), - PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN), - PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN), - PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN), - PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN), - PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN), - PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN), - PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN), - PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN), - - /* PC FN */ - PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN), - PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN), - PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN), - PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN), - PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN), - PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN), - PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN), - PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN), - - PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN), - PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN), - PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN), - PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN), - PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN), - PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN), - PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN), - PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN), - - /* PD FN */ - PINMUX_DATA(DCLKOUT_MARK, PD7_FN), - PINMUX_DATA(SCIF1_SCK_MARK, PD6_FN), - PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN), - PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN), - PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN), - PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN), - PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN), - PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN), - PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN), - PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN), - PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN), - PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN), - PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN), - PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN), - - /* PE FN */ - PINMUX_DATA(USB_PENC1_MARK, PE7_FN), - PINMUX_DATA(USB_PENC0_MARK, PE6_FN), - - /* PF FN */ - PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN), - PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN), - PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN), - PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN), - PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN), - PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN), - PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN), - PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN), - PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN), - PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN), - PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN), - PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN), - PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN), - PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN), - PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN), - PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN), - PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN), - PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN), - PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN), - PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN), - PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN), - PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN), - PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN), - PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN), - - /* PG FN */ - PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN), - PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN), - PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN), - PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN), - PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN), - PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN), - PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN), - PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN), - - /* PH FN */ - PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN), - PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN), - PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN), - PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN), - PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN), - PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN), - PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN), - PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN), - PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN), - PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN), - PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN), - PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN), - PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN), - PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN), - PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN), - PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN), - PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN), - PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN), - PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN), - PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN), - PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN), - - /* PJ FN */ - PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN), - PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN), - PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN), - PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN), - PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN), - PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN), - PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN), - PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN), - PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN), - PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN), - PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN), - PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN), - PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN), - PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN), - PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN), - PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN), - PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN), - PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN), - PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - /* PA */ - PINMUX_GPIO(GPIO_PA7, PA7_DATA), - PINMUX_GPIO(GPIO_PA6, PA6_DATA), - PINMUX_GPIO(GPIO_PA5, PA5_DATA), - PINMUX_GPIO(GPIO_PA4, PA4_DATA), - PINMUX_GPIO(GPIO_PA3, PA3_DATA), - PINMUX_GPIO(GPIO_PA2, PA2_DATA), - PINMUX_GPIO(GPIO_PA1, PA1_DATA), - PINMUX_GPIO(GPIO_PA0, PA0_DATA), - - /* PB */ - PINMUX_GPIO(GPIO_PB7, PB7_DATA), - PINMUX_GPIO(GPIO_PB6, PB6_DATA), - PINMUX_GPIO(GPIO_PB5, PB5_DATA), - PINMUX_GPIO(GPIO_PB4, PB4_DATA), - PINMUX_GPIO(GPIO_PB3, PB3_DATA), - PINMUX_GPIO(GPIO_PB2, PB2_DATA), - PINMUX_GPIO(GPIO_PB1, PB1_DATA), - PINMUX_GPIO(GPIO_PB0, PB0_DATA), - - /* PC */ - PINMUX_GPIO(GPIO_PC7, PC7_DATA), - PINMUX_GPIO(GPIO_PC6, PC6_DATA), - PINMUX_GPIO(GPIO_PC5, PC5_DATA), - PINMUX_GPIO(GPIO_PC4, PC4_DATA), - PINMUX_GPIO(GPIO_PC3, PC3_DATA), - PINMUX_GPIO(GPIO_PC2, PC2_DATA), - PINMUX_GPIO(GPIO_PC1, PC1_DATA), - PINMUX_GPIO(GPIO_PC0, PC0_DATA), - - /* PD */ - PINMUX_GPIO(GPIO_PD7, PD7_DATA), - PINMUX_GPIO(GPIO_PD6, PD6_DATA), - PINMUX_GPIO(GPIO_PD5, PD5_DATA), - PINMUX_GPIO(GPIO_PD4, PD4_DATA), - PINMUX_GPIO(GPIO_PD3, PD3_DATA), - PINMUX_GPIO(GPIO_PD2, PD2_DATA), - PINMUX_GPIO(GPIO_PD1, PD1_DATA), - PINMUX_GPIO(GPIO_PD0, PD0_DATA), - - /* PE */ - PINMUX_GPIO(GPIO_PE5, PE7_DATA), - PINMUX_GPIO(GPIO_PE4, PE6_DATA), - - /* PF */ - PINMUX_GPIO(GPIO_PF7, PF7_DATA), - PINMUX_GPIO(GPIO_PF6, PF6_DATA), - PINMUX_GPIO(GPIO_PF5, PF5_DATA), - PINMUX_GPIO(GPIO_PF4, PF4_DATA), - PINMUX_GPIO(GPIO_PF3, PF3_DATA), - PINMUX_GPIO(GPIO_PF2, PF2_DATA), - PINMUX_GPIO(GPIO_PF1, PF1_DATA), - PINMUX_GPIO(GPIO_PF0, PF0_DATA), - - /* PG */ - PINMUX_GPIO(GPIO_PG7, PG7_DATA), - PINMUX_GPIO(GPIO_PG6, PG6_DATA), - PINMUX_GPIO(GPIO_PG5, PG5_DATA), - - /* PH */ - PINMUX_GPIO(GPIO_PH7, PH7_DATA), - PINMUX_GPIO(GPIO_PH6, PH6_DATA), - PINMUX_GPIO(GPIO_PH5, PH5_DATA), - PINMUX_GPIO(GPIO_PH4, PH4_DATA), - PINMUX_GPIO(GPIO_PH3, PH3_DATA), - PINMUX_GPIO(GPIO_PH2, PH2_DATA), - PINMUX_GPIO(GPIO_PH1, PH1_DATA), - PINMUX_GPIO(GPIO_PH0, PH0_DATA), - - /* PJ */ - PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), - PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), - PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), - PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), - PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), - PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), - PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), - - /* FN */ - PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK), - PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK), - PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK), - PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK), - PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK), - PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK), - PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK), - PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), - PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), - PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK), - PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK), - PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK), - PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK), - PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK), - PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK), - PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK), - PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK), - PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), - PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), - PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK), - PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK), - PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK), - PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK), - PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK), - PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK), - PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), - PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), - PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), - PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), - PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), - PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), - PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) { - PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, - PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, - PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, - PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, - PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, - PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, - PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, - PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU } - }, - { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) { - PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, - PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, - PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, - PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, - PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, - PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, - PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, - PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU } - }, - { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) { - PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, - PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, - PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, - PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, - PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, - PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, - PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, - PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU } - }, - { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) { - PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, - PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, - PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, - PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, - PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, - PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, - PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, - PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU } - }, - { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) { - PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU, - PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, } - }, - { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) { - PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, - PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, - PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, - PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, - PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, - PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, - PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, - PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU } - }, - { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) { - PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, - PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, - PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, } - }, - { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) { - PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU, - PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU, - PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, - PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, - PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, - PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, - PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, - PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU } - }, - { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) { - PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU, - PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU, - PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU, - PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU, - PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU, - PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU, - PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU, - 0, 0, 0, 0, } - }, - { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) { - 0, 0, - P1MSEL14_0, P1MSEL14_1, - P1MSEL13_0, P1MSEL13_1, - P1MSEL12_0, P1MSEL12_1, - P1MSEL11_0, P1MSEL11_1, - P1MSEL10_0, P1MSEL10_1, - P1MSEL9_0, P1MSEL9_1, - P1MSEL8_0, P1MSEL8_1, - P1MSEL7_0, P1MSEL7_1, - P1MSEL6_0, P1MSEL6_1, - P1MSEL5_0, P1MSEL5_1, - P1MSEL4_0, P1MSEL4_1, - P1MSEL3_0, P1MSEL3_1, - P1MSEL2_0, P1MSEL2_1, - P1MSEL1_0, P1MSEL1_1, - P1MSEL0_0, P1MSEL0_1 } - }, - { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) { - P2MSEL15_0, P2MSEL15_1, - P2MSEL14_0, P2MSEL14_1, - P2MSEL13_0, P2MSEL13_1, - P2MSEL12_0, P2MSEL12_1, - P2MSEL11_0, P2MSEL11_1, - P2MSEL10_0, P2MSEL10_1, - P2MSEL9_0, P2MSEL9_1, - P2MSEL8_0, P2MSEL8_1, - P2MSEL7_0, P2MSEL7_1, - P2MSEL6_0, P2MSEL6_1, - P2MSEL5_0, P2MSEL5_1, - P2MSEL4_0, P2MSEL4_1, - P2MSEL3_0, P2MSEL3_1, - P2MSEL2_0, P2MSEL2_1, - P2MSEL1_0, P2MSEL1_1, - P2MSEL0_0, P2MSEL0_1 } +static struct resource sh7786_pfc_resources[] = { + [0] = { + .start = 0xffcc0000, + .end = 0xffcc008f, + .flags = IORESOURCE_MEM, }, - {} -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) { - PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, - PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } - }, - { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) { - PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, - PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA } - }, - { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) { - PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, - PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } - }, - { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) { - PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, - PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } - }, - { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) { - PE7_DATA, PE6_DATA, - 0, 0, 0, 0, 0, 0 } - }, - { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) { - PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, - PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } - }, - { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) { - PG7_DATA, PG6_DATA, PG5_DATA, 0, - 0, 0, 0, 0 } - }, - { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) { - PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, - PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA } - }, - { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) { - PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, - PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 } - }, - { }, -}; - -static struct pinmux_info sh7786_pinmux_info = { - .name = "sh7786_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_FSE, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), }; static int __init plat_pinmux_setup(void) { - return register_pinmux(&sh7786_pinmux_info); + return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources, + ARRAY_SIZE(sh7786_pfc_resources)); } - arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c new file mode 100644 index 00000000000..444bf25c60f --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c @@ -0,0 +1,29 @@ +/* + * SH-X3 prototype CPU pinmux + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/bug.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/ioport.h> +#include <cpu/pfc.h> + +static struct resource shx3_pfc_resources[] = { + [0] = { + .start = 0xffc70000, + .end = 0xffc7001f, + .flags = IORESOURCE_MEM, + }, +}; + +static int __init plat_pinmux_setup(void) +{ + return sh_pfc_register("pfc-shx3", shx3_pfc_resources, + ARRAY_SIZE(shx3_pfc_resources)); +} +arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/serial-sh7722.c b/arch/sh/kernel/cpu/sh4a/serial-sh7722.c new file mode 100644 index 00000000000..59bc3a72702 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/serial-sh7722.c @@ -0,0 +1,23 @@ +#include <linux/serial_sci.h> +#include <linux/serial_core.h> +#include <linux/io.h> + +#define PSCR 0xA405011E + +static void sh7722_sci_init_pins(struct uart_port *port, unsigned int cflag) +{ + unsigned short data; + + if (port->mapbase == 0xffe00000) { + data = __raw_readw(PSCR); + data &= ~0x03cf; + if (!(cflag & CRTSCTS)) + data |= 0x0340; + + __raw_writew(data, PSCR); + } +} + +struct plat_sci_port_ops sh7722_sci_port_ops = { + .init_pins = sh7722_sci_init_pins, +}; diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 6307e087c86..ceb3dedad98 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c @@ -13,8 +13,94 @@ #include <linux/serial_sci.h> #include <linux/uio_driver.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> #include <asm/clock.h> +/* Serial */ +static struct plat_sci_port scif0_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .type = PORT_SCIF, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .type = PORT_SCIF, +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc20)), +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .type = PORT_SCIF, +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe20000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc40)), +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .type = PORT_SCIF, +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xffe30000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc60)), +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + static struct resource iic0_resources[] = { [0] = { .name = "IIC0", @@ -23,8 +109,8 @@ static struct resource iic0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -44,8 +130,8 @@ static struct resource iic1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 44, - .end = 47, + .start = evt2irq(0x780), + .end = evt2irq(0x7e0), .flags = IORESOURCE_IRQ, }, }; @@ -60,7 +146,7 @@ static struct platform_device iic1_device = { static struct uio_info vpu_platform_data = { .name = "VPU4", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -88,7 +174,7 @@ static struct platform_device vpu_device = { static struct uio_info veu_platform_data = { .name = "VEU", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu_resources[] = { @@ -116,7 +202,7 @@ static struct platform_device veu_device = { static struct uio_info jpu_platform_data = { .name = "JPU", .version = "0", - .irq = 27, + .irq = evt2irq(0x560), }; static struct resource jpu_resources[] = { @@ -142,29 +228,16 @@ static struct platform_device jpu_device = { }; static struct sh_timer_config cmt_platform_data = { - .name = "CMT", - .channel_offset = 0x60, - .timer_bit = 5, - .clk = "cmt0", - .clockevent_rating = 125, - .clocksource_rating = 200, + .channels_mask = 0x20, }; static struct resource cmt_resources[] = { - [0] = { - .name = "CMT", - .start = 0x044a0060, - .end = 0x044a006b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 104, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0x044a0000, 0x70), + DEFINE_RES_IRQ(evt2irq(0xf00)), }; static struct platform_device cmt_device = { - .name = "sh_cmt", + .name = "sh-cmt-32", .id = 0, .dev = { .platform_data = &cmt_platform_data, @@ -174,28 +247,18 @@ static struct platform_device cmt_device = { }; static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "tmu0", - .clockevent_rating = 200, + .channels_mask = 7, }; static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 16, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0xffd80000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x400)), + DEFINE_RES_IRQ(evt2irq(0x420)), + DEFINE_RES_IRQ(evt2irq(0x440)), }; static struct platform_device tmu0_device = { - .name = "sh_tmu", + .name = "sh-tmu", .id = 0, .dev = { .platform_data = &tmu0_platform_data, @@ -204,113 +267,15 @@ static struct platform_device tmu0_device = { .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "tmu0", - .clocksource_rating = 200, -}; - -static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 17, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu1_device = { - .name = "sh_tmu", - .id = 1, - .dev = { - .platform_data = &tmu1_platform_data, - }, - .resource = tmu1_resources, - .num_resources = ARRAY_SIZE(tmu1_resources), -}; - -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "tmu0", -}; - -static struct resource tmu2_resources[] = { - [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 18, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu2_device = { - .name = "sh_tmu", - .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, - }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), -}; - -static struct plat_sci_port sci_platform_data[] = { - { - .mapbase = 0xffe00000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, - .clk = "scif0", - }, { - .mapbase = 0xffe10000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, - .clk = "scif1", - }, { - .mapbase = 0xffe20000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, - .clk = "scif2", - }, { - .mapbase = 0xffe30000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 83, 83, 83, 83 }, - .clk = "scif3", - }, { - .flags = 0, - } -}; - -static struct platform_device sci_device = { - .name = "sh-sci", - .id = -1, - .dev = { - .platform_data = sci_platform_data, - }, -}; - static struct platform_device *sh7343_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, &cmt_device, &tmu0_device, - &tmu1_device, - &tmu2_device, &iic0_device, &iic1_device, - &sci_device, &vpu_device, &veu_device, &jpu_device, @@ -325,13 +290,15 @@ static int __init sh7343_devices_setup(void) return platform_add_devices(sh7343_devices, ARRAY_SIZE(sh7343_devices)); } -__initcall(sh7343_devices_setup); +arch_initcall(sh7343_devices_setup); static struct platform_device *sh7343_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, &cmt_device, &tmu0_device, - &tmu1_device, - &tmu2_device, }; void __init plat_early_device_setup(void) @@ -342,6 +309,8 @@ void __init plat_early_device_setup(void) enum { UNUSED = 0, + ENABLED, + DISABLED, /* interrupt sources */ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, @@ -357,15 +326,13 @@ enum { I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, - IRDA, - SDHI0, SDHI1, SDHI2, SDHI3, - CMT, TSIF, SIU, + IRDA, SDHI, CMT, TSIF, SIU, TMU0, TMU1, TMU2, JPU, LCDC, /* interrupt groups */ - DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB, + DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB, }; static struct intc_vect vectors[] __initdata = { @@ -394,8 +361,8 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20), INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60), - INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), - INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), + INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), + INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), INTC_VECT(SIU, 0xf80), INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), @@ -413,7 +380,6 @@ static struct intc_group groups[] __initdata = { INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI), - INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), INTC_GROUP(USB, USBI0, USBI1), }; @@ -434,7 +400,7 @@ static struct intc_mask_reg mask_registers[] __initdata = { { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ - { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, + { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } }, { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ { 0, 0, 0, CMT, 0, USBI1, USBI0 } }, { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ @@ -470,9 +436,13 @@ static struct intc_mask_reg ack_registers[] __initdata = { { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; -static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups, - mask_registers, prio_registers, sense_registers, - ack_registers); +static struct intc_desc intc_desc __initdata = { + .name = "sh7343", + .force_enable = ENABLED, + .force_disable = DISABLED, + .hw = INTC_HW_DESC(vectors, groups, mask_registers, + prio_registers, sense_registers, ack_registers), +}; void __init plat_irq_setup(void) { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 318516f6bfa..f75f6734313 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c @@ -15,8 +15,32 @@ #include <linux/serial_sci.h> #include <linux/uio_driver.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> +#include <linux/usb/r8a66597.h> #include <asm/clock.h> +static struct plat_sci_port scif0_platform_data = { + .port_reg = 0xa405013e, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + static struct resource iic_resources[] = { [0] = { .name = "IIC", @@ -25,8 +49,8 @@ static struct resource iic_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -38,18 +62,20 @@ static struct platform_device iic_device = { .resource = iic_resources, }; +static struct r8a66597_platdata r8a66597_data = { + .on_chip = 1, +}; + static struct resource usb_host_resources[] = { [0] = { - .name = "r8a66597_hcd", .start = 0xa4d80000, .end = 0xa4d800ff, .flags = IORESOURCE_MEM, }, [1] = { - .name = "r8a66597_hcd", - .start = 65, - .end = 65, - .flags = IORESOURCE_IRQ, + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, }, }; @@ -59,6 +85,7 @@ static struct platform_device usb_host_device = { .dev = { .dma_mask = NULL, .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, }, .num_resources = ARRAY_SIZE(usb_host_resources), .resource = usb_host_resources, @@ -67,7 +94,7 @@ static struct platform_device usb_host_device = { static struct uio_info vpu_platform_data = { .name = "VPU5", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -95,7 +122,7 @@ static struct platform_device vpu_device = { static struct uio_info veu0_platform_data = { .name = "VEU", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu0_resources[] = { @@ -123,7 +150,7 @@ static struct platform_device veu0_device = { static struct uio_info veu1_platform_data = { .name = "VEU", .version = "0", - .irq = 27, + .irq = evt2irq(0x560), }; static struct resource veu1_resources[] = { @@ -149,29 +176,16 @@ static struct platform_device veu1_device = { }; static struct sh_timer_config cmt_platform_data = { - .name = "CMT", - .channel_offset = 0x60, - .timer_bit = 5, - .clk = "cmt0", - .clockevent_rating = 125, - .clocksource_rating = 200, + .channels_mask = 0x20, }; static struct resource cmt_resources[] = { - [0] = { - .name = "CMT", - .start = 0x044a0060, - .end = 0x044a006b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 104, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0x044a0000, 0x70), + DEFINE_RES_IRQ(evt2irq(0xf00)), }; static struct platform_device cmt_device = { - .name = "sh_cmt", + .name = "sh-cmt-32", .id = 0, .dev = { .platform_data = &cmt_platform_data, @@ -181,28 +195,18 @@ static struct platform_device cmt_device = { }; static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "tmu0", - .clockevent_rating = 200, + .channels_mask = 7, }; static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 16, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0xffd80000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x400)), + DEFINE_RES_IRQ(evt2irq(0x420)), + DEFINE_RES_IRQ(evt2irq(0x440)), }; static struct platform_device tmu0_device = { - .name = "sh_tmu", + .name = "sh-tmu", .id = 0, .dev = { .platform_data = &tmu0_platform_data, @@ -211,94 +215,11 @@ static struct platform_device tmu0_device = { .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "tmu0", - .clocksource_rating = 200, -}; - -static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 17, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu1_device = { - .name = "sh_tmu", - .id = 1, - .dev = { - .platform_data = &tmu1_platform_data, - }, - .resource = tmu1_resources, - .num_resources = ARRAY_SIZE(tmu1_resources), -}; - -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "tmu0", -}; - -static struct resource tmu2_resources[] = { - [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 18, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu2_device = { - .name = "sh_tmu", - .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, - }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), -}; - -static struct plat_sci_port sci_platform_data[] = { - { - .mapbase = 0xffe00000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, - .clk = "scif0", - }, { - .flags = 0, - } -}; - -static struct platform_device sci_device = { - .name = "sh-sci", - .id = -1, - .dev = { - .platform_data = sci_platform_data, - }, -}; - static struct platform_device *sh7366_devices[] __initdata = { + &scif0_device, &cmt_device, &tmu0_device, - &tmu1_device, - &tmu2_device, &iic_device, - &sci_device, &usb_host_device, &vpu_device, &veu0_device, @@ -314,13 +235,12 @@ static int __init sh7366_devices_setup(void) return platform_add_devices(sh7366_devices, ARRAY_SIZE(sh7366_devices)); } -__initcall(sh7366_devices_setup); +arch_initcall(sh7366_devices_setup); static struct platform_device *sh7366_early_devices[] __initdata = { + &scif0_device, &cmt_device, &tmu0_device, - &tmu1_device, - &tmu2_device, }; void __init plat_early_device_setup(void) @@ -331,6 +251,8 @@ void __init plat_early_device_setup(void) enum { UNUSED=0, + ENABLED, + DISABLED, /* interrupt sources */ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, @@ -344,14 +266,13 @@ enum { DENC, MSIOF, FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, - SDHI0, SDHI1, SDHI2, SDHI3, - CMT, TSIF, SIU, + SDHI, CMT, TSIF, SIU, TMU0, TMU1, TMU2, VEU2, LCDC, /* interrupt groups */ - DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI, + DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, }; static struct intc_vect vectors[] __initdata = { @@ -376,8 +297,8 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), - INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), - INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), + INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), + INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), INTC_VECT(SIU, 0xf80), INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), @@ -393,7 +314,6 @@ static struct intc_group groups[] __initdata = { INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), - INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), }; static struct intc_mask_reg mask_registers[] __initdata = { @@ -415,7 +335,7 @@ static struct intc_mask_reg mask_registers[] __initdata = { { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ - { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, + { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } }, { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ { 0, 0, 0, CMT, 0, USB, } }, { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ @@ -453,9 +373,13 @@ static struct intc_mask_reg ack_registers[] __initdata = { { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; -static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups, - mask_registers, prio_registers, sense_registers, - ack_registers); +static struct intc_desc intc_desc __initdata = { + .name = "sh7366", + .force_enable = ENABLED, + .force_disable = DISABLED, + .hw = INTC_HW_DESC(vectors, groups, mask_registers, + prio_registers, sense_registers, ack_registers), +}; void __init plat_irq_setup(void) { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index ea524a2da3e..57f83a92a50 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -7,15 +7,245 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#include <linux/platform_device.h> #include <linux/init.h> +#include <linux/mm.h> +#include <linux/platform_device.h> #include <linux/serial.h> #include <linux/serial_sci.h> -#include <linux/mm.h> -#include <linux/uio_driver.h> +#include <linux/sh_dma.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> +#include <linux/uio_driver.h> +#include <linux/usb/m66592.h> + #include <asm/clock.h> #include <asm/mmzone.h> +#include <asm/siu.h> + +#include <cpu/dma-register.h> +#include <cpu/sh7722.h> +#include <cpu/serial.h> + +static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { + { + .slave_id = SHDMA_SLAVE_SCIF0_TX, + .addr = 0xffe0000c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, { + .slave_id = SHDMA_SLAVE_SCIF0_RX, + .addr = 0xffe00014, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, { + .slave_id = SHDMA_SLAVE_SCIF1_TX, + .addr = 0xffe1000c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x25, + }, { + .slave_id = SHDMA_SLAVE_SCIF1_RX, + .addr = 0xffe10014, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x26, + }, { + .slave_id = SHDMA_SLAVE_SCIF2_TX, + .addr = 0xffe2000c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, { + .slave_id = SHDMA_SLAVE_SCIF2_RX, + .addr = 0xffe20014, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, { + .slave_id = SHDMA_SLAVE_SIUA_TX, + .addr = 0xa454c098, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xb1, + }, { + .slave_id = SHDMA_SLAVE_SIUA_RX, + .addr = 0xa454c090, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xb2, + }, { + .slave_id = SHDMA_SLAVE_SIUB_TX, + .addr = 0xa454c09c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xb5, + }, { + .slave_id = SHDMA_SLAVE_SIUB_RX, + .addr = 0xa454c094, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xb6, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_TX, + .addr = 0x04ce0030, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc1, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_RX, + .addr = 0x04ce0030, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc2, + }, +}; + +static const struct sh_dmae_channel sh7722_dmae_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + +static const unsigned int ts_shift[] = TS_SHIFT; + +static struct sh_dmae_pdata dma_platform_data = { + .slave = sh7722_dmae_slaves, + .slave_num = ARRAY_SIZE(sh7722_dmae_slaves), + .channel = sh7722_dmae_channels, + .channel_num = ARRAY_SIZE(sh7722_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +static struct resource sh7722_dmae_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xfe008020, + .end = 0xfe00808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xfe009000, + .end = 0xfe00900b, + .flags = IORESOURCE_MEM, + }, + { + .name = "error_irq", + .start = evt2irq(0xbc0), + .end = evt2irq(0xbc0), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 0-3 */ + .start = evt2irq(0x800), + .end = evt2irq(0x860), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 4-5 */ + .start = evt2irq(0xb80), + .end = evt2irq(0xba0), + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device dma_device = { + .name = "sh-dma-engine", + .id = -1, + .resource = sh7722_dmae_resources, + .num_resources = ARRAY_SIZE(sh7722_dmae_resources), + .dev = { + .platform_data = &dma_platform_data, + }, +}; + +/* Serial */ +static struct plat_sci_port scif0_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .ops = &sh7722_sci_port_ops, + .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .ops = &sh7722_sci_port_ops, + .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc20)), +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .ops = &sh7722_sci_port_ops, + .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe20000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc40)), +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, + }, +}; static struct resource rtc_resources[] = { [0] = { @@ -25,17 +255,17 @@ static struct resource rtc_resources[] = { }, [1] = { /* Period IRQ */ - .start = 45, + .start = evt2irq(0x7a0), .flags = IORESOURCE_IRQ, }, [2] = { /* Carry IRQ */ - .start = 46, + .start = evt2irq(0x7c0), .flags = IORESOURCE_IRQ, }, [3] = { /* Alarm IRQ */ - .start = 44, + .start = evt2irq(0x780), .flags = IORESOURCE_IRQ, }, }; @@ -47,16 +277,20 @@ static struct platform_device rtc_device = { .resource = rtc_resources, }; +static struct m66592_platdata usbf_platdata = { + .on_chip = 1, +}; + static struct resource usbf_resources[] = { [0] = { - .name = "m66592_udc", + .name = "USBF", .start = 0x04480000, .end = 0x044800FF, .flags = IORESOURCE_MEM, }, [1] = { - .start = 65, - .end = 65, + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), .flags = IORESOURCE_IRQ, }, }; @@ -67,6 +301,7 @@ static struct platform_device usbf_device = { .dev = { .dma_mask = NULL, .coherent_dma_mask = 0xffffffff, + .platform_data = &usbf_platdata, }, .num_resources = ARRAY_SIZE(usbf_resources), .resource = usbf_resources, @@ -80,8 +315,8 @@ static struct resource iic_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -96,7 +331,7 @@ static struct platform_device iic_device = { static struct uio_info vpu_platform_data = { .name = "VPU4", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -124,7 +359,7 @@ static struct platform_device vpu_device = { static struct uio_info veu_platform_data = { .name = "VEU", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu_resources[] = { @@ -152,7 +387,7 @@ static struct platform_device veu_device = { static struct uio_info jpu_platform_data = { .name = "JPU", .version = "0", - .irq = 27, + .irq = evt2irq(0x560), }; static struct resource jpu_resources[] = { @@ -178,29 +413,16 @@ static struct platform_device jpu_device = { }; static struct sh_timer_config cmt_platform_data = { - .name = "CMT", - .channel_offset = 0x60, - .timer_bit = 5, - .clk = "cmt0", - .clockevent_rating = 125, - .clocksource_rating = 125, + .channels_mask = 0x20, }; static struct resource cmt_resources[] = { - [0] = { - .name = "CMT", - .start = 0x044a0060, - .end = 0x044a006b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 104, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0x044a0000, 0x70), + DEFINE_RES_IRQ(evt2irq(0xf00)), }; static struct platform_device cmt_device = { - .name = "sh_cmt", + .name = "sh-cmt-32", .id = 0, .dev = { .platform_data = &cmt_platform_data, @@ -210,28 +432,18 @@ static struct platform_device cmt_device = { }; static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "tmu0", - .clockevent_rating = 200, + .channels_mask = 7, }; static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 16, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0xffd80000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x400)), + DEFINE_RES_IRQ(evt2irq(0x420)), + DEFINE_RES_IRQ(evt2irq(0x440)), }; static struct platform_device tmu0_device = { - .name = "sh_tmu", + .name = "sh-tmu", .id = 0, .dev = { .platform_data = &tmu0_platform_data, @@ -240,114 +452,49 @@ static struct platform_device tmu0_device = { .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "tmu0", - .clocksource_rating = 200, -}; - -static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 17, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu1_device = { - .name = "sh_tmu", - .id = 1, - .dev = { - .platform_data = &tmu1_platform_data, - }, - .resource = tmu1_resources, - .num_resources = ARRAY_SIZE(tmu1_resources), +static struct siu_platform siu_platform_data = { + .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX, + .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX, + .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX, + .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX, }; -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "tmu0", -}; - -static struct resource tmu2_resources[] = { +static struct resource siu_resources[] = { [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002b, + .start = 0xa4540000, + .end = 0xa454c10f, .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0xf80), .flags = IORESOURCE_IRQ, }, }; -static struct platform_device tmu2_device = { - .name = "sh_tmu", - .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, - }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), -}; - -static struct plat_sci_port sci_platform_data[] = { - { - .mapbase = 0xffe00000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, - .clk = "scif0", - }, - { - .mapbase = 0xffe10000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, - .clk = "scif1", - }, - { - .mapbase = 0xffe20000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, - .clk = "scif2", - }, - { - .flags = 0, - } -}; - -static struct platform_device sci_device = { - .name = "sh-sci", +static struct platform_device siu_device = { + .name = "siu-pcm-audio", .id = -1, - .dev = { - .platform_data = sci_platform_data, + .dev = { + .platform_data = &siu_platform_data, }, + .resource = siu_resources, + .num_resources = ARRAY_SIZE(siu_resources), }; static struct platform_device *sh7722_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, &cmt_device, &tmu0_device, - &tmu1_device, - &tmu2_device, &rtc_device, &usbf_device, &iic_device, - &sci_device, &vpu_device, &veu_device, &jpu_device, + &siu_device, + &dma_device, }; static int __init sh7722_devices_setup(void) @@ -359,13 +506,14 @@ static int __init sh7722_devices_setup(void) return platform_add_devices(sh7722_devices, ARRAY_SIZE(sh7722_devices)); } -__initcall(sh7722_devices_setup); +arch_initcall(sh7722_devices_setup); static struct platform_device *sh7722_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, &cmt_device, &tmu0_device, - &tmu1_device, - &tmu2_device, }; void __init plat_early_device_setup(void) @@ -376,6 +524,8 @@ void __init plat_early_device_setup(void) enum { UNUSED=0, + ENABLED, + DISABLED, /* interrupt sources */ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, @@ -391,7 +541,6 @@ enum { SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, - SDHI0, SDHI1, SDHI2, SDHI3, CMT, TSIF, SIU, TWODG, TMU0, TMU1, TMU2, IRDA, JPU, LCDC, @@ -424,8 +573,8 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), - INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), - INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), + INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), + INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), @@ -443,7 +592,6 @@ static struct intc_group groups[] __initdata = { INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), - INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), }; static struct intc_mask_reg mask_registers[] __initdata = { @@ -465,7 +613,7 @@ static struct intc_mask_reg mask_registers[] __initdata = { { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ - { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } }, + { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } }, { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ @@ -503,9 +651,13 @@ static struct intc_mask_reg ack_registers[] __initdata = { { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; -static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups, - mask_registers, prio_registers, sense_registers, - ack_registers); +static struct intc_desc intc_desc __initdata = { + .name = "sh7722", + .force_enable = ENABLED, + .force_disable = DISABLED, + .hw = INTC_HW_DESC(vectors, groups, mask_registers, + prio_registers, sense_registers, ack_registers), +}; void __init plat_irq_setup(void) { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index d8f4a13aeff..3533b56dd46 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -13,15 +13,157 @@ #include <linux/mm.h> #include <linux/serial_sci.h> #include <linux/uio_driver.h> +#include <linux/usb/r8a66597.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> #include <linux/io.h> #include <asm/clock.h> #include <asm/mmzone.h> +#include <cpu/sh7723.h> + +/* Serial */ +static struct plat_sci_port scif0_platform_data = { + .port_reg = 0xa4050160, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc20)), +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe20000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc40)), +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .port_reg = SCIx_NOT_SUPPORTED, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .sampling_rate = 8, + .type = PORT_SCIFA, +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xa4e30000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x900)), +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .sampling_rate = 8, + .type = PORT_SCIFA, +}; + +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xa4e40000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xd00)), +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .sampling_rate = 8, + .type = PORT_SCIFA, +}; + +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xa4e50000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xfa0)), +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), + .dev = { + .platform_data = &scif5_platform_data, + }, +}; static struct uio_info vpu_platform_data = { .name = "VPU5", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -49,7 +191,7 @@ static struct platform_device vpu_device = { static struct uio_info veu0_platform_data = { .name = "VEU2H", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu0_resources[] = { @@ -77,7 +219,7 @@ static struct platform_device veu0_device = { static struct uio_info veu1_platform_data = { .name = "VEU2H", .version = "0", - .irq = 27, + .irq = evt2irq(0x560), }; static struct resource veu1_resources[] = { @@ -103,29 +245,16 @@ static struct platform_device veu1_device = { }; static struct sh_timer_config cmt_platform_data = { - .name = "CMT", - .channel_offset = 0x60, - .timer_bit = 5, - .clk = "cmt0", - .clockevent_rating = 125, - .clocksource_rating = 125, + .channels_mask = 0x20, }; static struct resource cmt_resources[] = { - [0] = { - .name = "CMT", - .start = 0x044a0060, - .end = 0x044a006b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 104, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0x044a0000, 0x70), + DEFINE_RES_IRQ(evt2irq(0xf00)), }; static struct platform_device cmt_device = { - .name = "sh_cmt", + .name = "sh-cmt-32", .id = 0, .dev = { .platform_data = &cmt_platform_data, @@ -135,28 +264,18 @@ static struct platform_device cmt_device = { }; static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "tmu0", - .clockevent_rating = 200, + .channels_mask = 7, }; static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 16, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0xffd80000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x400)), + DEFINE_RES_IRQ(evt2irq(0x420)), + DEFINE_RES_IRQ(evt2irq(0x440)), }; static struct platform_device tmu0_device = { - .name = "sh_tmu", + .name = "sh-tmu", .id = 0, .dev = { .platform_data = &tmu0_platform_data, @@ -166,28 +285,18 @@ static struct platform_device tmu0_device = { }; static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "tmu0", - .clocksource_rating = 200, + .channels_mask = 7, }; static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 17, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0xffd90000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x920)), + DEFINE_RES_IRQ(evt2irq(0x940)), + DEFINE_RES_IRQ(evt2irq(0x960)), }; static struct platform_device tmu1_device = { - .name = "sh_tmu", + .name = "sh-tmu", .id = 1, .dev = { .platform_data = &tmu1_platform_data, @@ -196,176 +305,6 @@ static struct platform_device tmu1_device = { .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "tmu0", -}; - -static struct resource tmu2_resources[] = { - [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 18, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu2_device = { - .name = "sh_tmu", - .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, - }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), -}; - -static struct sh_timer_config tmu3_platform_data = { - .name = "TMU3", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "tmu1", -}; - -static struct resource tmu3_resources[] = { - [0] = { - .name = "TMU3", - .start = 0xffd90008, - .end = 0xffd90013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 57, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu3_device = { - .name = "sh_tmu", - .id = 3, - .dev = { - .platform_data = &tmu3_platform_data, - }, - .resource = tmu3_resources, - .num_resources = ARRAY_SIZE(tmu3_resources), -}; - -static struct sh_timer_config tmu4_platform_data = { - .name = "TMU4", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "tmu1", -}; - -static struct resource tmu4_resources[] = { - [0] = { - .name = "TMU4", - .start = 0xffd90014, - .end = 0xffd9001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 58, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu4_device = { - .name = "sh_tmu", - .id = 4, - .dev = { - .platform_data = &tmu4_platform_data, - }, - .resource = tmu4_resources, - .num_resources = ARRAY_SIZE(tmu4_resources), -}; - -static struct sh_timer_config tmu5_platform_data = { - .name = "TMU5", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "tmu1", -}; - -static struct resource tmu5_resources[] = { - [0] = { - .name = "TMU5", - .start = 0xffd90020, - .end = 0xffd9002b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 57, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu5_device = { - .name = "sh_tmu", - .id = 5, - .dev = { - .platform_data = &tmu5_platform_data, - }, - .resource = tmu5_resources, - .num_resources = ARRAY_SIZE(tmu5_resources), -}; - -static struct plat_sci_port sci_platform_data[] = { - { - .mapbase = 0xffe00000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, - .clk = "scif0", - },{ - .mapbase = 0xffe10000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, - .clk = "scif1", - },{ - .mapbase = 0xffe20000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, - .clk = "scif2", - },{ - .mapbase = 0xa4e30000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIFA, - .irqs = { 56, 56, 56, 56 }, - .clk = "scif3", - },{ - .mapbase = 0xa4e40000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIFA, - .irqs = { 88, 88, 88, 88 }, - .clk = "scif4", - },{ - .mapbase = 0xa4e50000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIFA, - .irqs = { 109, 109, 109, 109 }, - .clk = "scif5", - }, { - .flags = 0, - } -}; - -static struct platform_device sci_device = { - .name = "sh-sci", - .id = -1, - .dev = { - .platform_data = sci_platform_data, - }, -}; - static struct resource rtc_resources[] = { [0] = { .start = 0xa465fec0, @@ -374,17 +313,17 @@ static struct resource rtc_resources[] = { }, [1] = { /* Period IRQ */ - .start = 69, + .start = evt2irq(0xaa0), .flags = IORESOURCE_IRQ, }, [2] = { /* Carry IRQ */ - .start = 70, + .start = evt2irq(0xac0), .flags = IORESOURCE_IRQ, }, [3] = { /* Alarm IRQ */ - .start = 68, + .start = evt2irq(0xa80), .flags = IORESOURCE_IRQ, }, }; @@ -396,17 +335,20 @@ static struct platform_device rtc_device = { .resource = rtc_resources, }; +static struct r8a66597_platdata r8a66597_data = { + .on_chip = 1, +}; + static struct resource sh7723_usb_host_resources[] = { [0] = { - .name = "r8a66597_hcd", .start = 0xa4d80000, .end = 0xa4d800ff, .flags = IORESOURCE_MEM, }, [1] = { - .start = 65, - .end = 65, - .flags = IORESOURCE_IRQ, + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, }, }; @@ -416,6 +358,7 @@ static struct platform_device sh7723_usb_host_device = { .dev = { .dma_mask = NULL, /* not use dma */ .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, }, .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), .resource = sh7723_usb_host_resources, @@ -429,8 +372,8 @@ static struct resource iic_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -443,14 +386,15 @@ static struct platform_device iic_device = { }; static struct platform_device *sh7723_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, &cmt_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, - &sci_device, &rtc_device, &iic_device, &sh7723_usb_host_device, @@ -468,16 +412,18 @@ static int __init sh7723_devices_setup(void) return platform_add_devices(sh7723_devices, ARRAY_SIZE(sh7723_devices)); } -__initcall(sh7723_devices_setup); +arch_initcall(sh7723_devices_setup); static struct platform_device *sh7723_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, &cmt_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, }; void __init plat_early_device_setup(void) @@ -489,14 +435,17 @@ void __init plat_early_device_setup(void) #define RAMCR_CACHE_L2FC 0x0002 #define RAMCR_CACHE_L2E 0x0001 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) -void __uses_jump_to_uncached l2_cache_init(void) + +void l2_cache_init(void) { /* Enable L2 cache */ - ctrl_outl(L2_CACHE_ENABLE, RAMCR); + __raw_writel(L2_CACHE_ENABLE, RAMCR); } enum { UNUSED=0, + ENABLED, + DISABLED, /* interrupt sources */ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, @@ -519,7 +468,6 @@ enum { SCIFA_SCIFA1, FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, - SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2, CMT_CMTI, TSIF_TSIFI, SIU_SIUI, @@ -527,7 +475,6 @@ enum { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI, ATAPI_ATAPII, - SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2, VEU2H1_VEU2HI, LCDC_LCDCI, TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, @@ -598,9 +545,9 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(I2C_WAITI,0xE40), INTC_VECT(I2C_DTEI,0xE60), - INTC_VECT(SDHI0_SDHII0,0xE80), - INTC_VECT(SDHI0_SDHII1,0xEA0), - INTC_VECT(SDHI0_SDHII2,0xEC0), + INTC_VECT(SDHI0, 0xE80), + INTC_VECT(SDHI0, 0xEA0), + INTC_VECT(SDHI0, 0xEC0), INTC_VECT(CMT_CMTI,0xF00), INTC_VECT(TSIF_TSIFI,0xF20), @@ -614,9 +561,9 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(IRDA_IRDAI,0x480), INTC_VECT(ATAPI_ATAPII,0x4A0), - INTC_VECT(SDHI1_SDHII0,0x4E0), - INTC_VECT(SDHI1_SDHII1,0x500), - INTC_VECT(SDHI1_SDHII2,0x520), + INTC_VECT(SDHI1, 0x4E0), + INTC_VECT(SDHI1, 0x500), + INTC_VECT(SDHI1, 0x520), INTC_VECT(VEU2H1_VEU2HI,0x560), INTC_VECT(LCDC_LCDCI,0x580), @@ -635,15 +582,14 @@ static struct intc_group groups[] __initdata = { INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), - INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2), INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), - INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2), }; static struct intc_mask_reg mask_registers[] __initdata = { { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ - { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} }, + { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, + 0, ENABLED, ENABLED, ENABLED } }, { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ @@ -660,7 +606,8 @@ static struct intc_mask_reg mask_registers[] __initdata = { { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ - { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } }, + { 0, ENABLED, ENABLED, ENABLED, + 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ @@ -700,9 +647,13 @@ static struct intc_mask_reg ack_registers[] __initdata = { { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; -static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups, - mask_registers, prio_registers, sense_registers, - ack_registers); +static struct intc_desc intc_desc __initdata = { + .name = "sh7723", + .force_enable = ENABLED, + .force_disable = DISABLED, + .hw = INTC_HW_DESC(vectors, groups, mask_registers, + prio_registers, sense_registers, ack_registers), +}; void __init plat_irq_setup(void) { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index e5ac9eb11c6..b9e84b1d3aa 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -18,59 +18,412 @@ #include <linux/mm.h> #include <linux/serial_sci.h> #include <linux/uio_driver.h> +#include <linux/sh_dma.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> #include <linux/io.h> +#include <linux/notifier.h> + +#include <asm/suspend.h> #include <asm/clock.h> #include <asm/mmzone.h> -/* Serial */ -static struct plat_sci_port sci_platform_data[] = { +#include <cpu/dma-register.h> +#include <cpu/sh7724.h> + +/* DMA */ +static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = { { - .mapbase = 0xffe00000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, - .clk = "scif0", + .slave_id = SHDMA_SLAVE_SCIF0_TX, + .addr = 0xffe0000c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, { + .slave_id = SHDMA_SLAVE_SCIF0_RX, + .addr = 0xffe00014, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, { + .slave_id = SHDMA_SLAVE_SCIF1_TX, + .addr = 0xffe1000c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x25, + }, { + .slave_id = SHDMA_SLAVE_SCIF1_RX, + .addr = 0xffe10014, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x26, + }, { + .slave_id = SHDMA_SLAVE_SCIF2_TX, + .addr = 0xffe2000c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, { + .slave_id = SHDMA_SLAVE_SCIF2_RX, + .addr = 0xffe20014, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, { + .slave_id = SHDMA_SLAVE_SCIF3_TX, + .addr = 0xa4e30020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2d, + }, { + .slave_id = SHDMA_SLAVE_SCIF3_RX, + .addr = 0xa4e30024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2e, + }, { + .slave_id = SHDMA_SLAVE_SCIF4_TX, + .addr = 0xa4e40020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x31, + }, { + .slave_id = SHDMA_SLAVE_SCIF4_RX, + .addr = 0xa4e40024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x32, + }, { + .slave_id = SHDMA_SLAVE_SCIF5_TX, + .addr = 0xa4e50020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x35, + }, { + .slave_id = SHDMA_SLAVE_SCIF5_RX, + .addr = 0xa4e50024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x36, + }, { + .slave_id = SHDMA_SLAVE_USB0D0_TX, + .addr = 0xA4D80100, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0x73, + }, { + .slave_id = SHDMA_SLAVE_USB0D0_RX, + .addr = 0xA4D80100, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0x73, }, { - .mapbase = 0xffe10000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, - .clk = "scif1", + .slave_id = SHDMA_SLAVE_USB0D1_TX, + .addr = 0xA4D80120, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0x77, }, { - .mapbase = 0xffe20000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, - .clk = "scif2", + .slave_id = SHDMA_SLAVE_USB0D1_RX, + .addr = 0xA4D80120, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0x77, }, { - .mapbase = 0xa4e30000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIFA, - .irqs = { 56, 56, 56, 56 }, - .clk = "scif3", + .slave_id = SHDMA_SLAVE_USB1D0_TX, + .addr = 0xA4D90100, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xab, }, { - .mapbase = 0xa4e40000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIFA, - .irqs = { 88, 88, 88, 88 }, - .clk = "scif4", + .slave_id = SHDMA_SLAVE_USB1D0_RX, + .addr = 0xA4D90100, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xab, }, { - .mapbase = 0xa4e50000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIFA, - .irqs = { 109, 109, 109, 109 }, - .clk = "scif5", + .slave_id = SHDMA_SLAVE_USB1D1_TX, + .addr = 0xA4D90120, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xaf, }, { - .flags = 0, + .slave_id = SHDMA_SLAVE_USB1D1_RX, + .addr = 0xA4D90120, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xaf, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_TX, + .addr = 0x04ce0030, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc1, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_RX, + .addr = 0x04ce0030, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc2, + }, { + .slave_id = SHDMA_SLAVE_SDHI1_TX, + .addr = 0x04cf0030, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc9, + }, { + .slave_id = SHDMA_SLAVE_SDHI1_RX, + .addr = 0x04cf0030, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xca, + }, +}; + +static const struct sh_dmae_channel sh7724_dmae_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, } }; -static struct platform_device sci_device = { +static const unsigned int ts_shift[] = TS_SHIFT; + +static struct sh_dmae_pdata dma_platform_data = { + .slave = sh7724_dmae_slaves, + .slave_num = ARRAY_SIZE(sh7724_dmae_slaves), + .channel = sh7724_dmae_channels, + .channel_num = ARRAY_SIZE(sh7724_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +/* Resource order important! */ +static struct resource sh7724_dmae0_resources[] = { + { + /* Channel registers and DMAOR */ + .start = 0xfe008020, + .end = 0xfe00808f, + .flags = IORESOURCE_MEM, + }, + { + /* DMARSx */ + .start = 0xfe009000, + .end = 0xfe00900b, + .flags = IORESOURCE_MEM, + }, + { + .name = "error_irq", + .start = evt2irq(0xbc0), + .end = evt2irq(0xbc0), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 0-3 */ + .start = evt2irq(0x800), + .end = evt2irq(0x860), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 4-5 */ + .start = evt2irq(0xb80), + .end = evt2irq(0xba0), + .flags = IORESOURCE_IRQ, + }, +}; + +/* Resource order important! */ +static struct resource sh7724_dmae1_resources[] = { + { + /* Channel registers and DMAOR */ + .start = 0xfdc08020, + .end = 0xfdc0808f, + .flags = IORESOURCE_MEM, + }, + { + /* DMARSx */ + .start = 0xfdc09000, + .end = 0xfdc0900b, + .flags = IORESOURCE_MEM, + }, + { + .name = "error_irq", + .start = evt2irq(0xb40), + .end = evt2irq(0xb40), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 0-3 */ + .start = evt2irq(0x700), + .end = evt2irq(0x760), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 4-5 */ + .start = evt2irq(0xb00), + .end = evt2irq(0xb20), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dma0_device = { + .name = "sh-dma-engine", + .id = 0, + .resource = sh7724_dmae0_resources, + .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), + .dev = { + .platform_data = &dma_platform_data, + }, +}; + +static struct platform_device dma1_device = { + .name = "sh-dma-engine", + .id = 1, + .resource = sh7724_dmae1_resources, + .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), + .dev = { + .platform_data = &dma_platform_data, + }, +}; + +/* Serial */ +static struct plat_sci_port scif0_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), +}; + +static struct platform_device scif0_device = { .name = "sh-sci", - .id = -1, + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc20)), +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe20000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc40)), +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .sampling_rate = 8, + .type = PORT_SCIFA, +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xa4e30000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x900)), +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .sampling_rate = 8, + .type = PORT_SCIFA, +}; + +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xa4e40000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xd00)), +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .port_reg = SCIx_NOT_SUPPORTED, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .sampling_rate = 8, + .type = PORT_SCIFA, +}; + +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xa4e50000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xfa0)), +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { - .platform_data = sci_platform_data, + .platform_data = &scif5_platform_data, }, }; @@ -83,17 +436,17 @@ static struct resource rtc_resources[] = { }, [1] = { /* Period IRQ */ - .start = 69, + .start = evt2irq(0xaa0), .flags = IORESOURCE_IRQ, }, [2] = { /* Carry IRQ */ - .start = 70, + .start = evt2irq(0xac0), .flags = IORESOURCE_IRQ, }, [3] = { /* Alarm IRQ */ - .start = 68, + .start = evt2irq(0xa80), .flags = IORESOURCE_IRQ, }, }; @@ -114,8 +467,8 @@ static struct resource iic0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -136,8 +489,8 @@ static struct resource iic1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 92, - .end = 95, + .start = evt2irq(0xd80), + .end = evt2irq(0xde0), .flags = IORESOURCE_IRQ, }, }; @@ -153,7 +506,7 @@ static struct platform_device iic1_device = { static struct uio_info vpu_platform_data = { .name = "VPU5F", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -182,14 +535,14 @@ static struct platform_device vpu_device = { static struct uio_info veu0_platform_data = { .name = "VEU3F0", .version = "0", - .irq = 83, + .irq = evt2irq(0xc60), }; static struct resource veu0_resources[] = { [0] = { .name = "VEU3F0", .start = 0xfe920000, - .end = 0xfe9200cb - 1, + .end = 0xfe9200cb, .flags = IORESOURCE_MEM, }, [1] = { @@ -211,14 +564,14 @@ static struct platform_device veu0_device = { static struct uio_info veu1_platform_data = { .name = "VEU3F1", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu1_resources[] = { [0] = { .name = "VEU3F1", .start = 0xfe924000, - .end = 0xfe9240cb - 1, + .end = 0xfe9240cb, .flags = IORESOURCE_MEM, }, [1] = { @@ -236,233 +589,195 @@ static struct platform_device veu1_device = { .num_resources = ARRAY_SIZE(veu1_resources), }; -static struct sh_timer_config cmt_platform_data = { - .name = "CMT", - .channel_offset = 0x60, - .timer_bit = 5, - .clk = "cmt0", - .clockevent_rating = 125, - .clocksource_rating = 200, +/* BEU0 */ +static struct uio_info beu0_platform_data = { + .name = "BEU0", + .version = "0", + .irq = evt2irq(0x8A0), }; -static struct resource cmt_resources[] = { +static struct resource beu0_resources[] = { [0] = { - .name = "CMT", - .start = 0x044a0060, - .end = 0x044a006b, + .name = "BEU0", + .start = 0xfe930000, + .end = 0xfe933400, .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, - .flags = IORESOURCE_IRQ, + /* place holder for contiguous memory */ }, }; -static struct platform_device cmt_device = { - .name = "sh_cmt", - .id = 0, +static struct platform_device beu0_device = { + .name = "uio_pdrv_genirq", + .id = 6, .dev = { - .platform_data = &cmt_platform_data, + .platform_data = &beu0_platform_data, }, - .resource = cmt_resources, - .num_resources = ARRAY_SIZE(cmt_resources), + .resource = beu0_resources, + .num_resources = ARRAY_SIZE(beu0_resources), }; -static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "tmu0", - .clockevent_rating = 200, +/* BEU1 */ +static struct uio_info beu1_platform_data = { + .name = "BEU1", + .version = "0", + .irq = evt2irq(0xA00), }; -static struct resource tmu0_resources[] = { +static struct resource beu1_resources[] = { [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, + .name = "BEU1", + .start = 0xfe940000, + .end = 0xfe943400, .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, - .flags = IORESOURCE_IRQ, + /* place holder for contiguous memory */ }, }; -static struct platform_device tmu0_device = { - .name = "sh_tmu", - .id = 0, +static struct platform_device beu1_device = { + .name = "uio_pdrv_genirq", + .id = 7, .dev = { - .platform_data = &tmu0_platform_data, + .platform_data = &beu1_platform_data, }, - .resource = tmu0_resources, - .num_resources = ARRAY_SIZE(tmu0_resources), + .resource = beu1_resources, + .num_resources = ARRAY_SIZE(beu1_resources), }; -static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "tmu0", - .clocksource_rating = 200, +static struct sh_timer_config cmt_platform_data = { + .channels_mask = 0x20, }; -static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 17, - .flags = IORESOURCE_IRQ, - }, +static struct resource cmt_resources[] = { + DEFINE_RES_MEM(0x044a0000, 0x70), + DEFINE_RES_IRQ(evt2irq(0xf00)), }; -static struct platform_device tmu1_device = { - .name = "sh_tmu", - .id = 1, +static struct platform_device cmt_device = { + .name = "sh-cmt-32", + .id = 0, .dev = { - .platform_data = &tmu1_platform_data, + .platform_data = &cmt_platform_data, }, - .resource = tmu1_resources, - .num_resources = ARRAY_SIZE(tmu1_resources), + .resource = cmt_resources, + .num_resources = ARRAY_SIZE(cmt_resources), }; -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "tmu0", +static struct sh_timer_config tmu0_platform_data = { + .channels_mask = 7, }; -static struct resource tmu2_resources[] = { - [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 18, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu0_resources[] = { + DEFINE_RES_MEM(0xffd80000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x400)), + DEFINE_RES_IRQ(evt2irq(0x420)), + DEFINE_RES_IRQ(evt2irq(0x440)), }; -static struct platform_device tmu2_device = { - .name = "sh_tmu", - .id = 2, +static struct platform_device tmu0_device = { + .name = "sh-tmu", + .id = 0, .dev = { - .platform_data = &tmu2_platform_data, + .platform_data = &tmu0_platform_data, }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), + .resource = tmu0_resources, + .num_resources = ARRAY_SIZE(tmu0_resources), }; - -static struct sh_timer_config tmu3_platform_data = { - .name = "TMU3", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "tmu1", +static struct sh_timer_config tmu1_platform_data = { + .channels_mask = 7, }; -static struct resource tmu3_resources[] = { - [0] = { - .name = "TMU3", - .start = 0xffd90008, - .end = 0xffd90013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 57, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu1_resources[] = { + DEFINE_RES_MEM(0xffd90000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x920)), + DEFINE_RES_IRQ(evt2irq(0x940)), + DEFINE_RES_IRQ(evt2irq(0x960)), }; -static struct platform_device tmu3_device = { - .name = "sh_tmu", - .id = 3, +static struct platform_device tmu1_device = { + .name = "sh-tmu", + .id = 1, .dev = { - .platform_data = &tmu3_platform_data, + .platform_data = &tmu1_platform_data, }, - .resource = tmu3_resources, - .num_resources = ARRAY_SIZE(tmu3_resources), + .resource = tmu1_resources, + .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu4_platform_data = { - .name = "TMU4", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "tmu1", +/* JPU */ +static struct uio_info jpu_platform_data = { + .name = "JPU", + .version = "0", + .irq = evt2irq(0x560), }; -static struct resource tmu4_resources[] = { +static struct resource jpu_resources[] = { [0] = { - .name = "TMU4", - .start = 0xffd90014, - .end = 0xffd9001f, + .name = "JPU", + .start = 0xfe980000, + .end = 0xfe9902d3, .flags = IORESOURCE_MEM, }, [1] = { - .start = 58, - .flags = IORESOURCE_IRQ, + /* place holder for contiguous memory */ }, }; -static struct platform_device tmu4_device = { - .name = "sh_tmu", - .id = 4, +static struct platform_device jpu_device = { + .name = "uio_pdrv_genirq", + .id = 3, .dev = { - .platform_data = &tmu4_platform_data, + .platform_data = &jpu_platform_data, }, - .resource = tmu4_resources, - .num_resources = ARRAY_SIZE(tmu4_resources), + .resource = jpu_resources, + .num_resources = ARRAY_SIZE(jpu_resources), }; -static struct sh_timer_config tmu5_platform_data = { - .name = "TMU5", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "tmu1", +/* SPU2DSP0 */ +static struct uio_info spu0_platform_data = { + .name = "SPU2DSP0", + .version = "0", + .irq = evt2irq(0xcc0), }; -static struct resource tmu5_resources[] = { +static struct resource spu0_resources[] = { [0] = { - .name = "TMU5", - .start = 0xffd90020, - .end = 0xffd9002b, + .name = "SPU2DSP0", + .start = 0xFE200000, + .end = 0xFE2FFFFF, .flags = IORESOURCE_MEM, }, [1] = { - .start = 57, - .flags = IORESOURCE_IRQ, + /* place holder for contiguous memory */ }, }; -static struct platform_device tmu5_device = { - .name = "sh_tmu", - .id = 5, +static struct platform_device spu0_device = { + .name = "uio_pdrv_genirq", + .id = 4, .dev = { - .platform_data = &tmu5_platform_data, + .platform_data = &spu0_platform_data, }, - .resource = tmu5_resources, - .num_resources = ARRAY_SIZE(tmu5_resources), + .resource = spu0_resources, + .num_resources = ARRAY_SIZE(spu0_resources), }; -/* JPU */ -static struct uio_info jpu_platform_data = { - .name = "JPU", +/* SPU2DSP1 */ +static struct uio_info spu1_platform_data = { + .name = "SPU2DSP1", .version = "0", - .irq = 27, + .irq = evt2irq(0xce0), }; -static struct resource jpu_resources[] = { +static struct resource spu1_resources[] = { [0] = { - .name = "JPU", - .start = 0xfe980000, - .end = 0xfe9902d3, + .name = "SPU2DSP1", + .start = 0xFE300000, + .end = 0xFE3FFFFF, .flags = IORESOURCE_MEM, }, [1] = { @@ -470,32 +785,39 @@ static struct resource jpu_resources[] = { }, }; -static struct platform_device jpu_device = { +static struct platform_device spu1_device = { .name = "uio_pdrv_genirq", - .id = 3, + .id = 5, .dev = { - .platform_data = &jpu_platform_data, + .platform_data = &spu1_platform_data, }, - .resource = jpu_resources, - .num_resources = ARRAY_SIZE(jpu_resources), + .resource = spu1_resources, + .num_resources = ARRAY_SIZE(spu1_resources), }; static struct platform_device *sh7724_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, &cmt_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, - &sci_device, + &dma0_device, + &dma1_device, &rtc_device, &iic0_device, &iic1_device, &vpu_device, &veu0_device, &veu1_device, + &beu0_device, + &beu1_device, &jpu_device, + &spu0_device, + &spu1_device, }; static int __init sh7724_devices_setup(void) @@ -504,20 +826,24 @@ static int __init sh7724_devices_setup(void) platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); + platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20); + platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20); return platform_add_devices(sh7724_devices, ARRAY_SIZE(sh7724_devices)); } -device_initcall(sh7724_devices_setup); +arch_initcall(sh7724_devices_setup); static struct platform_device *sh7724_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, &cmt_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, }; void __init plat_early_device_setup(void) @@ -529,14 +855,17 @@ void __init plat_early_device_setup(void) #define RAMCR_CACHE_L2FC 0x0002 #define RAMCR_CACHE_L2E 0x0001 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) -void __uses_jump_to_uncached l2_cache_init(void) + +void l2_cache_init(void) { /* Enable L2 cache */ - ctrl_outl(L2_CACHE_ENABLE, RAMCR); + __raw_writel(L2_CACHE_ENABLE, RAMCR); } enum { UNUSED = 0, + ENABLED, + DISABLED, /* interrupt sources */ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, @@ -565,14 +894,12 @@ enum { ETHI, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, - SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3, CMT, TSIF, FSI, SCIFA5, TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA, - SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2, JPU, _2DDMAC, MMC_MMC2I, MMC_MMC3I, @@ -654,10 +981,10 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(I2C0_WAITI, 0xE40), INTC_VECT(I2C0_DTEI, 0xE60), - INTC_VECT(SDHI0_SDHII0, 0xE80), - INTC_VECT(SDHI0_SDHII1, 0xEA0), - INTC_VECT(SDHI0_SDHII2, 0xEC0), - INTC_VECT(SDHI0_SDHII3, 0xEE0), + INTC_VECT(SDHI0, 0xE80), + INTC_VECT(SDHI0, 0xEA0), + INTC_VECT(SDHI0, 0xEC0), + INTC_VECT(SDHI0, 0xEE0), INTC_VECT(CMT, 0xF00), INTC_VECT(TSIF, 0xF20), @@ -670,9 +997,9 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(IRDA, 0x480), - INTC_VECT(SDHI1_SDHII0, 0x4E0), - INTC_VECT(SDHI1_SDHII1, 0x500), - INTC_VECT(SDHI1_SDHII2, 0x520), + INTC_VECT(SDHI1, 0x4E0), + INTC_VECT(SDHI1, 0x500), + INTC_VECT(SDHI1, 0x520), INTC_VECT(JPU, 0x560), INTC_VECT(_2DDMAC, 0x4A0), @@ -698,8 +1025,6 @@ static struct intc_group groups[] __initdata = { INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), - INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3), - INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2), INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), }; @@ -707,7 +1032,7 @@ static struct intc_group groups[] __initdata = { static struct intc_mask_reg mask_registers[] __initdata = { { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, - 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } }, + 0, ENABLED, ENABLED, ENABLED } }, { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, @@ -729,7 +1054,7 @@ static struct intc_mask_reg mask_registers[] __initdata = { { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ - { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0, + { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, SCIFA5, FSI } }, { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, @@ -776,11 +1101,205 @@ static struct intc_mask_reg ack_registers[] __initdata = { { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; -static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups, - mask_registers, prio_registers, sense_registers, - ack_registers); +static struct intc_desc intc_desc __initdata = { + .name = "sh7724", + .force_enable = ENABLED, + .force_disable = DISABLED, + .hw = INTC_HW_DESC(vectors, groups, mask_registers, + prio_registers, sense_registers, ack_registers), +}; void __init plat_irq_setup(void) { register_intc_controller(&intc_desc); } + +static struct { + /* BSC */ + unsigned long mmselr; + unsigned long cs0bcr; + unsigned long cs4bcr; + unsigned long cs5abcr; + unsigned long cs5bbcr; + unsigned long cs6abcr; + unsigned long cs6bbcr; + unsigned long cs4wcr; + unsigned long cs5awcr; + unsigned long cs5bwcr; + unsigned long cs6awcr; + unsigned long cs6bwcr; + /* INTC */ + unsigned short ipra; + unsigned short iprb; + unsigned short iprc; + unsigned short iprd; + unsigned short ipre; + unsigned short iprf; + unsigned short iprg; + unsigned short iprh; + unsigned short ipri; + unsigned short iprj; + unsigned short iprk; + unsigned short iprl; + unsigned char imr0; + unsigned char imr1; + unsigned char imr2; + unsigned char imr3; + unsigned char imr4; + unsigned char imr5; + unsigned char imr6; + unsigned char imr7; + unsigned char imr8; + unsigned char imr9; + unsigned char imr10; + unsigned char imr11; + unsigned char imr12; + /* RWDT */ + unsigned short rwtcnt; + unsigned short rwtcsr; + /* CPG */ + unsigned long irdaclk; + unsigned long spuclk; +} sh7724_rstandby_state; + +static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb, + unsigned long flags, void *unused) +{ + if (!(flags & SUSP_SH_RSTANDBY)) + return NOTIFY_DONE; + + /* BCR */ + sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ + sh7724_rstandby_state.mmselr |= 0xa5a50000; + sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ + sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ + sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ + sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ + sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ + sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ + sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ + sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ + sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ + sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ + sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ + + /* INTC */ + sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */ + sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */ + sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */ + sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */ + sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */ + sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */ + sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */ + sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */ + sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */ + sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */ + sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */ + sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */ + sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */ + sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */ + sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */ + sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */ + sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */ + sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */ + sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */ + sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */ + sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */ + sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */ + sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */ + sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */ + sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */ + + /* RWDT */ + sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */ + sh7724_rstandby_state.rwtcnt |= 0x5a00; + sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */ + sh7724_rstandby_state.rwtcsr |= 0xa500; + __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004); + + /* CPG */ + sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */ + sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */ + + return NOTIFY_DONE; +} + +static int sh7724_post_sleep_notifier_call(struct notifier_block *nb, + unsigned long flags, void *unused) +{ + if (!(flags & SUSP_SH_RSTANDBY)) + return NOTIFY_DONE; + + /* BCR */ + __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ + __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ + __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ + __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ + __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ + __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ + __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ + __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ + __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ + __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */ + __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */ + __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */ + + /* INTC */ + __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */ + __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */ + __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */ + __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */ + __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */ + __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */ + __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */ + __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */ + __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */ + __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */ + __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */ + __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */ + __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ + __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ + __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ + __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ + __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ + __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ + __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ + __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ + __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ + __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ + __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */ + __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */ + __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */ + + /* RWDT */ + __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */ + __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */ + + /* CPG */ + __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */ + __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */ + + return NOTIFY_DONE; +} + +static struct notifier_block sh7724_pre_sleep_notifier = { + .notifier_call = sh7724_pre_sleep_notifier_call, + .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU), +}; + +static struct notifier_block sh7724_post_sleep_notifier = { + .notifier_call = sh7724_post_sleep_notifier_call, + .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU), +}; + +static int __init sh7724_sleep_setup(void) +{ + atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list, + &sh7724_pre_sleep_notifier); + + atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list, + &sh7724_post_sleep_notifier); + return 0; +} +arch_initcall(sh7724_sleep_setup); + diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c new file mode 100644 index 00000000000..f617bcb734d --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c @@ -0,0 +1,629 @@ +/* + * arch/sh/kernel/cpu/sh4a/setup-sh7734.c + + * SH7734 Setup + * + * Copyright (C) 2011,2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * Copyright (C) 2011,2012 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial.h> +#include <linux/mm.h> +#include <linux/dma-mapping.h> +#include <linux/serial_sci.h> +#include <linux/sh_timer.h> +#include <linux/io.h> +#include <asm/clock.h> +#include <asm/irq.h> +#include <cpu/sh7734.h> + +/* SCIF */ +static struct plat_sci_port scif0_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe40000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x8c0)), +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe41000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x8e0)), +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe42000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x900)), +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xffe43000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x920)), +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xffe44000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x940)), +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xffe43000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x960)), +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +/* RTC */ +static struct resource rtc_resources[] = { + [0] = { + .name = "rtc", + .start = 0xFFFC5000, + .end = 0xFFFC5000 + 0x26 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = evt2irq(0xC00), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +/* I2C 0 */ +static struct resource i2c0_resources[] = { + [0] = { + .name = "IIC0", + .start = 0xFFC70000, + .end = 0xFFC7000A - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x860), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c0_device = { + .name = "i2c-sh7734", + .id = 0, + .num_resources = ARRAY_SIZE(i2c0_resources), + .resource = i2c0_resources, +}; + +/* TMU */ +static struct sh_timer_config tmu0_platform_data = { + .channels_mask = 7, +}; + +static struct resource tmu0_resources[] = { + DEFINE_RES_MEM(0xffd80000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x400)), + DEFINE_RES_IRQ(evt2irq(0x420)), + DEFINE_RES_IRQ(evt2irq(0x440)), +}; + +static struct platform_device tmu0_device = { + .name = "sh-tmu", + .id = 0, + .dev = { + .platform_data = &tmu0_platform_data, + }, + .resource = tmu0_resources, + .num_resources = ARRAY_SIZE(tmu0_resources), +}; + +static struct sh_timer_config tmu1_platform_data = { + .channels_mask = 7, +}; + +static struct resource tmu1_resources[] = { + DEFINE_RES_MEM(0xffd81000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x480)), + DEFINE_RES_IRQ(evt2irq(0x4a0)), + DEFINE_RES_IRQ(evt2irq(0x4c0)), +}; + +static struct platform_device tmu1_device = { + .name = "sh-tmu", + .id = 1, + .dev = { + .platform_data = &tmu1_platform_data, + }, + .resource = tmu1_resources, + .num_resources = ARRAY_SIZE(tmu1_resources), +}; + +static struct sh_timer_config tmu2_platform_data = { + .channels_mask = 7, +}; + +static struct resource tmu2_resources[] = { + DEFINE_RES_MEM(0xffd82000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x500)), + DEFINE_RES_IRQ(evt2irq(0x520)), + DEFINE_RES_IRQ(evt2irq(0x540)), +}; + +static struct platform_device tmu2_device = { + .name = "sh-tmu", + .id = 2, + .dev = { + .platform_data = &tmu2_platform_data, + }, + .resource = tmu2_resources, + .num_resources = ARRAY_SIZE(tmu2_resources), +}; + +static struct platform_device *sh7734_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &tmu0_device, + &tmu1_device, + &tmu2_device, + &rtc_device, +}; + +static struct platform_device *sh7734_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &tmu0_device, + &tmu1_device, + &tmu2_device, +}; + +void __init plat_early_device_setup(void) +{ + early_platform_add_devices(sh7734_early_devices, + ARRAY_SIZE(sh7734_early_devices)); +} + +#define GROUP 0 +enum { + UNUSED = 0, + + /* interrupt sources */ + + IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, + IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, + IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, + IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, + + IRQ0, IRQ1, IRQ2, IRQ3, + DU, + TMU00, TMU10, TMU20, TMU21, + TMU30, TMU40, TMU50, TMU51, + TMU60, TMU70, TMU80, + RESET_WDT, + USB, + HUDI, + SHDMAC, + SSI0, SSI1, SSI2, SSI3, + VIN0, + RGPVG, + _2DG, + MMC, + HSPI, + LBSCATA, + I2C0, + RCAN0, + MIMLB, + SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, + LBSCDMAC0, LBSCDMAC1, LBSCDMAC2, + RCAN1, + SDHI0, SDHI1, + IEBUS, + HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28, + RTC, + VIN1, + LCDC, + SRC0, SRC1, + GETHER, + SDHI2, + GPIO0_3, GPIO4_5, + STIF0, STIF1, + ADMAC, + HIF, + FLCTL, + ADC, + MTU2, + RSPI, + QSPI, + HSCIF, + VEU3F_VE3, + + /* Group */ + /* Mask */ + STIF_M, + GPIO_M, + HPBDMAC_M, + LBSCDMAC_M, + RCAN_M, + SRC_M, + SCIF_M, + LCDC_M, + _2DG_M, + VIN_M, + TMU_3_M, + TMU_0_M, + + /* Priority */ + RCAN_P, + LBSCDMAC_P, + + /* Common */ + SDHI, + SSI, + SPI, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_VECT(DU, 0x3E0), + INTC_VECT(TMU00, 0x400), + INTC_VECT(TMU10, 0x420), + INTC_VECT(TMU20, 0x440), + INTC_VECT(TMU30, 0x480), + INTC_VECT(TMU40, 0x4A0), + INTC_VECT(TMU50, 0x4C0), + INTC_VECT(TMU51, 0x4E0), + INTC_VECT(TMU60, 0x500), + INTC_VECT(TMU70, 0x520), + INTC_VECT(TMU80, 0x540), + INTC_VECT(RESET_WDT, 0x560), + INTC_VECT(USB, 0x580), + INTC_VECT(HUDI, 0x600), + INTC_VECT(SHDMAC, 0x620), + INTC_VECT(SSI0, 0x6C0), + INTC_VECT(SSI1, 0x6E0), + INTC_VECT(SSI2, 0x700), + INTC_VECT(SSI3, 0x720), + INTC_VECT(VIN0, 0x740), + INTC_VECT(RGPVG, 0x760), + INTC_VECT(_2DG, 0x780), + INTC_VECT(MMC, 0x7A0), + INTC_VECT(HSPI, 0x7E0), + INTC_VECT(LBSCATA, 0x840), + INTC_VECT(I2C0, 0x860), + INTC_VECT(RCAN0, 0x880), + INTC_VECT(SCIF0, 0x8A0), + INTC_VECT(SCIF1, 0x8C0), + INTC_VECT(SCIF2, 0x900), + INTC_VECT(SCIF3, 0x920), + INTC_VECT(SCIF4, 0x940), + INTC_VECT(SCIF5, 0x960), + INTC_VECT(LBSCDMAC0, 0x9E0), + INTC_VECT(LBSCDMAC1, 0xA00), + INTC_VECT(LBSCDMAC2, 0xA20), + INTC_VECT(RCAN1, 0xA60), + INTC_VECT(SDHI0, 0xAE0), + INTC_VECT(SDHI1, 0xB00), + INTC_VECT(IEBUS, 0xB20), + INTC_VECT(HPBDMAC0_3, 0xB60), + INTC_VECT(HPBDMAC4_10, 0xB80), + INTC_VECT(HPBDMAC11_18, 0xBA0), + INTC_VECT(HPBDMAC19_22, 0xBC0), + INTC_VECT(HPBDMAC23_25_27_28, 0xBE0), + INTC_VECT(RTC, 0xC00), + INTC_VECT(VIN1, 0xC20), + INTC_VECT(LCDC, 0xC40), + INTC_VECT(SRC0, 0xC60), + INTC_VECT(SRC1, 0xC80), + INTC_VECT(GETHER, 0xCA0), + INTC_VECT(SDHI2, 0xCC0), + INTC_VECT(GPIO0_3, 0xCE0), + INTC_VECT(GPIO4_5, 0xD00), + INTC_VECT(STIF0, 0xD20), + INTC_VECT(STIF1, 0xD40), + INTC_VECT(ADMAC, 0xDA0), + INTC_VECT(HIF, 0xDC0), + INTC_VECT(FLCTL, 0xDE0), + INTC_VECT(ADC, 0xE00), + INTC_VECT(MTU2, 0xE20), + INTC_VECT(RSPI, 0xE40), + INTC_VECT(QSPI, 0xE60), + INTC_VECT(HSCIF, 0xFC0), + INTC_VECT(VEU3F_VE3, 0xF40), +}; + +static struct intc_group groups[] __initdata = { + /* Common */ + INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2), + INTC_GROUP(SPI, HSPI, RSPI, QSPI), + INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3), + + /* Mask group */ + INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */ + INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */ + INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, + HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */ + INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */ + INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */ + INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */ + INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, + HSCIF), /* 14 */ + INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */ + INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */ + INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */ + INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51, + TMU60, TMU60, TMU70, TMU80), /* 2 */ + INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */ + + /* Priority group*/ + INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */ + INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */ +}; + +static struct intc_mask_reg mask_registers[] __initdata = { + { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */ + { 0, + VEU3F_VE3, + SDHI, /* SDHI 0-2 */ + ADMAC, + FLCTL, + RESET_WDT, + HIF, + ADC, + MTU2, + STIF_M, /* STIF 0,1 */ + GPIO_M, /* GPIO 0-5*/ + GETHER, + HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */ + LBSCDMAC_M, /* LBSCDMAC 0 - 2 */ + RCAN_M, /* RCAN, IEBUS */ + SRC_M, /* SRC 0,1 */ + LBSCATA, + SCIF_M, /* SCIF 0-5, HSCIF */ + LCDC_M, /* LCDC, MIMLB */ + _2DG_M, /* 2DG, RGPVG */ + SPI, /* HSPI, RSPI, QSPI */ + VIN_M, /* VIN0, 1 */ + SSI, /* SSI 0-3 */ + USB, + SHDMAC, + HUDI, + MMC, + RTC, + I2C0, /* I2C */ /* I2C 0, 1*/ + TMU_3_M, /* TMU30 - TMU80 */ + TMU_0_M, /* TMU00 - TMU21 */ + DU } }, +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { 0xFF804000, 0, 32, 8, /* INT2PRI0 */ + { DU, TMU00, TMU10, TMU20 } }, + { 0xFF804004, 0, 32, 8, /* INT2PRI1 */ + { TMU30, TMU60, RTC, SDHI } }, + { 0xFF804008, 0, 32, 8, /* INT2PRI2 */ + { HUDI, SHDMAC, USB, SSI } }, + { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */ + { VIN0, SPI, _2DG, LBSCATA } }, + { 0xFF804010, 0, 32, 8, /* INT2PRI4 */ + { SCIF0, SCIF3, HSCIF, LCDC } }, + { 0xFF804014, 0, 32, 8, /* INT2PRI5 */ + { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } }, + { 0xFF804018, 0, 32, 8, /* INT2PRI6 */ + { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } }, + { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */ + { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } }, + { 0xFF804020, 0, 32, 8, /* INT2PRI8 */ + { 0 /* ADIF */, VIN1, RESET_WDT, HIF } }, + { 0xFF804024, 0, 32, 8, /* INT2PRI9 */ + { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } }, + { 0xFF804028, 0, 32, 8, /* INT2PRI10 */ + { STIF0, STIF1, VEU3F_VE3, GETHER } }, + { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */ + { MTU2, RGPVG, MIMLB, IEBUS } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups, + mask_registers, prio_registers, NULL); + +/* Support for external interrupt pins in IRQ mode */ + +static struct intc_vect irq3210_vectors[] __initdata = { + INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), + INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300), +}; + +static struct intc_sense_reg irq3210_sense_registers[] __initdata = { + { 0xFF80201C, 32, 2, /* ICR1 */ + { IRQ0, IRQ1, IRQ2, IRQ3, } }, +}; + +static struct intc_mask_reg irq3210_ack_registers[] __initdata = { + { 0xFF802024, 0, 32, /* INTREQ */ + { IRQ0, IRQ1, IRQ2, IRQ3, } }, +}; + +static struct intc_mask_reg irq3210_mask_registers[] __initdata = { + { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */ + { IRQ0, IRQ1, IRQ2, IRQ3, } }, +}; + +static struct intc_prio_reg irq3210_prio_registers[] __initdata = { + { 0xFF802010, 0, 32, 4, /* INTPRI */ + { IRQ0, IRQ1, IRQ2, IRQ3, } }, +}; + +static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210", + irq3210_vectors, NULL, + irq3210_mask_registers, irq3210_prio_registers, + irq3210_sense_registers, irq3210_ack_registers); + +/* External interrupt pins in IRL mode */ + +static struct intc_vect vectors_irl3210[] __initdata = { + INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), + INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), + INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), + INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), + INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), + INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), + INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), + INTC_VECT(IRL0_HHHL, 0x3c0), +}; + +static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210", + vectors_irl3210, NULL, mask_registers, NULL, NULL); + +#define INTC_ICR0 0xFF802000 +#define INTC_INTMSK0 0xFF802044 +#define INTC_INTMSK1 0xFF802048 +#define INTC_INTMSKCLR0 0xFF802064 +#define INTC_INTMSKCLR1 0xFF802068 + +void __init plat_irq_setup(void) +{ + /* disable IRQ3-0 */ + __raw_writel(0xF0000000, INTC_INTMSK0); + + /* disable IRL3-0 */ + __raw_writel(0x80000000, INTC_INTMSK1); + + /* select IRL mode for IRL3-0 */ + __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0); + + /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */ + __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); + + register_intc_controller(&intc_desc); +} + +void __init plat_irq_setup_pins(int mode) +{ + switch (mode) { + case IRQ_MODE_IRQ3210: + /* select IRQ mode for IRL3-0 */ + __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); + register_intc_controller(&intc_desc_irq3210); + break; + case IRQ_MODE_IRL3210: + /* enable IRL0-3 but don't provide any masking */ + __raw_writel(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0xf0000000, INTC_INTMSKCLR0); + break; + case IRQ_MODE_IRL3210_MASK: + /* enable IRL0-3 and mask using cpu intc controller */ + __raw_writel(0x80000000, INTC_INTMSKCLR0); + register_intc_controller(&intc_desc_irl3210); + break; + default: + BUG(); + } +} diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c new file mode 100644 index 00000000000..7b24ec4b409 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c @@ -0,0 +1,1247 @@ +/* + * SH7757 Setup + * + * Copyright (C) 2009, 2011 Renesas Solutions Corp. + * + * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial.h> +#include <linux/serial_sci.h> +#include <linux/io.h> +#include <linux/mm.h> +#include <linux/dma-mapping.h> +#include <linux/sh_timer.h> +#include <linux/sh_dma.h> +#include <linux/sh_intc.h> +#include <linux/usb/ohci_pdriver.h> +#include <cpu/dma-register.h> +#include <cpu/sh7757.h> + +static struct plat_sci_port scif2_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */ + DEFINE_RES_IRQ(evt2irq(0x700)), +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 0, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */ + DEFINE_RES_IRQ(evt2irq(0xb80)), +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 1, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, +}; + +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */ + DEFINE_RES_IRQ(evt2irq(0xf00)), +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 2, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct sh_timer_config tmu0_platform_data = { + .channels_mask = 3, +}; + +static struct resource tmu0_resources[] = { + DEFINE_RES_MEM(0xfe430000, 0x20), + DEFINE_RES_IRQ(evt2irq(0x580)), + DEFINE_RES_IRQ(evt2irq(0x5a0)), +}; + +static struct platform_device tmu0_device = { + .name = "sh-tmu", + .id = 0, + .dev = { + .platform_data = &tmu0_platform_data, + }, + .resource = tmu0_resources, + .num_resources = ARRAY_SIZE(tmu0_resources), +}; + +static struct resource spi0_resources[] = { + [0] = { + .start = 0xfe002000, + .end = 0xfe0020ff, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, + }, + [1] = { + .start = evt2irq(0xcc0), + .flags = IORESOURCE_IRQ, + }, +}; + +/* DMA */ +static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = { + { + .slave_id = SHDMA_SLAVE_SDHI_TX, + .addr = 0x1fe50030, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc5, + }, + { + .slave_id = SHDMA_SLAVE_SDHI_RX, + .addr = 0x1fe50030, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc6, + }, + { + .slave_id = SHDMA_SLAVE_MMCIF_TX, + .addr = 0x1fcb0034, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xd3, + }, + { + .slave_id = SHDMA_SLAVE_MMCIF_RX, + .addr = 0x1fcb0034, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xd7, + }, +}; + +static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = { + { + .slave_id = SHDMA_SLAVE_SCIF2_TX, + .addr = 0x1f4b000c, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, + { + .slave_id = SHDMA_SLAVE_SCIF2_RX, + .addr = 0x1f4b0014, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, + { + .slave_id = SHDMA_SLAVE_SCIF3_TX, + .addr = 0x1f4c000c, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, + { + .slave_id = SHDMA_SLAVE_SCIF3_RX, + .addr = 0x1f4c0014, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, + { + .slave_id = SHDMA_SLAVE_SCIF4_TX, + .addr = 0x1f4d000c, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x41, + }, + { + .slave_id = SHDMA_SLAVE_SCIF4_RX, + .addr = 0x1f4d0014, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x42, + }, + { + .slave_id = SHDMA_SLAVE_RSPI_TX, + .addr = 0xfe480004, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc1, + }, + { + .slave_id = SHDMA_SLAVE_RSPI_RX, + .addr = 0xfe480004, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc2, + }, +}; + +static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = { + { + .slave_id = SHDMA_SLAVE_RIIC0_TX, + .addr = 0x1e500012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, + { + .slave_id = SHDMA_SLAVE_RIIC0_RX, + .addr = 0x1e500013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, + { + .slave_id = SHDMA_SLAVE_RIIC1_TX, + .addr = 0x1e510012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, + { + .slave_id = SHDMA_SLAVE_RIIC1_RX, + .addr = 0x1e510013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, + { + .slave_id = SHDMA_SLAVE_RIIC2_TX, + .addr = 0x1e520012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xa1, + }, + { + .slave_id = SHDMA_SLAVE_RIIC2_RX, + .addr = 0x1e520013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xa2, + }, + { + .slave_id = SHDMA_SLAVE_RIIC3_TX, + .addr = 0x1e530012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xa9, + }, + { + .slave_id = SHDMA_SLAVE_RIIC3_RX, + .addr = 0x1e530013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xaf, + }, + { + .slave_id = SHDMA_SLAVE_RIIC4_TX, + .addr = 0x1e540012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xc5, + }, + { + .slave_id = SHDMA_SLAVE_RIIC4_RX, + .addr = 0x1e540013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xc6, + }, +}; + +static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = { + { + .slave_id = SHDMA_SLAVE_RIIC5_TX, + .addr = 0x1e550012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, + { + .slave_id = SHDMA_SLAVE_RIIC5_RX, + .addr = 0x1e550013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, + { + .slave_id = SHDMA_SLAVE_RIIC6_TX, + .addr = 0x1e560012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, + { + .slave_id = SHDMA_SLAVE_RIIC6_RX, + .addr = 0x1e560013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, + { + .slave_id = SHDMA_SLAVE_RIIC7_TX, + .addr = 0x1e570012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x41, + }, + { + .slave_id = SHDMA_SLAVE_RIIC7_RX, + .addr = 0x1e570013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x42, + }, + { + .slave_id = SHDMA_SLAVE_RIIC8_TX, + .addr = 0x1e580012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x45, + }, + { + .slave_id = SHDMA_SLAVE_RIIC8_RX, + .addr = 0x1e580013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x46, + }, + { + .slave_id = SHDMA_SLAVE_RIIC9_TX, + .addr = 0x1e590012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x51, + }, + { + .slave_id = SHDMA_SLAVE_RIIC9_RX, + .addr = 0x1e590013, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x52, + }, +}; + +static const struct sh_dmae_channel sh7757_dmae_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + +static const unsigned int ts_shift[] = TS_SHIFT; + +static struct sh_dmae_pdata dma0_platform_data = { + .slave = sh7757_dmae0_slaves, + .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves), + .channel = sh7757_dmae_channels, + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +static struct sh_dmae_pdata dma1_platform_data = { + .slave = sh7757_dmae1_slaves, + .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves), + .channel = sh7757_dmae_channels, + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +static struct sh_dmae_pdata dma2_platform_data = { + .slave = sh7757_dmae2_slaves, + .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves), + .channel = sh7757_dmae_channels, + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +static struct sh_dmae_pdata dma3_platform_data = { + .slave = sh7757_dmae3_slaves, + .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves), + .channel = sh7757_dmae_channels, + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +/* channel 0 to 5 */ +static struct resource sh7757_dmae0_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xff608020, + .end = 0xff60808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xff609000, + .end = 0xff60900b, + .flags = IORESOURCE_MEM, + }, + { + .name = "error_irq", + .start = evt2irq(0x640), + .end = evt2irq(0x640), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, +}; + +/* channel 6 to 11 */ +static struct resource sh7757_dmae1_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xff618020, + .end = 0xff61808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xff619000, + .end = 0xff61900b, + .flags = IORESOURCE_MEM, + }, + { + .name = "error_irq", + .start = evt2irq(0x640), + .end = evt2irq(0x640), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 4 */ + .start = evt2irq(0x7c0), + .end = evt2irq(0x7c0), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 5 */ + .start = evt2irq(0x7c0), + .end = evt2irq(0x7c0), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 6 */ + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 7 */ + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 8 */ + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 9 */ + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 10 */ + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 11 */ + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, +}; + +/* channel 12 to 17 */ +static struct resource sh7757_dmae2_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xff708020, + .end = 0xff70808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xff709000, + .end = 0xff70900b, + .flags = IORESOURCE_MEM, + }, + { + .name = "error_irq", + .start = evt2irq(0x2a60), + .end = evt2irq(0x2a60), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 12 to 16 */ + .start = evt2irq(0x2400), + .end = evt2irq(0x2480), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channel 17 */ + .start = evt2irq(0x24e0), + .end = evt2irq(0x24e0), + .flags = IORESOURCE_IRQ, + }, +}; + +/* channel 18 to 23 */ +static struct resource sh7757_dmae3_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xff718020, + .end = 0xff71808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xff719000, + .end = 0xff71900b, + .flags = IORESOURCE_MEM, + }, + { + .name = "error_irq", + .start = evt2irq(0x2a80), + .end = evt2irq(0x2a80), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 18 to 22 */ + .start = evt2irq(0x2500), + .end = evt2irq(0x2580), + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channel 23 */ + .start = evt2irq(0x2600), + .end = evt2irq(0x2600), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dma0_device = { + .name = "sh-dma-engine", + .id = 0, + .resource = sh7757_dmae0_resources, + .num_resources = ARRAY_SIZE(sh7757_dmae0_resources), + .dev = { + .platform_data = &dma0_platform_data, + }, +}; + +static struct platform_device dma1_device = { + .name = "sh-dma-engine", + .id = 1, + .resource = sh7757_dmae1_resources, + .num_resources = ARRAY_SIZE(sh7757_dmae1_resources), + .dev = { + .platform_data = &dma1_platform_data, + }, +}; + +static struct platform_device dma2_device = { + .name = "sh-dma-engine", + .id = 2, + .resource = sh7757_dmae2_resources, + .num_resources = ARRAY_SIZE(sh7757_dmae2_resources), + .dev = { + .platform_data = &dma2_platform_data, + }, +}; + +static struct platform_device dma3_device = { + .name = "sh-dma-engine", + .id = 3, + .resource = sh7757_dmae3_resources, + .num_resources = ARRAY_SIZE(sh7757_dmae3_resources), + .dev = { + .platform_data = &dma3_platform_data, + }, +}; + +static struct platform_device spi0_device = { + .name = "sh_spi", + .id = 0, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(spi0_resources), + .resource = spi0_resources, +}; + +static struct resource spi1_resources[] = { + { + .start = 0xffd8ee70, + .end = 0xffd8eeff, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + { + .start = evt2irq(0x8c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device spi1_device = { + .name = "sh_spi", + .id = 1, + .num_resources = ARRAY_SIZE(spi1_resources), + .resource = spi1_resources, +}; + +static struct resource rspi_resources[] = { + { + .start = 0xfe480000, + .end = 0xfe4800ff, + .flags = IORESOURCE_MEM, + }, + { + .start = evt2irq(0x1d80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rspi_device = { + .name = "rspi", + .id = 2, + .num_resources = ARRAY_SIZE(rspi_resources), + .resource = rspi_resources, +}; + +static struct resource usb_ehci_resources[] = { + [0] = { + .start = 0xfe4f1000, + .end = 0xfe4f10ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x920), + .end = evt2irq(0x920), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb_ehci_device = { + .name = "sh_ehci", + .id = -1, + .dev = { + .dma_mask = &usb_ehci_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(usb_ehci_resources), + .resource = usb_ehci_resources, +}; + +static struct resource usb_ohci_resources[] = { + [0] = { + .start = 0xfe4f1800, + .end = 0xfe4f18ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x920), + .end = evt2irq(0x920), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct usb_ohci_pdata usb_ohci_pdata; + +static struct platform_device usb_ohci_device = { + .name = "ohci-platform", + .id = -1, + .dev = { + .dma_mask = &usb_ohci_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &usb_ohci_pdata, + }, + .num_resources = ARRAY_SIZE(usb_ohci_resources), + .resource = usb_ohci_resources, +}; + +static struct platform_device *sh7757_devices[] __initdata = { + &scif2_device, + &scif3_device, + &scif4_device, + &tmu0_device, + &dma0_device, + &dma1_device, + &dma2_device, + &dma3_device, + &spi0_device, + &spi1_device, + &rspi_device, + &usb_ehci_device, + &usb_ohci_device, +}; + +static int __init sh7757_devices_setup(void) +{ + return platform_add_devices(sh7757_devices, + ARRAY_SIZE(sh7757_devices)); +} +arch_initcall(sh7757_devices_setup); + +static struct platform_device *sh7757_early_devices[] __initdata = { + &scif2_device, + &scif3_device, + &scif4_device, + &tmu0_device, +}; + +void __init plat_early_device_setup(void) +{ + early_platform_add_devices(sh7757_early_devices, + ARRAY_SIZE(sh7757_early_devices)); +} + +enum { + UNUSED = 0, + + /* interrupt sources */ + + IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, + IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, + IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, + IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, + + IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, + IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, + IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, + IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, + + SDHI, DVC, + IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15, + TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, + HUDI, + ARC4, + DMAC0_5, DMAC6_7, DMAC8_11, + SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, + USB0, USB1, + JMC, + SPI0, SPI1, + TMR01, TMR23, TMR45, + FRT, + LPC, LPC5, LPC6, LPC7, LPC8, + PECI0, PECI1, PECI2, PECI3, PECI4, PECI5, + ETHERC, + ADC0, ADC1, + SIM, + IIC0_0, IIC0_1, IIC0_2, IIC0_3, + IIC1_0, IIC1_1, IIC1_2, IIC1_3, + IIC2_0, IIC2_1, IIC2_2, IIC2_3, + IIC3_0, IIC3_1, IIC3_2, IIC3_3, + IIC4_0, IIC4_1, IIC4_2, IIC4_3, + IIC5_0, IIC5_1, IIC5_2, IIC5_3, + IIC6_0, IIC6_1, IIC6_2, IIC6_3, + IIC7_0, IIC7_1, IIC7_2, IIC7_3, + IIC8_0, IIC8_1, IIC8_2, IIC8_3, + IIC9_0, IIC9_1, IIC9_2, IIC9_3, + ONFICTL, + MMC1, MMC2, + ECCU, + PCIC, + G200, + RSPI, + SGPIO, + DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19, + DMINT20, DMINT21, DMINT22, DMINT23, + DDRECC, + TSIP, + PCIE_BRIDGE, + WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B, + GETHER0, GETHER1, GETHER2, + PBIA, PBIB, PBIC, + DMAE2, DMAE3, + SERMUX2, SERMUX3, + + /* interrupt groups */ + + TMU012, TMU345, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0), + INTC_VECT(SDHI, 0x4c0), + INTC_VECT(DVC, 0x4e0), + INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), + INTC_VECT(IRQ10, 0x540), + INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), + INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), + INTC_VECT(HUDI, 0x600), + INTC_VECT(ARC4, 0x620), + INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660), + INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0), + INTC_VECT(DMAC0_5, 0x6c0), + INTC_VECT(IRQ11, 0x6e0), + INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), + INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), + INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0), + INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0), + INTC_VECT(USB0, 0x840), + INTC_VECT(IRQ12, 0x880), + INTC_VECT(JMC, 0x8a0), + INTC_VECT(SPI1, 0x8c0), + INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900), + INTC_VECT(USB1, 0x920), + INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), + INTC_VECT(TMR45, 0xa40), + INTC_VECT(FRT, 0xa80), + INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), + INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), + INTC_VECT(LPC, 0xb20), + INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), + INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), + INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), + INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20), + INTC_VECT(PECI2, 0xc40), + INTC_VECT(IRQ15, 0xc60), + INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), + INTC_VECT(SPI0, 0xcc0), + INTC_VECT(ADC1, 0xce0), + INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20), + INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60), + INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), + INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), + INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), + INTC_VECT(TMU5, 0xe40), + INTC_VECT(ADC0, 0xe60), + INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20), + INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60), + INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420), + INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460), + INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0), + INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520), + INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560), + INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600), + INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640), + INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700), + INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800), + INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840), + INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), + INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), + INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), + INTC_VECT(IIC6_2, 0x1920), + INTC_VECT(ONFICTL, 0x1960), + INTC_VECT(IIC6_3, 0x1980), + INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), + INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), + INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), + INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), + INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), + INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), + INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80), + INTC_VECT(ECCU, 0x1cc0), + INTC_VECT(PCIC, 0x1ce0), + INTC_VECT(G200, 0x1d00), + INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0), + INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0), + INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0), + INTC_VECT(PECI5, 0x1f00), + INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0), + INTC_VECT(SGPIO, 0x1fc0), + INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420), + INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460), + INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0), + INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520), + INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560), + INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600), + INTC_VECT(DDRECC, 0x2620), + INTC_VECT(TSIP, 0x2640), + INTC_VECT(PCIE_BRIDGE, 0x27c0), + INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820), + INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860), + INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0), + INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0), + INTC_VECT(WDT8B, 0x2900), + INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980), + INTC_VECT(GETHER2, 0x29a0), + INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20), + INTC_VECT(PBIC, 0x2a40), + INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80), + INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40), + INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80), + INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20), +}; + +static struct intc_group groups[] __initdata = { + INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), + INTC_GROUP(TMU345, TMU3, TMU4, TMU5), +}; + +static struct intc_mask_reg mask_registers[] __initdata = { + { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, + + { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ + { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, + IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, + IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, + IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, + IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, + IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, + IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, + IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, + + { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45, + TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5, + HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012 + } }, + + { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ + { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, + IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, + ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1, + ARC4, 0, SPI1, JMC, 0, 0, 0, DVC + } }, + + { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ + { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0, + 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, + IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, + IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2 + } }, + + { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */ + { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2, + IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, + PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3, + IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 + } }, + + { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */ + { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0, + 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC, + PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP, + DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22 + } }, + + { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */ + { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0, + DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0, + 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8, + DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17 + } }, +}; + +#define INTPRI 0xffd00010 +#define INT2PRI0 0xffd40000 +#define INT2PRI1 0xffd40004 +#define INT2PRI2 0xffd40008 +#define INT2PRI3 0xffd4000c +#define INT2PRI4 0xffd40010 +#define INT2PRI5 0xffd40014 +#define INT2PRI6 0xffd40018 +#define INT2PRI7 0xffd4001c +#define INT2PRI8 0xffd400a0 +#define INT2PRI9 0xffd400a4 +#define INT2PRI10 0xffd400a8 +#define INT2PRI11 0xffd400ac +#define INT2PRI12 0xffd400b0 +#define INT2PRI13 0xffd400b4 +#define INT2PRI14 0xffd400b8 +#define INT2PRI15 0xffd400bc +#define INT2PRI16 0xffd10000 +#define INT2PRI17 0xffd10004 +#define INT2PRI18 0xffd10008 +#define INT2PRI19 0xffd1000c +#define INT2PRI20 0xffd10010 +#define INT2PRI21 0xffd10014 +#define INT2PRI22 0xffd10018 +#define INT2PRI23 0xffd1001c +#define INT2PRI24 0xffd100a0 +#define INT2PRI25 0xffd100a4 +#define INT2PRI26 0xffd100a8 +#define INT2PRI27 0xffd100ac +#define INT2PRI28 0xffd100b0 +#define INT2PRI29 0xffd100b4 +#define INT2PRI30 0xffd100b8 +#define INT2PRI31 0xffd100bc +#define INT2PRI32 0xffd20000 +#define INT2PRI33 0xffd20004 +#define INT2PRI34 0xffd20008 +#define INT2PRI35 0xffd2000c +#define INT2PRI36 0xffd20010 +#define INT2PRI37 0xffd20014 +#define INT2PRI38 0xffd20018 +#define INT2PRI39 0xffd2001c +#define INT2PRI40 0xffd200a0 +#define INT2PRI41 0xffd200a4 +#define INT2PRI42 0xffd200a8 +#define INT2PRI43 0xffd200ac +#define INT2PRI44 0xffd200b0 +#define INT2PRI45 0xffd200b4 +#define INT2PRI46 0xffd200b8 +#define INT2PRI47 0xffd200bc + +static struct intc_prio_reg prio_registers[] __initdata = { + { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, + IRQ4, IRQ5, IRQ6, IRQ7 } }, + + { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, + { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, + { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } }, + { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } }, + { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, + { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } }, + { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } }, + { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, + { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, + { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, + { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } }, + { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } }, + { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, + { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, + + { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, + { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } }, + { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, + { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, + { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, + { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, + { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } }, + { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } }, + { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } }, + { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, + { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } }, + { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } }, + { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } }, + { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, + { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } }, + { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, + { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } }, + { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } }, + { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } }, + { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } }, + { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } }, + { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } }, + { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } }, + { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } }, + { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } }, + { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } }, + { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } }, + { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } }, + { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } }, + { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } }, + { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } }, + { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } }, +}; + +static struct intc_sense_reg sense_registers_irq8to15[] __initdata = { + { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12, + IRQ11, IRQ10, IRQ9, IRQ8 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, + mask_registers, prio_registers, + sense_registers_irq8to15); + +/* Support for external interrupt pins in IRQ mode */ +static struct intc_vect vectors_irq0123[] __initdata = { + INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), + INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), +}; + +static struct intc_vect vectors_irq4567[] __initdata = { + INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340), + INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), +}; + +static struct intc_sense_reg sense_registers[] __initdata = { + { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, + IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static struct intc_mask_reg ack_registers[] __initdata = { + { 0xffd00024, 0, 32, /* INTREQ */ + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123", + vectors_irq0123, NULL, mask_registers, + prio_registers, sense_registers, ack_registers); + +static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567", + vectors_irq4567, NULL, mask_registers, + prio_registers, sense_registers, ack_registers); + +/* External interrupt pins in IRL mode */ +static struct intc_vect vectors_irl0123[] __initdata = { + INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), + INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), + INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), + INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), + INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), + INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), + INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), + INTC_VECT(IRL0_HHHL, 0x3c0), +}; + +static struct intc_vect vectors_irl4567[] __initdata = { + INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220), + INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260), + INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0), + INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0), + INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320), + INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360), + INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0), + INTC_VECT(IRL4_HHHL, 0x3c0), +}; + +static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123, + NULL, mask_registers, NULL, NULL); + +static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567, + NULL, mask_registers, NULL, NULL); + +#define INTC_ICR0 0xffd00000 +#define INTC_INTMSK0 0xffd00044 +#define INTC_INTMSK1 0xffd00048 +#define INTC_INTMSK2 0xffd40080 +#define INTC_INTMSKCLR1 0xffd00068 +#define INTC_INTMSKCLR2 0xffd40084 + +void __init plat_irq_setup(void) +{ + /* disable IRQ3-0 + IRQ7-4 */ + __raw_writel(0xff000000, INTC_INTMSK0); + + /* disable IRL3-0 + IRL7-4 */ + __raw_writel(0xc0000000, INTC_INTMSK1); + __raw_writel(0xfffefffe, INTC_INTMSK2); + + /* select IRL mode for IRL3-0 + IRL7-4 */ + __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); + + /* disable holding function, ie enable "SH-4 Mode" */ + __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); + + register_intc_controller(&intc_desc); +} + +void __init plat_irq_setup_pins(int mode) +{ + switch (mode) { + case IRQ_MODE_IRQ7654: + /* select IRQ mode for IRL7-4 */ + __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); + register_intc_controller(&intc_desc_irq4567); + break; + case IRQ_MODE_IRQ3210: + /* select IRQ mode for IRL3-0 */ + __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); + register_intc_controller(&intc_desc_irq0123); + break; + case IRQ_MODE_IRL7654: + /* enable IRL7-4 but don't provide any masking */ + __raw_writel(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x0000fffe, INTC_INTMSKCLR2); + break; + case IRQ_MODE_IRL3210: + /* enable IRL0-3 but don't provide any masking */ + __raw_writel(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0xfffe0000, INTC_INTMSKCLR2); + break; + case IRQ_MODE_IRL7654_MASK: + /* enable IRL7-4 and mask using cpu intc controller */ + __raw_writel(0x40000000, INTC_INTMSKCLR1); + register_intc_controller(&intc_desc_irl4567); + break; + case IRQ_MODE_IRL3210_MASK: + /* enable IRL0-3 and mask using cpu intc controller */ + __raw_writel(0x80000000, INTC_INTMSKCLR1); + register_intc_controller(&intc_desc_irl0123); + break; + default: + BUG(); + } +} + +void __init plat_mem_setup(void) +{ +} diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index f1e0c0d36da..5a47d670dde 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c @@ -13,8 +13,76 @@ #include <linux/init.h> #include <linux/serial.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> #include <linux/io.h> #include <linux/serial_sci.h> +#include <linux/usb/ohci_pdriver.h> + +static struct plat_sci_port scif0_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe08000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xb80)), +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xf00)), +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, + }, +}; static struct resource rtc_resources[] = { [0] = { @@ -24,7 +92,7 @@ static struct resource rtc_resources[] = { }, [1] = { /* Shared Period/Carry/Alarm IRQ */ - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -36,35 +104,6 @@ static struct platform_device rtc_device = { .resource = rtc_resources, }; -static struct plat_sci_port sci_platform_data[] = { - { - .mapbase = 0xffe00000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, - }, { - .mapbase = 0xffe08000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 76, 76, 76, 76 }, - }, { - .mapbase = 0xffe10000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 104, 104, 104, 104 }, - }, { - .flags = 0, - } -}; - -static struct platform_device sci_device = { - .name = "sh-sci", - .id = -1, - .dev = { - .platform_data = sci_platform_data, - }, -}; - static struct resource usb_ohci_resources[] = { [0] = { .start = 0xffec8000, @@ -72,19 +111,23 @@ static struct resource usb_ohci_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 83, - .end = 83, + .start = evt2irq(0xc60), + .end = evt2irq(0xc60), .flags = IORESOURCE_IRQ, }, }; static u64 usb_ohci_dma_mask = 0xffffffffUL; + +static struct usb_ohci_pdata usb_ohci_pdata; + static struct platform_device usb_ohci_device = { - .name = "sh_ohci", + .name = "ohci-platform", .id = -1, .dev = { .dma_mask = &usb_ohci_dma_mask, .coherent_dma_mask = 0xffffffff, + .platform_data = &usb_ohci_pdata, }, .num_resources = ARRAY_SIZE(usb_ohci_resources), .resource = usb_ohci_resources, @@ -97,8 +140,8 @@ static struct resource usbf_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 84, - .end = 84, + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), .flags = IORESOURCE_IRQ, }, }; @@ -115,28 +158,18 @@ static struct platform_device usbf_device = { }; static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", - .clockevent_rating = 200, + .channels_mask = 7, }; static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 28, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0xffd80000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x580)), + DEFINE_RES_IRQ(evt2irq(0x5a0)), + DEFINE_RES_IRQ(evt2irq(0x5c0)), }; static struct platform_device tmu0_device = { - .name = "sh_tmu", + .name = "sh-tmu", .id = 0, .dev = { .platform_data = &tmu0_platform_data, @@ -146,28 +179,18 @@ static struct platform_device tmu0_device = { }; static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", - .clocksource_rating = 200, + .channels_mask = 7, }; static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 29, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0xffd88000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0xe00)), + DEFINE_RES_IRQ(evt2irq(0xe20)), + DEFINE_RES_IRQ(evt2irq(0xe40)), }; static struct platform_device tmu1_device = { - .name = "sh_tmu", + .name = "sh-tmu", .id = 1, .dev = { .platform_data = &tmu1_platform_data, @@ -176,135 +199,13 @@ static struct platform_device tmu1_device = { .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", -}; - -static struct resource tmu2_resources[] = { - [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 30, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu2_device = { - .name = "sh_tmu", - .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, - }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), -}; - -static struct sh_timer_config tmu3_platform_data = { - .name = "TMU3", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", -}; - -static struct resource tmu3_resources[] = { - [0] = { - .name = "TMU3", - .start = 0xffd88008, - .end = 0xffd88013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 96, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu3_device = { - .name = "sh_tmu", - .id = 3, - .dev = { - .platform_data = &tmu3_platform_data, - }, - .resource = tmu3_resources, - .num_resources = ARRAY_SIZE(tmu3_resources), -}; - -static struct sh_timer_config tmu4_platform_data = { - .name = "TMU4", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", -}; - -static struct resource tmu4_resources[] = { - [0] = { - .name = "TMU4", - .start = 0xffd88014, - .end = 0xffd8801f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 97, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu4_device = { - .name = "sh_tmu", - .id = 4, - .dev = { - .platform_data = &tmu4_platform_data, - }, - .resource = tmu4_resources, - .num_resources = ARRAY_SIZE(tmu4_resources), -}; - -static struct sh_timer_config tmu5_platform_data = { - .name = "TMU5", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", -}; - -static struct resource tmu5_resources[] = { - [0] = { - .name = "TMU5", - .start = 0xffd88020, - .end = 0xffd8802b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 98, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu5_device = { - .name = "sh_tmu", - .id = 5, - .dev = { - .platform_data = &tmu5_platform_data, - }, - .resource = tmu5_resources, - .num_resources = ARRAY_SIZE(tmu5_resources), -}; - static struct platform_device *sh7763_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, &rtc_device, - &sci_device, &usb_ohci_device, &usbf_device, }; @@ -314,15 +215,14 @@ static int __init sh7763_devices_setup(void) return platform_add_devices(sh7763_devices, ARRAY_SIZE(sh7763_devices)); } -__initcall(sh7763_devices_setup); +arch_initcall(sh7763_devices_setup); static struct platform_device *sh7763_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, }; void __init plat_early_device_setup(void) @@ -517,11 +417,11 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors, void __init plat_irq_setup(void) { /* disable IRQ7-0 */ - ctrl_outl(0xff000000, INTC_INTMSK0); + __raw_writel(0xff000000, INTC_INTMSK0); /* disable IRL3-0 + IRL7-4 */ - ctrl_outl(0xc0000000, INTC_INTMSK1); - ctrl_outl(0xfffefffe, INTC_INTMSK2); + __raw_writel(0xc0000000, INTC_INTMSK1); + __raw_writel(0xfffefffe, INTC_INTMSK2); register_intc_controller(&intc_desc); } @@ -531,27 +431,27 @@ void __init plat_irq_setup_pins(int mode) switch (mode) { case IRQ_MODE_IRQ: /* select IRQ mode for IRL3-0 + IRL7-4 */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); register_intc_controller(&intc_irq_desc); break; case IRQ_MODE_IRL7654: /* enable IRL7-4 but don't provide any masking */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); - ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); + __raw_writel(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x0000fffe, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL3210: /* enable IRL0-3 but don't provide any masking */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); - ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); + __raw_writel(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0xfffe0000, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL7654_MASK: /* enable IRL7-4 and mask using cpu intc controller */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x40000000, INTC_INTMSKCLR1); register_intc_controller(&intc_irl7654_desc); break; case IRQ_MODE_IRL3210_MASK: /* enable IRL0-3 and mask using cpu intc controller */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0x80000000, INTC_INTMSKCLR1); register_intc_controller(&intc_irl3210_desc); break; default: diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 1e86209db28..e9b532a76c3 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c @@ -12,355 +12,296 @@ #include <linux/serial.h> #include <linux/serial_sci.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> #include <linux/io.h> -static struct plat_sci_port sci_platform_data[] = { - { - .mapbase = 0xff923000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 61, 61, 61, 61 }, - }, { - .mapbase = 0xff924000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 62, 62, 62, 62 }, - }, { - .mapbase = 0xff925000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 63, 63, 63, 63 }, - }, { - .mapbase = 0xff926000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 64, 64, 64, 64 }, - }, { - .mapbase = 0xff927000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 65, 65, 65, 65 }, - }, { - .mapbase = 0xff928000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 66, 66, 66, 66 }, - }, { - .mapbase = 0xff929000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 67, 67, 67, 67 }, - }, { - .mapbase = 0xff92a000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 68, 68, 68, 68 }, - }, { - .mapbase = 0xff92b000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 69, 69, 69, 69 }, - }, { - .mapbase = 0xff92c000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 70, 70, 70, 70 }, - }, { - .flags = 0, - } +static struct plat_sci_port scif0_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xff923000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9a0)), }; -static struct platform_device sci_device = { +static struct platform_device scif0_device = { .name = "sh-sci", - .id = -1, + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { - .platform_data = sci_platform_data, + .platform_data = &scif0_platform_data, }, }; -static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", - .clockevent_rating = 200, +static struct plat_sci_port scif1_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, }; -static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 16, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xff924000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9c0)), }; -static struct platform_device tmu0_device = { - .name = "sh_tmu", - .id = 0, - .dev = { - .platform_data = &tmu0_platform_data, +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, }, - .resource = tmu0_resources, - .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", - .clocksource_rating = 200, +static struct plat_sci_port scif2_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, }; -static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 17, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xff925000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9e0)), }; -static struct platform_device tmu1_device = { - .name = "sh_tmu", - .id = 1, - .dev = { - .platform_data = &tmu1_platform_data, +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, }, - .resource = tmu1_resources, - .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", +static struct plat_sci_port scif3_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, }; -static struct resource tmu2_resources[] = { - [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 18, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xff926000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa00)), }; -static struct platform_device tmu2_device = { - .name = "sh_tmu", - .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), + .dev = { + .platform_data = &scif3_platform_data, }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), }; -static struct sh_timer_config tmu3_platform_data = { - .name = "TMU3", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", +static struct plat_sci_port scif4_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, }; -static struct resource tmu3_resources[] = { - [0] = { - .name = "TMU3", - .start = 0xffd81008, - .end = 0xffd81013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 19, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xff927000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa20)), }; -static struct platform_device tmu3_device = { - .name = "sh_tmu", - .id = 3, - .dev = { - .platform_data = &tmu3_platform_data, +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), + .dev = { + .platform_data = &scif4_platform_data, }, - .resource = tmu3_resources, - .num_resources = ARRAY_SIZE(tmu3_resources), }; -static struct sh_timer_config tmu4_platform_data = { - .name = "TMU4", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", +static struct plat_sci_port scif5_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, }; -static struct resource tmu4_resources[] = { - [0] = { - .name = "TMU4", - .start = 0xffd81014, - .end = 0xffd8101f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 20, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xff928000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa40)), }; -static struct platform_device tmu4_device = { - .name = "sh_tmu", - .id = 4, - .dev = { - .platform_data = &tmu4_platform_data, +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), + .dev = { + .platform_data = &scif5_platform_data, }, - .resource = tmu4_resources, - .num_resources = ARRAY_SIZE(tmu4_resources), }; -static struct sh_timer_config tmu5_platform_data = { - .name = "TMU5", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", +static struct plat_sci_port scif6_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, }; -static struct resource tmu5_resources[] = { - [0] = { - .name = "TMU5", - .start = 0xffd81020, - .end = 0xffd8102f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 21, - .flags = IORESOURCE_IRQ, +static struct resource scif6_resources[] = { + DEFINE_RES_MEM(0xff929000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa60)), +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .resource = scif6_resources, + .num_resources = ARRAY_SIZE(scif6_resources), + .dev = { + .platform_data = &scif6_platform_data, }, }; -static struct platform_device tmu5_device = { - .name = "sh_tmu", - .id = 5, - .dev = { - .platform_data = &tmu5_platform_data, +static struct plat_sci_port scif7_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, +}; + +static struct resource scif7_resources[] = { + DEFINE_RES_MEM(0xff92a000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa80)), +}; + +static struct platform_device scif7_device = { + .name = "sh-sci", + .id = 7, + .resource = scif7_resources, + .num_resources = ARRAY_SIZE(scif7_resources), + .dev = { + .platform_data = &scif7_platform_data, }, - .resource = tmu5_resources, - .num_resources = ARRAY_SIZE(tmu5_resources), }; -static struct sh_timer_config tmu6_platform_data = { - .name = "TMU6", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", +static struct plat_sci_port scif8_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, +}; + +static struct resource scif8_resources[] = { + DEFINE_RES_MEM(0xff92b000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xaa0)), }; -static struct resource tmu6_resources[] = { - [0] = { - .name = "TMU6", - .start = 0xffd82008, - .end = 0xffd82013, - .flags = IORESOURCE_MEM, +static struct platform_device scif8_device = { + .name = "sh-sci", + .id = 8, + .resource = scif8_resources, + .num_resources = ARRAY_SIZE(scif8_resources), + .dev = { + .platform_data = &scif8_platform_data, }, - [1] = { - .start = 22, - .flags = IORESOURCE_IRQ, +}; + +static struct plat_sci_port scif9_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .type = PORT_SCIF, +}; + +static struct resource scif9_resources[] = { + DEFINE_RES_MEM(0xff92c000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xac0)), +}; + +static struct platform_device scif9_device = { + .name = "sh-sci", + .id = 9, + .resource = scif9_resources, + .num_resources = ARRAY_SIZE(scif9_resources), + .dev = { + .platform_data = &scif9_platform_data, }, }; -static struct platform_device tmu6_device = { - .name = "sh_tmu", - .id = 6, +static struct sh_timer_config tmu0_platform_data = { + .channels_mask = 7, +}; + +static struct resource tmu0_resources[] = { + DEFINE_RES_MEM(0xffd80000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x400)), + DEFINE_RES_IRQ(evt2irq(0x420)), + DEFINE_RES_IRQ(evt2irq(0x440)), +}; + +static struct platform_device tmu0_device = { + .name = "sh-tmu", + .id = 0, .dev = { - .platform_data = &tmu6_platform_data, + .platform_data = &tmu0_platform_data, }, - .resource = tmu6_resources, - .num_resources = ARRAY_SIZE(tmu6_resources), + .resource = tmu0_resources, + .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct sh_timer_config tmu7_platform_data = { - .name = "TMU7", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", +static struct sh_timer_config tmu1_platform_data = { + .channels_mask = 7, }; -static struct resource tmu7_resources[] = { - [0] = { - .name = "TMU7", - .start = 0xffd82014, - .end = 0xffd8201f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 23, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu1_resources[] = { + DEFINE_RES_MEM(0xffd81000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x460)), + DEFINE_RES_IRQ(evt2irq(0x480)), + DEFINE_RES_IRQ(evt2irq(0x4a0)), }; -static struct platform_device tmu7_device = { - .name = "sh_tmu", - .id = 7, +static struct platform_device tmu1_device = { + .name = "sh-tmu", + .id = 1, .dev = { - .platform_data = &tmu7_platform_data, + .platform_data = &tmu1_platform_data, }, - .resource = tmu7_resources, - .num_resources = ARRAY_SIZE(tmu7_resources), + .resource = tmu1_resources, + .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu8_platform_data = { - .name = "TMU8", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", +static struct sh_timer_config tmu2_platform_data = { + .channels_mask = 7, }; -static struct resource tmu8_resources[] = { - [0] = { - .name = "TMU8", - .start = 0xffd82020, - .end = 0xffd8202b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 24, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu2_resources[] = { + DEFINE_RES_MEM(0xffd82000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x4c0)), + DEFINE_RES_IRQ(evt2irq(0x4e0)), + DEFINE_RES_IRQ(evt2irq(0x500)), }; -static struct platform_device tmu8_device = { - .name = "sh_tmu", - .id = 8, +static struct platform_device tmu2_device = { + .name = "sh-tmu", + .id = 2, .dev = { - .platform_data = &tmu8_platform_data, + .platform_data = &tmu2_platform_data, }, - .resource = tmu8_resources, - .num_resources = ARRAY_SIZE(tmu8_resources), + .resource = tmu2_resources, + .num_resources = ARRAY_SIZE(tmu2_resources), }; static struct platform_device *sh7770_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &scif8_device, + &scif9_device, &tmu0_device, &tmu1_device, &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, - &tmu6_device, - &tmu7_device, - &tmu8_device, - &sci_device, }; static int __init sh7770_devices_setup(void) @@ -368,18 +309,22 @@ static int __init sh7770_devices_setup(void) return platform_add_devices(sh7770_devices, ARRAY_SIZE(sh7770_devices)); } -__initcall(sh7770_devices_setup); +arch_initcall(sh7770_devices_setup); static struct platform_device *sh7770_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &scif8_device, + &scif9_device, &tmu0_device, &tmu1_device, &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, - &tmu6_device, - &tmu7_device, - &tmu8_device, }; void __init plat_early_device_setup(void) @@ -589,17 +534,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, void __init plat_irq_setup(void) { /* disable IRQ7-0 */ - ctrl_outl(0xff000000, INTC_INTMSK0); + __raw_writel(0xff000000, INTC_INTMSK0); /* disable IRL3-0 + IRL7-4 */ - ctrl_outl(0xc0000000, INTC_INTMSK1); - ctrl_outl(0xfffefffe, INTC_INTMSK2); + __raw_writel(0xc0000000, INTC_INTMSK1); + __raw_writel(0xfffefffe, INTC_INTMSK2); /* select IRL mode for IRL3-0 + IRL7-4 */ - ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); /* disable holding function, ie enable "SH-4 Mode" */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); register_intc_controller(&intc_desc); } @@ -609,27 +554,27 @@ void __init plat_irq_setup_pins(int mode) switch (mode) { case IRQ_MODE_IRQ: /* select IRQ mode for IRL3-0 + IRL7-4 */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); register_intc_controller(&intc_irq_desc); break; case IRQ_MODE_IRL7654: /* enable IRL7-4 but don't provide any masking */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); - ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); + __raw_writel(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x0000fffe, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL3210: /* enable IRL0-3 but don't provide any masking */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); - ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); + __raw_writel(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0xfffe0000, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL7654_MASK: /* enable IRL7-4 and mask using cpu intc controller */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x40000000, INTC_INTMSKCLR1); register_intc_controller(&intc_irl7654_desc); break; case IRQ_MODE_IRL3210_MASK: /* enable IRL0-3 and mask using cpu intc controller */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0x80000000, INTC_INTMSKCLR1); register_intc_controller(&intc_irl3210_desc); break; default: diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index 715e05b431e..3ee7dd9b3a6 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c @@ -12,31 +12,68 @@ #include <linux/serial.h> #include <linux/io.h> #include <linux/serial_sci.h> +#include <linux/sh_dma.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> +#include <cpu/dma-register.h> -static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", - .clockevent_rating = 200, +static struct plat_sci_port scif0_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, - .flags = IORESOURCE_MEM, +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, }, - [1] = { - .start = 28, - .flags = IORESOURCE_IRQ, +}; + +static struct plat_sci_port scif1_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xb80)), +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, }, }; +static struct sh_timer_config tmu0_platform_data = { + .channels_mask = 7, +}; + +static struct resource tmu0_resources[] = { + DEFINE_RES_MEM(0xffd80000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x580)), + DEFINE_RES_IRQ(evt2irq(0x5a0)), + DEFINE_RES_IRQ(evt2irq(0x5c0)), +}; + static struct platform_device tmu0_device = { - .name = "sh_tmu", + .name = "sh-tmu", .id = 0, .dev = { .platform_data = &tmu0_platform_data, @@ -46,28 +83,18 @@ static struct platform_device tmu0_device = { }; static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", - .clocksource_rating = 200, + .channels_mask = 7, }; static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 29, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(0xffdc0000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0xe00)), + DEFINE_RES_IRQ(evt2irq(0xe20)), + DEFINE_RES_IRQ(evt2irq(0xe40)), }; static struct platform_device tmu1_device = { - .name = "sh_tmu", + .name = "sh-tmu", .id = 1, .dev = { .platform_data = &tmu1_platform_data, @@ -76,179 +103,170 @@ static struct platform_device tmu1_device = { .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", -}; - -static struct resource tmu2_resources[] = { +static struct resource rtc_resources[] = { [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002f, - .flags = IORESOURCE_MEM, + .start = 0xffe80000, + .end = 0xffe80000 + 0x58 - 1, + .flags = IORESOURCE_IO, }, [1] = { - .start = 30, + /* Shared Period/Carry/Alarm IRQ */ + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; -static struct platform_device tmu2_device = { - .name = "sh_tmu", - .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, - }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, }; -static struct sh_timer_config tmu3_platform_data = { - .name = "TMU3", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", +/* DMA */ +static const struct sh_dmae_channel sh7780_dmae0_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } }; -static struct resource tmu3_resources[] = { - [0] = { - .name = "TMU3", - .start = 0xffdc0008, - .end = 0xffdc0013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 96, - .flags = IORESOURCE_IRQ, - }, +static const struct sh_dmae_channel sh7780_dmae1_channels[] = { + { + .offset = 0, + }, { + .offset = 0x10, + }, { + .offset = 0x20, + }, { + .offset = 0x30, + }, { + .offset = 0x50, + }, { + .offset = 0x60, + } }; -static struct platform_device tmu3_device = { - .name = "sh_tmu", - .id = 3, - .dev = { - .platform_data = &tmu3_platform_data, - }, - .resource = tmu3_resources, - .num_resources = ARRAY_SIZE(tmu3_resources), +static const unsigned int ts_shift[] = TS_SHIFT; + +static struct sh_dmae_pdata dma0_platform_data = { + .channel = sh7780_dmae0_channels, + .channel_num = ARRAY_SIZE(sh7780_dmae0_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, }; -static struct sh_timer_config tmu4_platform_data = { - .name = "TMU4", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", +static struct sh_dmae_pdata dma1_platform_data = { + .channel = sh7780_dmae1_channels, + .channel_num = ARRAY_SIZE(sh7780_dmae1_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, }; -static struct resource tmu4_resources[] = { +static struct resource sh7780_dmae0_resources[] = { [0] = { - .name = "TMU4", - .start = 0xffdc0014, - .end = 0xffdc001f, + /* Channel registers and DMAOR */ + .start = 0xfc808020, + .end = 0xfc80808f, .flags = IORESOURCE_MEM, }, [1] = { - .start = 97, - .flags = IORESOURCE_IRQ, + /* DMARSx */ + .start = 0xfc809000, + .end = 0xfc80900b, + .flags = IORESOURCE_MEM, }, -}; - -static struct platform_device tmu4_device = { - .name = "sh_tmu", - .id = 4, - .dev = { - .platform_data = &tmu4_platform_data, + { + /* + * Real DMA error vector is 0x6c0, and channel + * vectors are 0x640-0x6a0, 0x780-0x7a0 + */ + .name = "error_irq", + .start = evt2irq(0x640), + .end = evt2irq(0x640), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, - .resource = tmu4_resources, - .num_resources = ARRAY_SIZE(tmu4_resources), -}; - -static struct sh_timer_config tmu5_platform_data = { - .name = "TMU5", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", }; -static struct resource tmu5_resources[] = { +static struct resource sh7780_dmae1_resources[] = { [0] = { - .name = "TMU5", - .start = 0xffdc0020, - .end = 0xffdc002b, + /* Channel registers and DMAOR */ + .start = 0xfc818020, + .end = 0xfc81808f, .flags = IORESOURCE_MEM, }, - [1] = { - .start = 98, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu5_device = { - .name = "sh_tmu", - .id = 5, - .dev = { - .platform_data = &tmu5_platform_data, + /* DMAC1 has no DMARS */ + { + /* + * Real DMA error vector is 0x6c0, and channel + * vectors are 0x7c0-0x7e0, 0xd80-0xde0 + */ + .name = "error_irq", + .start = evt2irq(0x7c0), + .end = evt2irq(0x7c0), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, - .resource = tmu5_resources, - .num_resources = ARRAY_SIZE(tmu5_resources), }; -static struct resource rtc_resources[] = { - [0] = { - .start = 0xffe80000, - .end = 0xffe80000 + 0x58 - 1, - .flags = IORESOURCE_IO, - }, - [1] = { - /* Shared Period/Carry/Alarm IRQ */ - .start = 20, - .flags = IORESOURCE_IRQ, +static struct platform_device dma0_device = { + .name = "sh-dma-engine", + .id = 0, + .resource = sh7780_dmae0_resources, + .num_resources = ARRAY_SIZE(sh7780_dmae0_resources), + .dev = { + .platform_data = &dma0_platform_data, }, }; -static struct platform_device rtc_device = { - .name = "sh-rtc", - .id = -1, - .num_resources = ARRAY_SIZE(rtc_resources), - .resource = rtc_resources, -}; - -static struct plat_sci_port sci_platform_data[] = { - { - .mapbase = 0xffe00000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, - }, { - .mapbase = 0xffe10000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 76, 76, 76, 76 }, - }, { - .flags = 0, - } -}; - -static struct platform_device sci_device = { - .name = "sh-sci", - .id = -1, +static struct platform_device dma1_device = { + .name = "sh-dma-engine", + .id = 1, + .resource = sh7780_dmae1_resources, + .num_resources = ARRAY_SIZE(sh7780_dmae1_resources), .dev = { - .platform_data = sci_platform_data, + .platform_data = &dma1_platform_data, }, }; static struct platform_device *sh7780_devices[] __initdata = { + &scif0_device, + &scif1_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, &rtc_device, - &sci_device, + &dma0_device, + &dma1_device, }; static int __init sh7780_devices_setup(void) @@ -256,19 +274,22 @@ static int __init sh7780_devices_setup(void) return platform_add_devices(sh7780_devices, ARRAY_SIZE(sh7780_devices)); } -__initcall(sh7780_devices_setup); +arch_initcall(sh7780_devices_setup); static struct platform_device *sh7780_early_devices[] __initdata = { + &scif0_device, + &scif1_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, }; void __init plat_early_device_setup(void) { + if (mach_is_sh2007()) { + scif0_platform_data.scscr &= ~SCSCR_CKE1; + scif1_platform_data.scscr &= ~SCSCR_CKE1; + } + early_platform_add_devices(sh7780_early_devices, ARRAY_SIZE(sh7780_early_devices)); } @@ -439,17 +460,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, void __init plat_irq_setup(void) { /* disable IRQ7-0 */ - ctrl_outl(0xff000000, INTC_INTMSK0); + __raw_writel(0xff000000, INTC_INTMSK0); /* disable IRL3-0 + IRL7-4 */ - ctrl_outl(0xc0000000, INTC_INTMSK1); - ctrl_outl(0xfffefffe, INTC_INTMSK2); + __raw_writel(0xc0000000, INTC_INTMSK1); + __raw_writel(0xfffefffe, INTC_INTMSK2); /* select IRL mode for IRL3-0 + IRL7-4 */ - ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); /* disable holding function, ie enable "SH-4 Mode" */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); register_intc_controller(&intc_desc); } @@ -459,27 +480,27 @@ void __init plat_irq_setup_pins(int mode) switch (mode) { case IRQ_MODE_IRQ: /* select IRQ mode for IRL3-0 + IRL7-4 */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); register_intc_controller(&intc_irq_desc); break; case IRQ_MODE_IRL7654: /* enable IRL7-4 but don't provide any masking */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); - ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); + __raw_writel(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x0000fffe, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL3210: /* enable IRL0-3 but don't provide any masking */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); - ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); + __raw_writel(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0xfffe0000, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL7654_MASK: /* enable IRL7-4 and mask using cpu intc controller */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x40000000, INTC_INTMSKCLR1); register_intc_controller(&intc_irl7654_desc); break; case IRQ_MODE_IRL3210_MASK: /* enable IRL0-3 and mask using cpu intc controller */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0x80000000, INTC_INTMSKCLR1); register_intc_controller(&intc_irl3210_desc); break; default: diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index af561402570..c72d5a5d099 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -13,249 +13,333 @@ #include <linux/serial_sci.h> #include <linux/io.h> #include <linux/mm.h> +#include <linux/sh_dma.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> #include <asm/mmzone.h> +#include <cpu/dma-register.h> -static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "tmu012_fck", - .clockevent_rating = 200, +static struct plat_sci_port scif0_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 28, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffea0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), }; -static struct platform_device tmu0_device = { - .name = "sh_tmu", +static struct platform_device scif0_device = { + .name = "sh-sci", .id = 0, - .dev = { - .platform_data = &tmu0_platform_data, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, }, - .resource = tmu0_resources, - .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "tmu012_fck", - .clocksource_rating = 200, +static struct plat_sci_port scif1_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 29, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffeb0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x780)), }; -static struct platform_device tmu1_device = { - .name = "sh_tmu", +static struct platform_device scif1_device = { + .name = "sh-sci", .id = 1, - .dev = { - .platform_data = &tmu1_platform_data, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, }, - .resource = tmu1_resources, - .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "tmu012_fck", +static struct plat_sci_port scif2_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu2_resources[] = { - [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 30, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffec0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x980)), }; -static struct platform_device tmu2_device = { - .name = "sh_tmu", +static struct platform_device scif2_device = { + .name = "sh-sci", .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), }; -static struct sh_timer_config tmu3_platform_data = { - .name = "TMU3", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "tmu345_fck", +static struct plat_sci_port scif3_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu3_resources[] = { - [0] = { - .name = "TMU3", - .start = 0xffdc0008, - .end = 0xffdc0013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 96, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xffed0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9a0)), }; -static struct platform_device tmu3_device = { - .name = "sh_tmu", +static struct platform_device scif3_device = { + .name = "sh-sci", .id = 3, - .dev = { - .platform_data = &tmu3_platform_data, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), + .dev = { + .platform_data = &scif3_platform_data, }, - .resource = tmu3_resources, - .num_resources = ARRAY_SIZE(tmu3_resources), }; -static struct sh_timer_config tmu4_platform_data = { - .name = "TMU4", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "tmu345_fck", +static struct plat_sci_port scif4_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu4_resources[] = { - [0] = { - .name = "TMU4", - .start = 0xffdc0014, - .end = 0xffdc001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 97, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xffee0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9c0)), }; -static struct platform_device tmu4_device = { - .name = "sh_tmu", +static struct platform_device scif4_device = { + .name = "sh-sci", .id = 4, - .dev = { - .platform_data = &tmu4_platform_data, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), + .dev = { + .platform_data = &scif4_platform_data, }, - .resource = tmu4_resources, - .num_resources = ARRAY_SIZE(tmu4_resources), }; -static struct sh_timer_config tmu5_platform_data = { - .name = "TMU5", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "tmu345_fck", +static struct plat_sci_port scif5_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu5_resources[] = { - [0] = { - .name = "TMU5", - .start = 0xffdc0020, - .end = 0xffdc002b, - .flags = IORESOURCE_MEM, +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xffef0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9e0)), +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), + .dev = { + .platform_data = &scif5_platform_data, }, - [1] = { - .start = 98, - .flags = IORESOURCE_IRQ, +}; + +static struct sh_timer_config tmu0_platform_data = { + .channels_mask = 7, +}; + +static struct resource tmu0_resources[] = { + DEFINE_RES_MEM(0xffd80000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x580)), + DEFINE_RES_IRQ(evt2irq(0x5a0)), + DEFINE_RES_IRQ(evt2irq(0x5c0)), +}; + +static struct platform_device tmu0_device = { + .name = "sh-tmu", + .id = 0, + .dev = { + .platform_data = &tmu0_platform_data, }, + .resource = tmu0_resources, + .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct platform_device tmu5_device = { - .name = "sh_tmu", - .id = 5, +static struct sh_timer_config tmu1_platform_data = { + .channels_mask = 7, +}; + +static struct resource tmu1_resources[] = { + DEFINE_RES_MEM(0xffdc0000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0xe00)), + DEFINE_RES_IRQ(evt2irq(0xe20)), + DEFINE_RES_IRQ(evt2irq(0xe40)), +}; + +static struct platform_device tmu1_device = { + .name = "sh-tmu", + .id = 1, .dev = { - .platform_data = &tmu5_platform_data, + .platform_data = &tmu1_platform_data, }, - .resource = tmu5_resources, - .num_resources = ARRAY_SIZE(tmu5_resources), + .resource = tmu1_resources, + .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct plat_sci_port sci_platform_data[] = { +/* DMA */ +static const struct sh_dmae_channel sh7785_dmae0_channels[] = { { - .mapbase = 0xffea0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, - .clk = "scif_fck", + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, }, { - .mapbase = 0xffeb0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 44, 44, 44, 44 }, - .clk = "scif_fck", + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + +static const struct sh_dmae_channel sh7785_dmae1_channels[] = { + { + .offset = 0, }, { - .mapbase = 0xffec0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 60, 60, 60, 60 }, - .clk = "scif_fck", + .offset = 0x10, }, { - .mapbase = 0xffed0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 61, 61, 61, 61 }, - .clk = "scif_fck", + .offset = 0x20, }, { - .mapbase = 0xffee0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 62, 62, 62, 62 }, - .clk = "scif_fck", + .offset = 0x30, }, { - .mapbase = 0xffef0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 63, 63, 63, 63 }, - .clk = "scif_fck", + .offset = 0x50, }, { - .flags = 0, + .offset = 0x60, } }; -static struct platform_device sci_device = { - .name = "sh-sci", - .id = -1, +static const unsigned int ts_shift[] = TS_SHIFT; + +static struct sh_dmae_pdata dma0_platform_data = { + .channel = sh7785_dmae0_channels, + .channel_num = ARRAY_SIZE(sh7785_dmae0_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +static struct sh_dmae_pdata dma1_platform_data = { + .channel = sh7785_dmae1_channels, + .channel_num = ARRAY_SIZE(sh7785_dmae1_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +static struct resource sh7785_dmae0_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xfc808020, + .end = 0xfc80808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xfc809000, + .end = 0xfc80900b, + .flags = IORESOURCE_MEM, + }, + { + /* + * Real DMA error vector is 0x6e0, and channel + * vectors are 0x620-0x6c0 + */ + .name = "error_irq", + .start = evt2irq(0x620), + .end = evt2irq(0x620), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, +}; + +static struct resource sh7785_dmae1_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xfcc08020, + .end = 0xfcc0808f, + .flags = IORESOURCE_MEM, + }, + /* DMAC1 has no DMARS */ + { + /* + * Real DMA error vector is 0x940, and channel + * vectors are 0x880-0x920 + */ + .name = "error_irq", + .start = evt2irq(0x880), + .end = evt2irq(0x880), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, +}; + +static struct platform_device dma0_device = { + .name = "sh-dma-engine", + .id = 0, + .resource = sh7785_dmae0_resources, + .num_resources = ARRAY_SIZE(sh7785_dmae0_resources), + .dev = { + .platform_data = &dma0_platform_data, + }, +}; + +static struct platform_device dma1_device = { + .name = "sh-dma-engine", + .id = 1, + .resource = sh7785_dmae1_resources, + .num_resources = ARRAY_SIZE(sh7785_dmae1_resources), .dev = { - .platform_data = sci_platform_data, + .platform_data = &dma1_platform_data, }, }; static struct platform_device *sh7785_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, - &sci_device, + &dma0_device, + &dma1_device, }; static int __init sh7785_devices_setup(void) @@ -263,15 +347,17 @@ static int __init sh7785_devices_setup(void) return platform_add_devices(sh7785_devices, ARRAY_SIZE(sh7785_devices)); } -__initcall(sh7785_devices_setup); +arch_initcall(sh7785_devices_setup); static struct platform_device *sh7785_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, }; void __init plat_early_device_setup(void) @@ -470,17 +556,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567, void __init plat_irq_setup(void) { /* disable IRQ3-0 + IRQ7-4 */ - ctrl_outl(0xff000000, INTC_INTMSK0); + __raw_writel(0xff000000, INTC_INTMSK0); /* disable IRL3-0 + IRL7-4 */ - ctrl_outl(0xc0000000, INTC_INTMSK1); - ctrl_outl(0xfffefffe, INTC_INTMSK2); + __raw_writel(0xc0000000, INTC_INTMSK1); + __raw_writel(0xfffefffe, INTC_INTMSK2); /* select IRL mode for IRL3-0 + IRL7-4 */ - ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); /* disable holding function, ie enable "SH-4 Mode" */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); register_intc_controller(&intc_desc); } @@ -490,32 +576,32 @@ void __init plat_irq_setup_pins(int mode) switch (mode) { case IRQ_MODE_IRQ7654: /* select IRQ mode for IRL7-4 */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); register_intc_controller(&intc_desc_irq4567); break; case IRQ_MODE_IRQ3210: /* select IRQ mode for IRL3-0 */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); register_intc_controller(&intc_desc_irq0123); break; case IRQ_MODE_IRL7654: /* enable IRL7-4 but don't provide any masking */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); - ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); + __raw_writel(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x0000fffe, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL3210: /* enable IRL0-3 but don't provide any masking */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); - ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); + __raw_writel(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0xfffe0000, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL7654_MASK: /* enable IRL7-4 and mask using cpu intc controller */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x40000000, INTC_INTMSKCLR1); register_intc_controller(&intc_desc_irl4567); break; case IRQ_MODE_IRL3210_MASK: /* enable IRL0-3 and mask using cpu intc controller */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0x80000000, INTC_INTMSKCLR1); register_intc_controller(&intc_desc_irl0123); break; default: diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 93e0d2c017e..479e79bdd3d 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -1,7 +1,7 @@ /* * SH7786 Setup * - * Copyright (C) 2009 Renesas Solutions Corp. + * Copyright (C) 2009 - 2011 Renesas Solutions Corp. * Kuninori Morimoto <morimoto.kuninori@renesas.com> * Paul Mundt <paul.mundt@renesas.com> * @@ -21,464 +21,392 @@ #include <linux/mm.h> #include <linux/dma-mapping.h> #include <linux/sh_timer.h> +#include <linux/sh_dma.h> +#include <linux/sh_intc.h> +#include <linux/usb/ohci_pdriver.h> +#include <cpu/dma-register.h> #include <asm/mmzone.h> -static struct plat_sci_port sci_platform_data[] = { - { - .mapbase = 0xffea0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 40, 41, 43, 42 }, - }, - /* - * The rest of these all have multiplexed IRQs - */ - { - .mapbase = 0xffeb0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 44, 44, 44, 44 }, - }, { - .mapbase = 0xffec0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 50, 50, 50, 50 }, - }, { - .mapbase = 0xffed0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 51, 51, 51, 51 }, - }, { - .mapbase = 0xffee0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 52, 52, 52, 52 }, - }, { - .mapbase = 0xffef0000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 53, 53, 53, 53 }, - }, { - .flags = 0, - } -}; - -static struct platform_device sci_device = { - .name = "sh-sci", - .id = -1, - .dev = { - .platform_data = sci_platform_data, - }, +static struct plat_sci_port scif0_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", - .clockevent_rating = 200, +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffea0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), + DEFINE_RES_IRQ(evt2irq(0x720)), + DEFINE_RES_IRQ(evt2irq(0x760)), + DEFINE_RES_IRQ(evt2irq(0x740)), }; -static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffd80008, - .end = 0xffd80013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 16, - .flags = IORESOURCE_IRQ, +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, }, }; -static struct platform_device tmu0_device = { - .name = "sh_tmu", - .id = 0, - .dev = { - .platform_data = &tmu0_platform_data, - }, - .resource = tmu0_resources, - .num_resources = ARRAY_SIZE(tmu0_resources), +/* + * The rest of these all have multiplexed IRQs + */ +static struct plat_sci_port scif1_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", - .clocksource_rating = 200, +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffeb0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x780)), }; -static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffd80014, - .end = 0xffd8001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 17, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif1_demux_resources[] = { + DEFINE_RES_MEM(0xffeb0000, 0x100), + /* Placeholders, see sh7786_devices_setup() */ + DEFINE_RES_IRQ(0), + DEFINE_RES_IRQ(0), + DEFINE_RES_IRQ(0), + DEFINE_RES_IRQ(0), }; -static struct platform_device tmu1_device = { - .name = "sh_tmu", +static struct platform_device scif1_device = { + .name = "sh-sci", .id = 1, - .dev = { - .platform_data = &tmu1_platform_data, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, }, - .resource = tmu1_resources, - .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", +static struct plat_sci_port scif2_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu2_resources[] = { - [0] = { - .name = "TMU2", - .start = 0xffd80020, - .end = 0xffd8002f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 18, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffec0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x840)), }; -static struct platform_device tmu2_device = { - .name = "sh_tmu", +static struct platform_device scif2_device = { + .name = "sh-sci", .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), }; -static struct sh_timer_config tmu3_platform_data = { - .name = "TMU3", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", +static struct plat_sci_port scif3_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu3_resources[] = { - [0] = { - .name = "TMU3", - .start = 0xffda0008, - .end = 0xffda0013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 20, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xffed0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x860)), }; -static struct platform_device tmu3_device = { - .name = "sh_tmu", +static struct platform_device scif3_device = { + .name = "sh-sci", .id = 3, - .dev = { - .platform_data = &tmu3_platform_data, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), + .dev = { + .platform_data = &scif3_platform_data, }, - .resource = tmu3_resources, - .num_resources = ARRAY_SIZE(tmu3_resources), }; -static struct sh_timer_config tmu4_platform_data = { - .name = "TMU4", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", +static struct plat_sci_port scif4_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu4_resources[] = { - [0] = { - .name = "TMU4", - .start = 0xffda0014, - .end = 0xffda001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 21, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xffee0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x880)), }; -static struct platform_device tmu4_device = { - .name = "sh_tmu", +static struct platform_device scif4_device = { + .name = "sh-sci", .id = 4, - .dev = { - .platform_data = &tmu4_platform_data, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), + .dev = { + .platform_data = &scif4_platform_data, }, - .resource = tmu4_resources, - .num_resources = ARRAY_SIZE(tmu4_resources), }; -static struct sh_timer_config tmu5_platform_data = { - .name = "TMU5", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", +static struct plat_sci_port scif5_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, + .type = PORT_SCIF, + .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -static struct resource tmu5_resources[] = { - [0] = { - .name = "TMU5", - .start = 0xffda0020, - .end = 0xffda002b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 22, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xffef0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x8a0)), }; -static struct platform_device tmu5_device = { - .name = "sh_tmu", +static struct platform_device scif5_device = { + .name = "sh-sci", .id = 5, - .dev = { - .platform_data = &tmu5_platform_data, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), + .dev = { + .platform_data = &scif5_platform_data, }, - .resource = tmu5_resources, - .num_resources = ARRAY_SIZE(tmu5_resources), }; -static struct sh_timer_config tmu6_platform_data = { - .name = "TMU6", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", +static struct sh_timer_config tmu0_platform_data = { + .channels_mask = 7, }; -static struct resource tmu6_resources[] = { - [0] = { - .name = "TMU6", - .start = 0xffdc0008, - .end = 0xffdc0013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 45, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu0_resources[] = { + DEFINE_RES_MEM(0xffd80000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x400)), + DEFINE_RES_IRQ(evt2irq(0x420)), + DEFINE_RES_IRQ(evt2irq(0x440)), }; -static struct platform_device tmu6_device = { - .name = "sh_tmu", - .id = 6, +static struct platform_device tmu0_device = { + .name = "sh-tmu", + .id = 0, .dev = { - .platform_data = &tmu6_platform_data, + .platform_data = &tmu0_platform_data, }, - .resource = tmu6_resources, - .num_resources = ARRAY_SIZE(tmu6_resources), + .resource = tmu0_resources, + .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct sh_timer_config tmu7_platform_data = { - .name = "TMU7", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", +static struct sh_timer_config tmu1_platform_data = { + .channels_mask = 7, }; -static struct resource tmu7_resources[] = { - [0] = { - .name = "TMU7", - .start = 0xffdc0014, - .end = 0xffdc001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 45, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu1_resources[] = { + DEFINE_RES_MEM(0xffda0000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x480)), + DEFINE_RES_IRQ(evt2irq(0x4a0)), + DEFINE_RES_IRQ(evt2irq(0x4c0)), }; -static struct platform_device tmu7_device = { - .name = "sh_tmu", - .id = 7, +static struct platform_device tmu1_device = { + .name = "sh-tmu", + .id = 1, .dev = { - .platform_data = &tmu7_platform_data, + .platform_data = &tmu1_platform_data, }, - .resource = tmu7_resources, - .num_resources = ARRAY_SIZE(tmu7_resources), + .resource = tmu1_resources, + .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu8_platform_data = { - .name = "TMU8", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", +static struct sh_timer_config tmu2_platform_data = { + .channels_mask = 7, }; -static struct resource tmu8_resources[] = { - [0] = { - .name = "TMU8", - .start = 0xffdc0020, - .end = 0xffdc002b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 45, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu2_resources[] = { + DEFINE_RES_MEM(0xffdc0000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x7a0)), + DEFINE_RES_IRQ(evt2irq(0x7a0)), + DEFINE_RES_IRQ(evt2irq(0x7a0)), }; -static struct platform_device tmu8_device = { - .name = "sh_tmu", - .id = 8, +static struct platform_device tmu2_device = { + .name = "sh-tmu", + .id = 2, .dev = { - .platform_data = &tmu8_platform_data, + .platform_data = &tmu2_platform_data, }, - .resource = tmu8_resources, - .num_resources = ARRAY_SIZE(tmu8_resources), + .resource = tmu2_resources, + .num_resources = ARRAY_SIZE(tmu2_resources), }; -static struct sh_timer_config tmu9_platform_data = { - .name = "TMU9", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", +static struct sh_timer_config tmu3_platform_data = { + .channels_mask = 7, }; -static struct resource tmu9_resources[] = { - [0] = { - .name = "TMU9", - .start = 0xffde0008, - .end = 0xffde0013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 46, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu3_resources[] = { + DEFINE_RES_MEM(0xffde0000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x7c0)), + DEFINE_RES_IRQ(evt2irq(0x7c0)), + DEFINE_RES_IRQ(evt2irq(0x7c0)), }; -static struct platform_device tmu9_device = { - .name = "sh_tmu", - .id = 9, +static struct platform_device tmu3_device = { + .name = "sh-tmu", + .id = 3, .dev = { - .platform_data = &tmu9_platform_data, + .platform_data = &tmu3_platform_data, }, - .resource = tmu9_resources, - .num_resources = ARRAY_SIZE(tmu9_resources), + .resource = tmu3_resources, + .num_resources = ARRAY_SIZE(tmu3_resources), }; -static struct sh_timer_config tmu10_platform_data = { - .name = "TMU10", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", +static const struct sh_dmae_channel dmac0_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } }; -static struct resource tmu10_resources[] = { - [0] = { - .name = "TMU10", - .start = 0xffde0014, - .end = 0xffde001f, +static const unsigned int ts_shift[] = TS_SHIFT; + +static struct sh_dmae_pdata dma0_platform_data = { + .channel = dmac0_channels, + .channel_num = ARRAY_SIZE(dmac0_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +/* Resource order important! */ +static struct resource dmac0_resources[] = { + { + /* Channel registers and DMAOR */ + .start = 0xfe008020, + .end = 0xfe00808f, .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 46, + }, { + /* DMARSx */ + .start = 0xfe009000, + .end = 0xfe00900b, + .flags = IORESOURCE_MEM, + }, { + .name = "error_irq", + .start = evt2irq(0x5c0), + .end = evt2irq(0x5c0), + .flags = IORESOURCE_IRQ, + }, { + /* IRQ for channels 0-5 */ + .start = evt2irq(0x500), + .end = evt2irq(0x5a0), .flags = IORESOURCE_IRQ, }, }; -static struct platform_device tmu10_device = { - .name = "sh_tmu", - .id = 10, - .dev = { - .platform_data = &tmu10_platform_data, +static struct platform_device dma0_device = { + .name = "sh-dma-engine", + .id = 0, + .resource = dmac0_resources, + .num_resources = ARRAY_SIZE(dmac0_resources), + .dev = { + .platform_data = &dma0_platform_data, }, - .resource = tmu10_resources, - .num_resources = ARRAY_SIZE(tmu10_resources), }; -static struct sh_timer_config tmu11_platform_data = { - .name = "TMU11", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", -}; +#define USB_EHCI_START 0xffe70000 +#define USB_OHCI_START 0xffe70400 -static struct resource tmu11_resources[] = { +static struct resource usb_ehci_resources[] = { [0] = { - .name = "TMU11", - .start = 0xffde0020, - .end = 0xffde002b, + .start = USB_EHCI_START, + .end = USB_EHCI_START + 0x3ff, .flags = IORESOURCE_MEM, }, [1] = { - .start = 46, + .start = evt2irq(0xba0), + .end = evt2irq(0xba0), .flags = IORESOURCE_IRQ, }, }; -static struct platform_device tmu11_device = { - .name = "sh_tmu", - .id = 11, +static struct platform_device usb_ehci_device = { + .name = "sh_ehci", + .id = -1, .dev = { - .platform_data = &tmu11_platform_data, + .dma_mask = &usb_ehci_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), }, - .resource = tmu11_resources, - .num_resources = ARRAY_SIZE(tmu11_resources), + .num_resources = ARRAY_SIZE(usb_ehci_resources), + .resource = usb_ehci_resources, }; static struct resource usb_ohci_resources[] = { [0] = { - .start = 0xffe70400, - .end = 0xffe704ff, + .start = USB_OHCI_START, + .end = USB_OHCI_START + 0x3ff, .flags = IORESOURCE_MEM, }, [1] = { - .start = 77, - .end = 77, + .start = evt2irq(0xba0), + .end = evt2irq(0xba0), .flags = IORESOURCE_IRQ, }, }; -static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32); +static struct usb_ohci_pdata usb_ohci_pdata; + static struct platform_device usb_ohci_device = { - .name = "sh_ohci", + .name = "ohci-platform", .id = -1, .dev = { - .dma_mask = &usb_ohci_dma_mask, + .dma_mask = &usb_ohci_device.dev.coherent_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &usb_ohci_pdata, }, .num_resources = ARRAY_SIZE(usb_ohci_resources), .resource = usb_ohci_resources, }; static struct platform_device *sh7786_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, &tmu0_device, &tmu1_device, &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, - &tmu6_device, - &tmu7_device, - &tmu8_device, - &tmu9_device, - &tmu10_device, - &tmu11_device, }; static struct platform_device *sh7786_devices[] __initdata = { - &sci_device, + &dma0_device, + &usb_ehci_device, &usb_ohci_device, }; - /* * Please call this function if your platform board * use external clock for USB @@ -486,6 +414,7 @@ static struct platform_device *sh7786_devices[] __initdata = { #define USBCTL0 0xffe70858 #define CLOCK_MODE_MASK 0xffffff7f #define EXT_CLOCK_MODE 0x00000080 + void __init sh7786_usb_use_exclock(void) { u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK; @@ -503,6 +432,7 @@ void __init sh7786_usb_use_exclock(void) #define PLL_ENB 0x00000002 #define PHY_RST 0x00000004 #define ACT_PLL_STATUS 0xc0000000 + static void __init sh7786_usb_setup(void) { int i = 1000000; @@ -513,7 +443,7 @@ static void __init sh7786_usb_setup(void) * The following settings are necessary * for using the USB modules. * - * see "USB Inital Settings" for detail + * see "USB Initial Settings" for detail */ __raw_writel(USBINITVAL1, USBINITREG1); __raw_writel(USBINITVAL2, USBINITREG2); @@ -533,33 +463,10 @@ static void __init sh7786_usb_setup(void) } } -static int __init sh7786_devices_setup(void) -{ - int ret; - - sh7786_usb_setup(); - - ret = platform_add_devices(sh7786_early_devices, - ARRAY_SIZE(sh7786_early_devices)); - if (unlikely(ret != 0)) - return ret; - - return platform_add_devices(sh7786_devices, - ARRAY_SIZE(sh7786_devices)); -} -device_initcall(sh7786_devices_setup); - -void __init plat_early_device_setup(void) -{ - early_platform_add_devices(sh7786_early_devices, - ARRAY_SIZE(sh7786_early_devices)); -} - enum { UNUSED = 0, /* interrupt sources */ - IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, @@ -595,12 +502,14 @@ enum { HSPI, GPIO0, GPIO1, Thermal, - INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7, + INTICI0, INTICI1, INTICI2, INTICI3, + INTICI4, INTICI5, INTICI6, INTICI7, - /* interrupt groups */ + /* Muxed sub-events */ + TXI1, BRI1, RXI1, ERI1, }; -static struct intc_vect vectors[] __initdata = { +static struct intc_vect sh7786_vectors[] __initdata = { INTC_VECT(WDT, 0x3e0), INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420), INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460), @@ -638,10 +547,12 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(HSPI, 0xe80), INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0), INTC_VECT(Thermal, 0xee0), + INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20), + INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60), + INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0), + INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0), }; -/* FIXME: Main CPU support only now */ -#if 1 /* Main CPU */ #define CnINTMSK0 0xfe410030 #define CnINTMSK1 0xfe410040 #define CnINTMSKCLR0 0xfe410050 @@ -654,27 +565,20 @@ static struct intc_vect vectors[] __initdata = { #define CnINT2MSKCR1 0xfe410a34 #define CnINT2MSKCR2 0xfe410a38 #define CnINT2MSKCR3 0xfe410a3c -#else /* Sub CPU */ -#define CnINTMSK0 0xfe410034 -#define CnINTMSK1 0xfe410044 -#define CnINTMSKCLR0 0xfe410054 -#define CnINTMSKCLR1 0xfe410064 -#define CnINT2MSKR0 0xfe410b20 -#define CnINT2MSKR1 0xfe410b24 -#define CnINT2MSKR2 0xfe410b28 -#define CnINT2MSKR3 0xfe410b2c -#define CnINT2MSKCR0 0xfe410b30 -#define CnINT2MSKCR1 0xfe410b34 -#define CnINT2MSKCR2 0xfe410b38 -#define CnINT2MSKCR3 0xfe410b3c -#endif - #define INTMSK2 0xfe410068 #define INTMSKCLR2 0xfe41006c -static struct intc_mask_reg mask_registers[] __initdata = { +#define INTDISTCR0 0xfe4100b0 +#define INTDISTCR1 0xfe4100b4 +#define INT2DISTCR0 0xfe410900 +#define INT2DISTCR1 0xfe410904 +#define INT2DISTCR2 0xfe410908 +#define INT2DISTCR3 0xfe41090c + +static struct intc_mask_reg sh7786_mask_registers[] __initdata = { { CnINTMSK0, CnINTMSKCLR0, 32, - { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 }, + INTC_SMP_BALANCING(INTDISTCR0) }, { INTMSK2, INTMSKCLR2, 32, { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, @@ -686,7 +590,8 @@ static struct intc_mask_reg mask_registers[] __initdata = { IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, { CnINT2MSKR0, CnINT2MSKCR0 , 32, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT }, + INTC_SMP_BALANCING(INT2DISTCR0) }, { CnINT2MSKR1, CnINT2MSKCR1, 32, { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0, DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6, @@ -695,14 +600,14 @@ static struct intc_mask_reg mask_registers[] __initdata = { HPB_0, HPB_1, HPB_2, SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3, SCIF1, - TMU2, TMU3, 0, } }, + TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) }, { CnINT2MSKR2, CnINT2MSKCR2, 32, { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5, Eth_0, Eth_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PCIeC0_0, PCIeC0_1, PCIeC0_2, PCIeC1_0, PCIeC1_1, PCIeC1_2, - USB, 0, 0 } }, + USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) }, { CnINT2MSKR3, CnINT2MSKCR3, 32, { 0, 0, 0, 0, 0, 0, I2C0, I2C1, @@ -711,10 +616,10 @@ static struct intc_mask_reg mask_registers[] __initdata = { HAC0, HAC1, FLCTL, 0, HSPI, GPIO0, GPIO1, Thermal, - 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) }, }; -static struct intc_prio_reg prio_registers[] __initdata = { +static struct intc_prio_reg sh7786_prio_registers[] __initdata = { { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } }, @@ -753,13 +658,32 @@ static struct intc_prio_reg prio_registers[] __initdata = { GPIO1, Thermal } }, { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } }, { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } }, + { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */ + { INTICI7, INTICI6, INTICI5, INTICI4, + INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) }, +}; + +static struct intc_subgroup sh7786_subgroups[] __initdata = { + { 0xfe410c20, 32, SCIF1, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } }, }; -static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL, - mask_registers, prio_registers, NULL); +static struct intc_desc sh7786_intc_desc __initdata = { + .name = "sh7786", + .hw = { + .vectors = sh7786_vectors, + .nr_vectors = ARRAY_SIZE(sh7786_vectors), + .mask_regs = sh7786_mask_registers, + .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers), + .subgroups = sh7786_subgroups, + .nr_subgroups = ARRAY_SIZE(sh7786_subgroups), + .prio_regs = sh7786_prio_registers, + .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers), + }, +}; /* Support for external interrupt pins in IRQ mode */ - static struct intc_vect vectors_irq0123[] __initdata = { INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), @@ -770,23 +694,25 @@ static struct intc_vect vectors_irq4567[] __initdata = { INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), }; -static struct intc_sense_reg sense_registers[] __initdata = { +static struct intc_sense_reg sh7786_sense_registers[] __initdata = { { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; -static struct intc_mask_reg ack_registers[] __initdata = { +static struct intc_mask_reg sh7786_ack_registers[] __initdata = { { 0xfe410024, 0, 32, /* INTREQ */ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123", - vectors_irq0123, NULL, mask_registers, - prio_registers, sense_registers, ack_registers); + vectors_irq0123, NULL, sh7786_mask_registers, + sh7786_prio_registers, sh7786_sense_registers, + sh7786_ack_registers); static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567", - vectors_irq4567, NULL, mask_registers, - prio_registers, sense_registers, ack_registers); + vectors_irq4567, NULL, sh7786_mask_registers, + sh7786_prio_registers, sh7786_sense_registers, + sh7786_ack_registers); /* External interrupt pins in IRL mode */ @@ -813,10 +739,10 @@ static struct intc_vect vectors_irl4567[] __initdata = { }; static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123, - NULL, mask_registers, NULL, NULL); + NULL, sh7786_mask_registers, NULL, NULL); static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567, - NULL, mask_registers, NULL, NULL); + NULL, sh7786_mask_registers, NULL, NULL); #define INTC_ICR0 0xfe410000 #define INTC_INTMSK0 CnINTMSK0 @@ -828,16 +754,16 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567, void __init plat_irq_setup(void) { /* disable IRQ3-0 + IRQ7-4 */ - ctrl_outl(0xff000000, INTC_INTMSK0); + __raw_writel(0xff000000, INTC_INTMSK0); /* disable IRL3-0 + IRL7-4 */ - ctrl_outl(0xc0000000, INTC_INTMSK1); - ctrl_outl(0xfffefffe, INTC_INTMSK2); + __raw_writel(0xc0000000, INTC_INTMSK1); + __raw_writel(0xfffefffe, INTC_INTMSK2); /* select IRL mode for IRL3-0 + IRL7-4 */ - ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); - register_intc_controller(&intc_desc); + register_intc_controller(&sh7786_intc_desc); } void __init plat_irq_setup_pins(int mode) @@ -845,32 +771,32 @@ void __init plat_irq_setup_pins(int mode) switch (mode) { case IRQ_MODE_IRQ7654: /* select IRQ mode for IRL7-4 */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); register_intc_controller(&intc_desc_irq4567); break; case IRQ_MODE_IRQ3210: /* select IRQ mode for IRL3-0 */ - ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); + __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); register_intc_controller(&intc_desc_irq0123); break; case IRQ_MODE_IRL7654: /* enable IRL7-4 but don't provide any masking */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); - ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); + __raw_writel(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x0000fffe, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL3210: /* enable IRL0-3 but don't provide any masking */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); - ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); + __raw_writel(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0xfffe0000, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL7654_MASK: /* enable IRL7-4 and mask using cpu intc controller */ - ctrl_outl(0x40000000, INTC_INTMSKCLR1); + __raw_writel(0x40000000, INTC_INTMSKCLR1); register_intc_controller(&intc_desc_irl4567); break; case IRQ_MODE_IRL3210_MASK: /* enable IRL0-3 and mask using cpu intc controller */ - ctrl_outl(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0x80000000, INTC_INTMSKCLR1); register_intc_controller(&intc_desc_irl0123); break; default: @@ -881,3 +807,42 @@ void __init plat_irq_setup_pins(int mode) void __init plat_mem_setup(void) { } + +static int __init sh7786_devices_setup(void) +{ + int ret, irq; + + sh7786_usb_setup(); + + /* + * De-mux SCIF1 IRQs if possible + */ + irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); + if (irq > 0) { + scif1_demux_resources[1].start = + intc_irq_lookup(sh7786_intc_desc.name, ERI1); + scif1_demux_resources[2].start = + intc_irq_lookup(sh7786_intc_desc.name, RXI1); + scif1_demux_resources[3].start = irq; + scif1_demux_resources[4].start = + intc_irq_lookup(sh7786_intc_desc.name, BRI1); + + scif1_device.resource = scif1_demux_resources; + scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources); + } + + ret = platform_add_devices(sh7786_early_devices, + ARRAY_SIZE(sh7786_early_devices)); + if (unlikely(ret != 0)) + return ret; + + return platform_add_devices(sh7786_devices, + ARRAY_SIZE(sh7786_devices)); +} +arch_initcall(sh7786_devices_setup); + +void __init plat_early_device_setup(void) +{ + early_platform_add_devices(sh7786_early_devices, + ARRAY_SIZE(sh7786_early_devices)); +} diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 53c65fd9cce..a78c5feb4e3 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c @@ -1,7 +1,7 @@ /* * SH-X3 Prototype Setup * - * Copyright (C) 2007 - 2009 Paul Mundt + * Copyright (C) 2007 - 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -12,251 +12,149 @@ #include <linux/serial.h> #include <linux/serial_sci.h> #include <linux/io.h> +#include <linux/gpio.h> #include <linux/sh_timer.h> +#include <linux/sh_intc.h> +#include <cpu/shx3.h> #include <asm/mmzone.h> -static struct plat_sci_port sci_platform_data[] = { - { - .mapbase = 0xffc30000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 40, 41, 43, 42 }, - }, { - .mapbase = 0xffc40000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 44, 45, 47, 46 }, - }, { - .mapbase = 0xffc50000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 48, 49, 51, 50 }, - }, { - .mapbase = 0xffc60000, - .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 52, 53, 55, 54 }, - }, { - .flags = 0, - } -}; - -static struct platform_device sci_device = { - .name = "sh-sci", - .id = -1, - .dev = { - .platform_data = sci_platform_data, - }, -}; - -static struct sh_timer_config tmu0_platform_data = { - .name = "TMU0", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", - .clockevent_rating = 200, +/* + * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2 + * INTEVT values overlap with the FPU EXPEVT ones, requiring special + * demuxing in the exception dispatch path. + * + * As this overlap is something that never should have made it in to + * silicon in the first place, we just refuse to deal with the port at + * all rather than adding infrastructure to hack around it. + */ +static struct plat_sci_port scif0_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, }; -static struct resource tmu0_resources[] = { - [0] = { - .name = "TMU0", - .start = 0xffc10008, - .end = 0xffc10013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 16, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffc30000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), + DEFINE_RES_IRQ(evt2irq(0x720)), + DEFINE_RES_IRQ(evt2irq(0x760)), + DEFINE_RES_IRQ(evt2irq(0x740)), }; -static struct platform_device tmu0_device = { - .name = "sh_tmu", +static struct platform_device scif0_device = { + .name = "sh-sci", .id = 0, - .dev = { - .platform_data = &tmu0_platform_data, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), + .dev = { + .platform_data = &scif0_platform_data, }, - .resource = tmu0_resources, - .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct sh_timer_config tmu1_platform_data = { - .name = "TMU1", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", - .clocksource_rating = 200, +static struct plat_sci_port scif1_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, }; -static struct resource tmu1_resources[] = { - [0] = { - .name = "TMU1", - .start = 0xffc10014, - .end = 0xffc1001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 17, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffc40000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x780)), + DEFINE_RES_IRQ(evt2irq(0x7a0)), + DEFINE_RES_IRQ(evt2irq(0x7e0)), + DEFINE_RES_IRQ(evt2irq(0x7c0)), }; -static struct platform_device tmu1_device = { - .name = "sh_tmu", +static struct platform_device scif1_device = { + .name = "sh-sci", .id = 1, - .dev = { - .platform_data = &tmu1_platform_data, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), + .dev = { + .platform_data = &scif1_platform_data, }, - .resource = tmu1_resources, - .num_resources = ARRAY_SIZE(tmu1_resources), }; -static struct sh_timer_config tmu2_platform_data = { - .name = "TMU2", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", +static struct plat_sci_port scif2_platform_data = { + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .type = PORT_SCIF, }; -static struct resource tmu2_resources[] = { - [0] = { - .name = "TMU2", - .start = 0xffc10020, - .end = 0xffc1002f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 18, - .flags = IORESOURCE_IRQ, - }, +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffc60000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x880)), + DEFINE_RES_IRQ(evt2irq(0x8a0)), + DEFINE_RES_IRQ(evt2irq(0x8e0)), + DEFINE_RES_IRQ(evt2irq(0x8c0)), }; -static struct platform_device tmu2_device = { - .name = "sh_tmu", +static struct platform_device scif2_device = { + .name = "sh-sci", .id = 2, - .dev = { - .platform_data = &tmu2_platform_data, - }, - .resource = tmu2_resources, - .num_resources = ARRAY_SIZE(tmu2_resources), -}; - -static struct sh_timer_config tmu3_platform_data = { - .name = "TMU3", - .channel_offset = 0x04, - .timer_bit = 0, - .clk = "peripheral_clk", -}; - -static struct resource tmu3_resources[] = { - [0] = { - .name = "TMU3", - .start = 0xffc20008, - .end = 0xffc20013, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 19, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tmu3_device = { - .name = "sh_tmu", - .id = 3, - .dev = { - .platform_data = &tmu3_platform_data, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), + .dev = { + .platform_data = &scif2_platform_data, }, - .resource = tmu3_resources, - .num_resources = ARRAY_SIZE(tmu3_resources), }; -static struct sh_timer_config tmu4_platform_data = { - .name = "TMU4", - .channel_offset = 0x10, - .timer_bit = 1, - .clk = "peripheral_clk", +static struct sh_timer_config tmu0_platform_data = { + .channels_mask = 7, }; -static struct resource tmu4_resources[] = { - [0] = { - .name = "TMU4", - .start = 0xffc20014, - .end = 0xffc2001f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 20, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu0_resources[] = { + DEFINE_RES_MEM(0xffc10000, 0x30), + DEFINE_RES_IRQ(evt2irq(0x400)), + DEFINE_RES_IRQ(evt2irq(0x420)), + DEFINE_RES_IRQ(evt2irq(0x440)), }; -static struct platform_device tmu4_device = { - .name = "sh_tmu", - .id = 4, +static struct platform_device tmu0_device = { + .name = "sh-tmu", + .id = 0, .dev = { - .platform_data = &tmu4_platform_data, + .platform_data = &tmu0_platform_data, }, - .resource = tmu4_resources, - .num_resources = ARRAY_SIZE(tmu4_resources), + .resource = tmu0_resources, + .num_resources = ARRAY_SIZE(tmu0_resources), }; -static struct sh_timer_config tmu5_platform_data = { - .name = "TMU5", - .channel_offset = 0x1c, - .timer_bit = 2, - .clk = "peripheral_clk", +static struct sh_timer_config tmu1_platform_data = { + .channels_mask = 7, }; -static struct resource tmu5_resources[] = { - [0] = { - .name = "TMU5", - .start = 0xffc20020, - .end = 0xffc2002b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 21, - .flags = IORESOURCE_IRQ, - }, +static struct resource tmu1_resources[] = { + DEFINE_RES_MEM(0xffc20000, 0x2c), + DEFINE_RES_IRQ(evt2irq(0x460)), + DEFINE_RES_IRQ(evt2irq(0x480)), + DEFINE_RES_IRQ(evt2irq(0x4a0)), }; -static struct platform_device tmu5_device = { - .name = "sh_tmu", - .id = 5, +static struct platform_device tmu1_device = { + .name = "sh-tmu", + .id = 1, .dev = { - .platform_data = &tmu5_platform_data, + .platform_data = &tmu1_platform_data, }, - .resource = tmu5_resources, - .num_resources = ARRAY_SIZE(tmu5_resources), + .resource = tmu1_resources, + .num_resources = ARRAY_SIZE(tmu1_resources), }; static struct platform_device *shx3_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, &tmu0_device, &tmu1_device, - &tmu2_device, - &tmu3_device, - &tmu4_device, - &tmu5_device, -}; - -static struct platform_device *shx3_devices[] __initdata = { - &sci_device, }; static int __init shx3_devices_setup(void) { - int ret; - - ret = platform_add_devices(shx3_early_devices, + return platform_add_devices(shx3_early_devices, ARRAY_SIZE(shx3_early_devices)); - if (unlikely(ret != 0)) - return ret; - - return platform_add_devices(shx3_devices, - ARRAY_SIZE(shx3_devices)); } -__initcall(shx3_devices_setup); +arch_initcall(shx3_devices_setup); void __init plat_early_device_setup(void) { @@ -287,10 +185,7 @@ enum { DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE, IIC, VIN0, VIN1, VCORE0, ATAPI, - DTU0_TEND, DTU0_AE, DTU0_TMISS, - DTU1_TEND, DTU1_AE, DTU1_TMISS, - DTU2_TEND, DTU2_AE, DTU2_TMISS, - DTU3_TEND, DTU3_AE, DTU3_TMISS, + DTU0, DTU1, DTU2, DTU3, FE0, FE1, GPIO0, GPIO1, GPIO2, GPIO3, PAM, IRM, @@ -299,7 +194,7 @@ enum { /* interrupt groups */ IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3, - DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3, + DMAC0, DMAC1, }; static struct intc_vect vectors[] __initdata = { @@ -316,8 +211,6 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0), INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0), - INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820), - INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860), INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0), INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0), INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920), @@ -332,14 +225,14 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(IIC, 0xae0), INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20), INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60), - INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20), - INTC_VECT(DTU0_TMISS, 0xc40), - INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80), - INTC_VECT(DTU1_TMISS, 0xca0), - INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0), - INTC_VECT(DTU2_TMISS, 0xd00), - INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40), - INTC_VECT(DTU3_TMISS, 0xd60), + INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20), + INTC_VECT(DTU0, 0xc40), + INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80), + INTC_VECT(DTU1, 0xca0), + INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0), + INTC_VECT(DTU2, 0xd00), + INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40), + INTC_VECT(DTU3, 0xd60), INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20), INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60), INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0), @@ -358,18 +251,17 @@ static struct intc_group groups[] __initdata = { INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9), INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), - INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI), INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), - INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS), - INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS), - INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS), - INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS), }; +#define INT2DISTCR0 0xfe4108a0 +#define INT2DISTCR1 0xfe4108a4 +#define INT2DISTCR2 0xfe4108a8 + static struct intc_mask_reg mask_registers[] __initdata = { { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, @@ -379,20 +271,23 @@ static struct intc_mask_reg mask_registers[] __initdata = { { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC, DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */ - 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } }, + 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, }, + INTC_SMP_BALANCING(INT2DISTCR0) }, { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */ { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */ PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2, PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11, DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7, DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4, - DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } }, + DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 }, + INTC_SMP_BALANCING(INT2DISTCR1) }, { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI, SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI, SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI, - SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } }, + SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI }, + INTC_SMP_BALANCING(INT2DISTCR2) }, }; static struct intc_prio_reg prio_registers[] __initdata = { @@ -449,11 +344,33 @@ static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups, void __init plat_irq_setup_pins(int mode) { + int ret = 0; + switch (mode) { case IRQ_MODE_IRQ: + ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name); + ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name); + ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name); + ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name); + + if (unlikely(ret)) { + pr_err("Failed to set IRQ mode\n"); + return; + } + register_intc_controller(&intc_desc_irq); break; case IRQ_MODE_IRL3210: + ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name); + ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name); + ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name); + ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name); + + if (unlikely(ret)) { + pr_err("Failed to set IRL mode\n"); + return; + } + register_intc_controller(&intc_desc_irl); break; default: diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c index b8869aa20de..4a298808789 100644 --- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c @@ -1,7 +1,7 @@ /* * SH-X3 SMP * - * Copyright (C) 2007 - 2008 Paul Mundt + * Copyright (C) 2007 - 2010 Paul Mundt * Copyright (C) 2007 Magnus Damm * * This file is subject to the terms and conditions of the GNU General Public @@ -9,10 +9,23 @@ * for more details. */ #include <linux/init.h> +#include <linux/kernel.h> #include <linux/cpumask.h> #include <linux/smp.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/cpu.h> +#include <asm/sections.h> + +#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12)) +#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12)) + +#define STBCR_MSTP 0x00000001 +#define STBCR_RESET 0x00000002 +#define STBCR_SLEEP 0x00000004 +#define STBCR_LTSLP 0x80000000 static irqreturn_t ipi_interrupt_handler(int irq, void *arg) { @@ -21,22 +34,24 @@ static irqreturn_t ipi_interrupt_handler(int irq, void *arg) unsigned int offs = 4 * cpu; unsigned int x; - x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ + x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ x &= (1 << (message << 2)); - ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ + __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ smp_message_recv(message); return IRQ_HANDLED; } -void __init plat_smp_setup(void) +static void shx3_smp_setup(void) { unsigned int cpu = 0; int i, num; - cpus_clear(cpu_possible_map); - cpu_set(cpu, cpu_possible_map); + init_cpu_possible(cpumask_of(cpu)); + + /* Enable light sleep for the boot CPU */ + __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); __cpu_number_map[0] = 0; __cpu_logical_map[0] = 0; @@ -46,7 +61,7 @@ void __init plat_smp_setup(void) * for the total number of cores. */ for (i = 1, num = 0; i < NR_CPUS; i++) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = ++num; __cpu_logical_map[num] = i; } @@ -54,50 +69,98 @@ void __init plat_smp_setup(void) printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); } -void __init plat_prepare_cpus(unsigned int max_cpus) +static void shx3_prepare_cpus(unsigned int max_cpus) { int i; + local_timer_setup(0); + BUILD_BUG_ON(SMP_MSG_NR >= 8); for (i = 0; i < SMP_MSG_NR; i++) - request_irq(104 + i, ipi_interrupt_handler, IRQF_DISABLED, - "IPI", (void *)(long)i); -} - -#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12)) -#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12)) + request_irq(104 + i, ipi_interrupt_handler, + IRQF_PERCPU, "IPI", (void *)(long)i); -#define STBCR_MSTP 0x00000001 -#define STBCR_RESET 0x00000002 -#define STBCR_LTSLP 0x80000000 - -#define STBCR_AP_VAL (STBCR_RESET | STBCR_LTSLP) + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); +} -void plat_start_cpu(unsigned int cpu, unsigned long entry_point) +static void shx3_start_cpu(unsigned int cpu, unsigned long entry_point) { - ctrl_outl(entry_point, RESET_REG(cpu)); + if (__in_29bit_mode()) + __raw_writel(entry_point, RESET_REG(cpu)); + else + __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu)); - if (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP)) - ctrl_outl(STBCR_MSTP, STBCR_REG(cpu)); + if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) + __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); - while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP)) + while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) cpu_relax(); /* Start up secondary processor by sending a reset */ - ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu)); + __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu)); } -int plat_smp_processor_id(void) +static unsigned int shx3_smp_processor_id(void) { - return ctrl_inl(0xff000048); /* CPIDR */ + return __raw_readl(0xff000048); /* CPIDR */ } -void plat_send_ipi(unsigned int cpu, unsigned int message) +static void shx3_send_ipi(unsigned int cpu, unsigned int message) { unsigned long addr = 0xfe410070 + (cpu * 4); BUG_ON(cpu >= 4); - ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ + __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ +} + +static void shx3_update_boot_vector(unsigned int cpu) +{ + __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); + while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) + cpu_relax(); + __raw_writel(STBCR_RESET, STBCR_REG(cpu)); +} + +static int +shx3_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) +{ + unsigned int cpu = (unsigned int)hcpu; + + switch (action) { + case CPU_UP_PREPARE: + shx3_update_boot_vector(cpu); + break; + case CPU_ONLINE: + pr_info("CPU %u is now online\n", cpu); + break; + case CPU_DEAD: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block shx3_cpu_notifier = { + .notifier_call = shx3_cpu_callback, +}; + +static int register_shx3_cpu_notifier(void) +{ + register_hotcpu_notifier(&shx3_cpu_notifier); + return 0; } +late_initcall(register_shx3_cpu_notifier); + +struct plat_smp_ops shx3_smp_ops = { + .smp_setup = shx3_smp_setup, + .prepare_cpus = shx3_prepare_cpus, + .start_cpu = shx3_start_cpu, + .smp_processor_id = shx3_smp_processor_id, + .send_ipi = shx3_send_ipi, + .cpu_die = native_cpu_die, + .cpu_disable = native_cpu_disable, + .play_dead = native_play_dead, +}; diff --git a/arch/sh/kernel/cpu/sh4a/ubc.c b/arch/sh/kernel/cpu/sh4a/ubc.c new file mode 100644 index 00000000000..efb2745bcb3 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/ubc.c @@ -0,0 +1,133 @@ +/* + * arch/sh/kernel/cpu/sh4a/ubc.c + * + * On-chip UBC support for SH-4A CPUs. + * + * Copyright (C) 2009 - 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <asm/hw_breakpoint.h> + +#define UBC_CBR(idx) (0xff200000 + (0x20 * idx)) +#define UBC_CRR(idx) (0xff200004 + (0x20 * idx)) +#define UBC_CAR(idx) (0xff200008 + (0x20 * idx)) +#define UBC_CAMR(idx) (0xff20000c + (0x20 * idx)) + +#define UBC_CCMFR 0xff200600 +#define UBC_CBCR 0xff200620 + +/* CRR */ +#define UBC_CRR_PCB (1 << 1) +#define UBC_CRR_BIE (1 << 0) + +/* CBR */ +#define UBC_CBR_CE (1 << 0) + +static struct sh_ubc sh4a_ubc; + +static void sh4a_ubc_enable(struct arch_hw_breakpoint *info, int idx) +{ + __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); + __raw_writel(info->address, UBC_CAR(idx)); +} + +static void sh4a_ubc_disable(struct arch_hw_breakpoint *info, int idx) +{ + __raw_writel(0, UBC_CBR(idx)); + __raw_writel(0, UBC_CAR(idx)); +} + +static void sh4a_ubc_enable_all(unsigned long mask) +{ + int i; + + for (i = 0; i < sh4a_ubc.num_events; i++) + if (mask & (1 << i)) + __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, + UBC_CBR(i)); +} + +static void sh4a_ubc_disable_all(void) +{ + int i; + + for (i = 0; i < sh4a_ubc.num_events; i++) + __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, + UBC_CBR(i)); +} + +static unsigned long sh4a_ubc_active_mask(void) +{ + unsigned long active = 0; + int i; + + for (i = 0; i < sh4a_ubc.num_events; i++) + if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE) + active |= (1 << i); + + return active; +} + +static unsigned long sh4a_ubc_triggered_mask(void) +{ + return __raw_readl(UBC_CCMFR); +} + +static void sh4a_ubc_clear_triggered_mask(unsigned long mask) +{ + __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); +} + +static struct sh_ubc sh4a_ubc = { + .name = "SH-4A", + .num_events = 2, + .trap_nr = 0x1e0, + .enable = sh4a_ubc_enable, + .disable = sh4a_ubc_disable, + .enable_all = sh4a_ubc_enable_all, + .disable_all = sh4a_ubc_disable_all, + .active_mask = sh4a_ubc_active_mask, + .triggered_mask = sh4a_ubc_triggered_mask, + .clear_triggered_mask = sh4a_ubc_clear_triggered_mask, +}; + +static int __init sh4a_ubc_init(void) +{ + struct clk *ubc_iclk = clk_get(NULL, "ubc0"); + int i; + + /* + * The UBC MSTP bit is optional, as not all platforms will have + * it. Just ignore it if we can't find it. + */ + if (IS_ERR(ubc_iclk)) + ubc_iclk = NULL; + + clk_enable(ubc_iclk); + + __raw_writel(0, UBC_CBCR); + + for (i = 0; i < sh4a_ubc.num_events; i++) { + __raw_writel(0, UBC_CAMR(i)); + __raw_writel(0, UBC_CBR(i)); + + __raw_writel(UBC_CRR_BIE | UBC_CRR_PCB, UBC_CRR(i)); + + /* dummy read for write posting */ + (void)__raw_readl(UBC_CRR(i)); + } + + clk_disable(ubc_iclk); + + sh4a_ubc.clk = ubc_iclk; + + return register_sh_ubc(&sh4a_ubc); +} +arch_initcall(sh4a_ubc_init); |