diff options
Diffstat (limited to 'arch/blackfin/mach-bf533/include/mach')
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/anomaly.h | 184 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/bf533.h | 27 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/bfin_serial.h | 14 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h | 164 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/blackfin.h | 62 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/cdefBF532.h | 180 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/defBF532.h | 447 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/gpio.h | 37 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/irq.h | 197 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/mem_map.h | 56 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/pll.h | 1 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/portmux.h | 9 |
12 files changed, 312 insertions, 1066 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 1cf893e2e55..0e754efc3cf 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h @@ -1,13 +1,16 @@ /* - * File: include/asm-blackfin/mach-bf533/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2011 Analog Devices Inc. + * Licensed under the Clear BSD license. */ -/* This file shoule be up to date with: - * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List +/* This file should be up to date with: + * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -34,21 +37,21 @@ # define ANOMALY_BF533 0 #endif -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) /* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ -#define ANOMALY_05000105 (1) +#define ANOMALY_05000105 (__SILICON_REVISION__ > 2) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) -/* Turning Serial Ports on with External Frame Syncs */ +/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) @@ -56,25 +59,25 @@ #define ANOMALY_05000180 (1) /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ -#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) +#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4) /* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ -#define ANOMALY_05000201 (__SILICON_REVISION__ < 4) +#define ANOMALY_05000201 (__SILICON_REVISION__ == 3) /* Possible Infinite Stall with Specific Dual-DAG Situation */ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) @@ -104,9 +107,9 @@ #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* Data CPLBs Should Prevent Spurious Hardware Errors */ +/* Data CPLBs Should Prevent False Hardware Errors */ #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) @@ -137,7 +140,7 @@ /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 5) /* Spontaneous Reset of Internal Voltage Regulator */ -#define ANOMALY_05000271 (__SILICON_REVISION__ < 4) +#define ANOMALY_05000271 (__SILICON_REVISION__ == 3) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) /* Writes to Synchronous SDRAM Memory May Be Lost */ @@ -148,33 +151,33 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 6) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 6) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ +/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ -#define ANOMALY_05000307 (1) +#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) -/* PPI Is Level-Sensitive on First Transfer */ +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) @@ -200,32 +203,101 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ +#define ANOMALY_05000471 (1) +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition when Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ +#define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) -/* These anomalies have been "phased" out of analog.com anomaly sheets and are +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. */ +/* Internal voltage regulator can't be modified via register writes */ +#define ANOMALY_05000066 (__SILICON_REVISION__ < 2) /* Watchpoints (Hardware Breakpoints) are not supported */ #define ANOMALY_05000067 (__SILICON_REVISION__ < 3) -/* Reserved bits in SYSCFG register not set at power on */ +/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */ +#define ANOMALY_05000070 (__SILICON_REVISION__ < 2) +/* Writing FIO_DIR can corrupt a programmable flag's data */ +#define ANOMALY_05000079 (__SILICON_REVISION__ < 2) +/* Timer Auto-Baud Mode requires the UART clock to be enabled. */ +#define ANOMALY_05000086 (__SILICON_REVISION__ < 2) +/* Internal Clocking Modes on SPORT0 not supported */ +#define ANOMALY_05000088 (__SILICON_REVISION__ < 2) +/* Internal voltage regulator does not wake up from an RTC wakeup */ +#define ANOMALY_05000092 (__SILICON_REVISION__ < 2) +/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ +#define ANOMALY_05000093 (__SILICON_REVISION__ < 2) +/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ +#define ANOMALY_05000095 (__SILICON_REVISION__ < 2) +/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ +#define ANOMALY_05000096 (__SILICON_REVISION__ < 2) +/* Performance Monitor 0 and 1 are swapped when monitoring memory events */ +#define ANOMALY_05000097 (__SILICON_REVISION__ < 2) +/* 32-bit SPORT DMA will be word reversed */ +#define ANOMALY_05000098 (__SILICON_REVISION__ < 2) +/* Incorrect status in the UART_IIR register */ +#define ANOMALY_05000100 (__SILICON_REVISION__ < 2) +/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ +#define ANOMALY_05000101 (__SILICON_REVISION__ < 2) +/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ +#define ANOMALY_05000102 (__SILICON_REVISION__ < 2) +/* Incorrect Value Written to the Cycle Counters */ +#define ANOMALY_05000103 (__SILICON_REVISION__ < 2) +/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ +#define ANOMALY_05000104 (__SILICON_REVISION__ < 2) +/* Programmable Flag (PF3) functionality not supported in all PPI modes */ +#define ANOMALY_05000106 (__SILICON_REVISION__ < 2) +/* Data store can be lost when targeting a cache line fill */ +#define ANOMALY_05000107 (__SILICON_REVISION__ < 2) +/* Reserved Bits in SYSCFG Register Not Set at Power-On */ #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +/* Infinite Core Stall */ +#define ANOMALY_05000114 (__SILICON_REVISION__ < 2) +/* PPI_FSx may glitch when generated by the on chip Timers. */ +#define ANOMALY_05000115 (__SILICON_REVISION__ < 2) +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ +/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ +#define ANOMALY_05000117 (__SILICON_REVISION__ < 2) +/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ +#define ANOMALY_05000118 (__SILICON_REVISION__ < 2) +/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) /* SPI clock polarity and phase bits incorrect during booting */ #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL is not set on Reset */ +/* DMEM_CONTROL<12> Is Not Set on Reset */ #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) /* SPI boot will not complete if there is a zero fill block in the loader file */ -#define ANOMALY_05000138 (__SILICON_REVISION__ < 3) +#define ANOMALY_05000138 (__SILICON_REVISION__ == 2) +/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ +#define ANOMALY_05000139 (__SILICON_REVISION__ < 2) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) @@ -237,23 +309,23 @@ #define ANOMALY_05000145 (__SILICON_REVISION__ < 3) /* MDMA may lose the first few words of a descriptor chain */ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* The source MDMA descriptor may stop with a DMA Error */ +/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ +/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) /* Frame Delay in SPORT Multichannel Mode */ #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */ +/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) -/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) /* DMA vs Core accesses to external memory */ #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) @@ -261,29 +333,51 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* In PPI Transmit Modes with External Frame Syncs POLC */ +/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000120 (0) +#define ANOMALY_05000149 (0) +#define ANOMALY_05000171 (0) +#define ANOMALY_05000182 (0) +#define ANOMALY_05000220 (0) +#define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000287 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000362 (1) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) #define ANOMALY_05000412 (0) +#define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) +#define ANOMALY_05000440 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) +#define ANOMALY_05000485 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h index cf4427cd3f7..e3e05f8f7af 100644 --- a/arch/blackfin/mach-bf533/include/mach/bf533.h +++ b/arch/blackfin/mach-bf533/include/mach/bf533.h @@ -1,30 +1,9 @@ /* - * File: include/asm-blackfin/mach-bf533/bf533.h - * Based on: - * Author: + * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 * - * Created: - * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 + * Copyright 2005-2008 Analog Devices Inc. * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #ifndef __MACH_BF533_H__ diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h new file mode 100644 index 00000000000..08072c86d5d --- /dev/null +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h @@ -0,0 +1,14 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 1 + +#endif diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h deleted file mode 100644 index 5f517f53b0f..00000000000 --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h - * based on: - * author: - * - * created: - * description: - * blackfin serial driver head file - * rev: - * - * modified: - * - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. - */ - -#include <linux/serial.h> -#include <asm/dma.h> -#include <asm/portmux.h> - -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) - -#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) -#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) -#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) -#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) -#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) -#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) -#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) -#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) - -#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) -#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) - -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - -#ifdef CONFIG_BFIN_UART0_CTSRTS -# define CONFIG_SERIAL_BFIN_CTSRTS -# ifndef CONFIG_UART0_CTS_PIN -# define CONFIG_UART0_CTS_PIN -1 -# endif -# ifndef CONFIG_UART0_RTS_PIN -# define CONFIG_UART0_RTS_PIN -1 -# endif -#endif - -#define BFIN_UART_TX_FIFO_SIZE 2 - -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - unsigned int lsr; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#else -# if ANOMALY_05000363 - unsigned int anomaly_threshold; -# endif -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct timer_list cts_timer; - int cts_pin; - int rts_pin; -#endif -}; - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) -{ - unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); - uart->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | uart->lsr; -} - -static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) -{ - uart->lsr = 0; - bfin_write16(uart->port.membase + OFFSET_LSR, -1); -} - -struct bfin_serial_res { - unsigned long uart_base_addr; - int uart_irq; -#ifdef CONFIG_SERIAL_BFIN_DMA - unsigned int uart_tx_dma_channel; - unsigned int uart_rx_dma_channel; -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - int uart_cts_pin; - int uart_rts_pin; -#endif -}; - -struct bfin_serial_res bfin_serial_resource[] = { - { - 0xFFC00400, - IRQ_UART_RX, -#ifdef CONFIG_SERIAL_BFIN_DMA - CH_UART_TX, - CH_UART_RX, -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - CONFIG_UART0_CTS_PIN, - CONFIG_UART0_RTS_PIN, -#endif - } -}; - -#define DRIVER_NAME "bfin-uart" - -static void bfin_serial_hw_init(struct bfin_serial_port *uart) -{ - -#ifdef CONFIG_SERIAL_BFIN_UART0 - peripheral_request(P_UART0_TX, DRIVER_NAME); - peripheral_request(P_UART0_RX, DRIVER_NAME); -#endif - -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - if (uart->cts_pin >= 0) { - gpio_request(uart->cts_pin, DRIVER_NAME); - gpio_direction_input(uart->cts_pin); - } - if (uart->rts_pin >= 0) { - gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin, 0); - } -#endif -} diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h index 045184f81a2..e366207fbf1 100644 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h @@ -1,31 +1,7 @@ /* - * File: include/asm-blackfin/mach-bf533/blackfin.h - * Based on: - * Author: + * Copyright 2005-2010 Analog Devices Inc. * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later. */ #ifndef _MACH_BLACKFIN_H_ @@ -34,34 +10,14 @@ #define BF533_FAMILY #include "bf533.h" -#include "mem_map.h" -#include "defBF532.h" #include "anomaly.h" -#if !defined(__ASSEMBLY__) -#include "cdefBF532.h" -#endif - -#define BFIN_UART_NR_PORTS 1 - -#define CH_UART_RX CH_UART0_RX -#define CH_UART_TX CH_UART0_TX - -#define IRQ_UART_ERROR IRQ_UART0_ERROR -#define IRQ_UART_RX IRQ_UART0_RX -#define IRQ_UART_TX IRQ_UART0_TX +#include <asm/def_LPBlackfin.h> +#include "defBF532.h" -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ +#ifndef __ASSEMBLY__ +# include <asm/cdef_LPBlackfin.h> +# include "cdefBF532.h" +#endif -#endif /* _MACH_BLACKFIN_H_ */ +#endif diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h index bbc3c8386d4..fd0cbe4df21 100644 --- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h @@ -1,44 +1,12 @@ /* - * File: include/asm-blackfin/mach-bf533/cdefBF532.h - * Based on: - * Author: + * Copyright 2005-2010 Analog Devices Inc. * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF532_H #define _CDEF_BF532_H -#include <asm/blackfin.h> - -/*include all Core registers and bit definitions*/ -#include "defBF532.h" - -/*include core specific register pointer definitions*/ -#include <asm/cdef_LPBlackfin.h> - /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) @@ -95,16 +63,10 @@ #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) /* DMA Traffic controls */ -#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) -#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) -#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) -#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) +#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) +#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) +#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) +#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) @@ -134,6 +96,47 @@ #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) +#if ANOMALY_05000311 +/* Keep at the CPP expansion to avoid circular header dependency loops */ +#define BFIN_WRITE_FIO_FLAG(name, val) \ + do { \ + unsigned long __flags; \ + __flags = hard_local_irq_save(); \ + bfin_write16(FIO_FLAG_##name, val); \ + bfin_read_CHIPID(); \ + hard_local_irq_restore(__flags); \ + } while (0) +#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val) +#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val) +#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val) +#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val) + +#define BFIN_READ_FIO_FLAG(name) \ + ({ \ + unsigned long __flags; \ + u16 __ret; \ + __flags = hard_local_irq_save(); \ + __ret = bfin_read16(FIO_FLAG_##name); \ + bfin_read_CHIPID(); \ + hard_local_irq_restore(__flags); \ + __ret; \ + }) +#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D) +#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C) +#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S) +#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T) + +#else +#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) +#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) +#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) +#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) +#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) +#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) +#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) +#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) +#endif + /* DMA Controller */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) @@ -676,93 +679,4 @@ #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - -#if ANOMALY_05000311 -#define BFIN_WRITE_FIO_FLAG(name) \ -static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ -{ \ - unsigned long flags; \ - local_irq_save_hw(flags); \ - bfin_write16(FIO_FLAG_##name, val); \ - bfin_read_CHIPID(); \ - local_irq_restore_hw(flags); \ -} -BFIN_WRITE_FIO_FLAG(D) -BFIN_WRITE_FIO_FLAG(C) -BFIN_WRITE_FIO_FLAG(S) -BFIN_WRITE_FIO_FLAG(T) - -#define BFIN_READ_FIO_FLAG(name) \ -static inline u16 bfin_read_FIO_FLAG_##name(void) \ -{ \ - unsigned long flags; \ - u16 ret; \ - local_irq_save_hw(flags); \ - ret = bfin_read16(FIO_FLAG_##name); \ - bfin_read_CHIPID(); \ - local_irq_restore_hw(flags); \ - return ret; \ -} -BFIN_READ_FIO_FLAG(D) -BFIN_READ_FIO_FLAG(C) -BFIN_READ_FIO_FLAG(S) -BFIN_READ_FIO_FLAG(T) - -#else -#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) -#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) -#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) -#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) -#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) -#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) -#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) -#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) -#endif - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_PLL_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - local_irq_restore_hw(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_VR_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - local_irq_restore_hw(flags); -} - #endif /* _CDEF_BF532_H */ diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h index 7f4633223e6..d438150b102 100644 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h @@ -1,55 +1,14 @@ -/************************************************************************ - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - ************************************************************************/ /* - * File: include/asm-blackfin/mach-bf533/defBF532.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * System & MMR bit and Address definitions for ADSP-BF532 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. + * Copyright 2005-2010 Analog Devices Inc. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the Clear BSD license or the GPL-2 (or later) */ -/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ #ifndef _DEF_BF532_H #define _DEF_BF532_H -/* include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - /*********************************************************************************** */ /* System MMR Register Map */ /*********************************************************************************** */ @@ -220,12 +179,8 @@ #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ /* DMA Traffic controls */ -#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ @@ -408,72 +363,6 @@ /* System MMR Register Bits */ /******************************************************************************* */ -/* ********************* PLL AND RESET MASKS ************************ */ - -/* PLL_CTL Masks */ -#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */ -#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */ -#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ -#define PLL_OFF 0x0002 /* Shut off PLL clocks */ -#define STOPCK_OFF 0x0008 /* Core clock off */ -#define STOPCK 0x0008 /* Core Clock Off */ -#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */ -#if !defined(__ADSPBF538__) -/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */ -# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ -# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ -#endif -#define BYPASS 0x0100 /* Bypass the PLL */ -/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ -#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ - -/* PLL_DIV Masks */ -#define SSEL 0x000F /* System Select */ -#define CSEL 0x0030 /* Core Select */ - -#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ - -#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ -#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ -#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ -#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ -/* PLL_DIV Macros */ -#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ - -/* PLL_STAT Masks */ -#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ -#define FULL_ON 0x0002 /* Processor In Full On Mode */ -#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ -#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ - -/* VR_CTL Masks */ -#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ -#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ -#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ -#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ -#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ - -#define GAIN 0x000C /* Voltage Level Gain */ -#define GAIN_5 0x0000 /* GAIN = 5 */ -#define GAIN_10 0x0004 /* GAIN = 10 */ -#define GAIN_20 0x0008 /* GAIN = 20 */ -#define GAIN_50 0x000C /* GAIN = 50 */ - -#define VLEV 0x00F0 /* Internal Voltage Level */ -#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ -#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ - -#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ -#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ - /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 #define CHIPID_FAMILY 0x0FFFF000 @@ -536,175 +425,6 @@ #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ -/* ***************************** UART CONTROLLER MASKS ********************** */ - -/* UART_LCR Register */ - -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR Register */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR Register */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER Register */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 -#define IIR_TX_READY 0x02 /* UART_THR empty */ -#define IIR_RX_READY 0x04 /* Receive data ready */ -#define IIR_LINE_CHANGE 0x06 /* Receive line status */ -#define IIR_STATUS 0x06 - -/* UART_GCTL Register */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* ********** SERIAL PORT MASKS ********************** */ - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define DTYPE_NORM 0x0000 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks */ -#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \ - defined(__ADSPBF533__) -# define SLEN 0x001F /*TX Word Length */ -#else -# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ -#endif -#define TXSE 0x0100 /*TX Secondary Enable */ -#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /*TX Right-First Data Order */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -#define DTYPE_NORM 0x0000 /* no companding */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -/* SLEN defined above */ -#define RXSE 0x0100 /*RX Secondary Enable */ -#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /*Right-First Data Order */ - -/*SPORTx_STAT Masks */ -#define RXNE 0x0001 /*RX FIFO Not Empty Status */ -#define RUVF 0x0002 /*RX Underflow Status */ -#define ROVF 0x0004 /*RX Overflow Status */ -#define TXF 0x0008 /*TX FIFO Full Status */ -#define TUVF 0x0010 /*TX Underflow Status */ -#define TOVF 0x0020 /*TX Overflow Status */ -#define TXHRE 0x0040 /*TX Hold Register Empty */ - -/*SPORTx_MCMC1 Masks */ -#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */ -#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */ -/* SPORTx_MCMC1 Macros */ -#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ -/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */ -#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ - -/*SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */ -#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ -#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ -#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ -#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */ -#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */ -#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */ -#define MFD 0x0000F000 /*Multichannel Frame Delay */ -#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ -#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ -#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ -#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ -#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ -#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ -#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ -#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ -#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ -#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ -#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ -#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ -#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ -#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ -#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ -#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ - /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ /* PPI_CONTROL Masks */ @@ -741,54 +461,7 @@ /* ********** DMA CONTROLLER MASKS *********************8 */ -/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */ -#define DMAEN 0x00000001 /* Channel Enable */ -#define WNR 0x00000002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ -#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ -#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ -#define DMA2D 0x00000010 /* 2D/1D* Mode */ -#define RESTART 0x00000020 /* Restart */ -#define DI_SEL 0x00000040 /* Data Interrupt Select */ -#define DI_EN 0x00000080 /* Data Interrupt Enable */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define NDSIZE 0x00000900 /* Next Descriptor Size */ -#define DMAFLOW 0x00007000 /* Flow Control */ -#define DMAFLOW_STOP 0x0000 /* Stop Mode */ -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ -#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ - -#define DMAEN_P 0 /* Channel Enable */ -#define WNR_P 1 /* Channel Direction (W/R*) */ -#define DMA2D_P 4 /* 2D/1D* Mode */ -#define RESTART_P 5 /* Restart */ -#define DI_SEL_P 6 /* Data Interrupt Select */ -#define DI_EN_P 7 /* Data Interrupt Enable */ - -/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ - -#define DMA_DONE 0x00000001 /* DMA Done Indicator */ -#define DMA_ERR 0x00000002 /* DMA Error Indicator */ -#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ -#define DMA_RUN 0x00000008 /* DMA Running Indicator */ - -#define DMA_DONE_P 0 /* DMA Done Indicator */ -#define DMA_ERR_P 1 /* DMA Error Indicator */ -#define DFETCH_P 2 /* Descriptor Fetch Indicator */ -#define DMA_RUN_P 3 /* DMA Running Indicator */ - -/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ @@ -886,114 +559,6 @@ #define ERR_TYP_P0 0x0E #define ERR_TYP_P1 0x0F -/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ -#define PF0_P 0 -#define PF1_P 1 -#define PF2_P 2 -#define PF3_P 3 -#define PF4_P 4 -#define PF5_P 5 -#define PF6_P 6 -#define PF7_P 7 -#define PF8_P 8 -#define PF9_P 9 -#define PF10_P 10 -#define PF11_P 11 -#define PF12_P 12 -#define PF13_P 13 -#define PF14_P 14 -#define PF15_P 15 - -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ - -/* SPI_CTL Masks */ -#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ -#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ -#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ -#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ -#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ -#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ -#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ -#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ -#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ -#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ - -/* SPI_FLG Masks */ -#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ -#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ - -/* SPIx_FLG Masks */ -#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */ -#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */ -#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */ -#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */ -#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */ -#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */ -#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */ - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ /* AMGCTL Masks */ diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h index e45c17077af..cce4f8fb378 100644 --- a/arch/blackfin/mach-bf533/include/mach/gpio.h +++ b/arch/blackfin/mach-bf533/include/mach/gpio.h @@ -1,7 +1,4 @@ /* - * File: arch/blackfin/mach-bf533/include/mach/gpio.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * * Copyright (C) 2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -12,23 +9,25 @@ #define MAX_BLACKFIN_GPIOS 16 -#define GPIO_PF0 0 -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 #define PORT_F GPIO_PF0 +#include <mach-common/ports-f.h> + #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h index db1e346cd1a..70973375414 100644 --- a/arch/blackfin/mach-bf533/include/mach/irq.h +++ b/arch/blackfin/mach-bf533/include/mach/irq.h @@ -1,113 +1,42 @@ /* - * File: include/asm-blackfin/mach-bf533/defBF532.h - * Based on: - * Author: + * Copyright 2005-2008 Analog Devices Inc. * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later */ #ifndef _BF533_IRQ_H_ #define _BF533_IRQ_H_ -/* - * Interrupt source definitions - Event Source Core Event Name -Core Emulation ** - Events (highest priority) EMU 0 - Reset RST 1 - NMI NMI 2 - Exception EVX 3 - Reserved -- 4 - Hardware Error IVHW 5 - Core Timer IVTMR 6 * - PLL Wakeup Interrupt IVG7 7 - DMA Error (generic) IVG7 8 - PPI Error Interrupt IVG7 9 - SPORT0 Error Interrupt IVG7 10 - SPORT1 Error Interrupt IVG7 11 - SPI Error Interrupt IVG7 12 - UART Error Interrupt IVG7 13 - RTC Interrupt IVG8 14 - DMA0 Interrupt (PPI) IVG8 15 - DMA1 (SPORT0 RX) IVG9 16 - DMA2 (SPORT0 TX) IVG9 17 - DMA3 (SPORT1 RX) IVG9 18 - DMA4 (SPORT1 TX) IVG9 19 - DMA5 (PPI) IVG10 20 - DMA6 (UART RX) IVG10 21 - DMA7 (UART TX) IVG10 22 - Timer0 IVG11 23 - Timer1 IVG11 24 - Timer2 IVG11 25 - PF Interrupt A IVG12 26 - PF Interrupt B IVG12 27 - DMA8/9 Interrupt IVG13 28 - DMA10/11 Interrupt IVG13 29 - Watchdog Timer IVG13 30 +#include <mach-common/irq.h> - Softirq IVG14 31 - System Call -- - (lowest priority) IVG15 32 * - */ -#define SYS_IRQS 31 -#define NR_PERI_INTS 24 +#define NR_PERI_INTS 24 -/* The ABSTRACT IRQ definitions */ -/** the first seven of the following are fixed, the rest you change if you need to **/ -#define IRQ_EMU 0 /*Emulation */ -#define IRQ_RST 1 /*reset */ -#define IRQ_NMI 2 /*Non Maskable */ -#define IRQ_EVX 3 /*Exception */ -#define IRQ_UNUSED 4 /*- unused interrupt*/ -#define IRQ_HWERR 5 /*Hardware Error */ -#define IRQ_CORETMR 6 /*Core timer */ +#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ +#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */ +#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */ +#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ +#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */ +#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */ +#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ +#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */ +#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */ +#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */ +#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */ +#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */ +#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */ +#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */ +#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */ +#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */ +#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */ +#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */ +#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */ +#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */ +#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */ +#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */ +#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */ -#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ -#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ -#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */ -#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */ -#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */ -#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */ -#define IRQ_RTC 14 /*RTC Interrupt */ -#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */ -#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */ -#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ -#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ -#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ -#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ -#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */ -#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */ -#define IRQ_TIMER0 23 /*Timer 0 */ -#define IRQ_TIMER1 24 /*Timer 1 */ -#define IRQ_TIMER2 25 /*Timer 2 */ -#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ -#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ -#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ -#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */ -#define IRQ_WATCH 30 /*Watch Dog Timer */ +#define SYS_IRQS 31 #define IRQ_PF0 33 #define IRQ_PF1 34 @@ -128,46 +57,36 @@ Core Emulation ** #define GPIO_IRQ_BASE IRQ_PF0 -#define NR_IRQS (IRQ_PF15+1) - -#define IVG7 7 -#define IVG8 8 -#define IVG9 9 -#define IVG10 10 -#define IVG11 11 -#define IVG12 12 -#define IVG13 13 -#define IVG14 14 -#define IVG15 15 +#define NR_MACH_IRQS (IRQ_PF15 + 1) -/* IAR0 BIT FIELDS*/ -#define RTC_ERROR_POS 28 -#define UART_ERROR_POS 24 -#define SPORT1_ERROR_POS 20 -#define SPI_ERROR_POS 16 -#define SPORT0_ERROR_POS 12 -#define PPI_ERROR_POS 8 -#define DMA_ERROR_POS 4 -#define PLLWAKE_ERROR_POS 0 +/* IAR0 BIT FIELDS */ +#define RTC_ERROR_POS 28 +#define UART_ERROR_POS 24 +#define SPORT1_ERROR_POS 20 +#define SPI_ERROR_POS 16 +#define SPORT0_ERROR_POS 12 +#define PPI_ERROR_POS 8 +#define DMA_ERROR_POS 4 +#define PLLWAKE_ERROR_POS 0 -/* IAR1 BIT FIELDS*/ -#define DMA7_UARTTX_POS 28 -#define DMA6_UARTRX_POS 24 -#define DMA5_SPI_POS 20 -#define DMA4_SPORT1TX_POS 16 -#define DMA3_SPORT1RX_POS 12 -#define DMA2_SPORT0TX_POS 8 -#define DMA1_SPORT0RX_POS 4 -#define DMA0_PPI_POS 0 +/* IAR1 BIT FIELDS */ +#define DMA7_UARTTX_POS 28 +#define DMA6_UARTRX_POS 24 +#define DMA5_SPI_POS 20 +#define DMA4_SPORT1TX_POS 16 +#define DMA3_SPORT1RX_POS 12 +#define DMA2_SPORT0TX_POS 8 +#define DMA1_SPORT0RX_POS 4 +#define DMA0_PPI_POS 0 -/* IAR2 BIT FIELDS*/ -#define WDTIMER_POS 28 -#define MEMDMA1_POS 24 -#define MEMDMA0_POS 20 -#define PFB_POS 16 -#define PFA_POS 12 -#define TIMER2_POS 8 -#define TIMER1_POS 4 -#define TIMER0_POS 0 +/* IAR2 BIT FIELDS */ +#define WDTIMER_POS 28 +#define MEMDMA1_POS 24 +#define MEMDMA0_POS 20 +#define PFB_POS 16 +#define PFA_POS 12 +#define TIMER2_POS 8 +#define TIMER1_POS 4 +#define TIMER0_POS 0 -#endif /* _BF533_IRQ_H_ */ +#endif diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h index fc33b7cb993..197af1a398a 100644 --- a/arch/blackfin/mach-bf533/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf533/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * File: include/asm-blackfin/mach-bf533/mem_map.h - * Based on: - * Author: + * BF533 memory map * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_533_H_ -#define _MEM_MAP_533_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -158,20 +136,4 @@ #endif -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_533_H_ */ +#endif diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h new file mode 100644 index 00000000000..94cca674d83 --- /dev/null +++ b/arch/blackfin/mach-bf533/include/mach/pll.h @@ -0,0 +1 @@ +#include <mach-common/pll.h> diff --git a/arch/blackfin/mach-bf533/include/mach/portmux.h b/arch/blackfin/mach-bf533/include/mach/portmux.h index 2f59ce0b0cb..96f5d9129f2 100644 --- a/arch/blackfin/mach-bf533/include/mach/portmux.h +++ b/arch/blackfin/mach-bf533/include/mach/portmux.h @@ -1,7 +1,13 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ -#define MAX_RESOURCES MAX_BLACKFIN_GPIOS +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS #define P_PPI0_CLK (P_DONTCARE) #define P_PPI0_FS1 (P_DONTCARE) @@ -54,6 +60,7 @@ #define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) #define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) #define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 #define P_TMR2 (P_DONTCARE) |