diff options
Diffstat (limited to 'arch/blackfin/mach-bf533/include/mach/cdefBF532.h')
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/cdefBF532.h | 180 |
1 files changed, 47 insertions, 133 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h index bbc3c8386d4..fd0cbe4df21 100644 --- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h @@ -1,44 +1,12 @@ /* - * File: include/asm-blackfin/mach-bf533/cdefBF532.h - * Based on: - * Author: + * Copyright 2005-2010 Analog Devices Inc. * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF532_H #define _CDEF_BF532_H -#include <asm/blackfin.h> - -/*include all Core registers and bit definitions*/ -#include "defBF532.h" - -/*include core specific register pointer definitions*/ -#include <asm/cdef_LPBlackfin.h> - /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) @@ -95,16 +63,10 @@ #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) /* DMA Traffic controls */ -#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) -#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) -#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) -#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) +#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) +#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) +#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) +#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) @@ -134,6 +96,47 @@ #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) +#if ANOMALY_05000311 +/* Keep at the CPP expansion to avoid circular header dependency loops */ +#define BFIN_WRITE_FIO_FLAG(name, val) \ + do { \ + unsigned long __flags; \ + __flags = hard_local_irq_save(); \ + bfin_write16(FIO_FLAG_##name, val); \ + bfin_read_CHIPID(); \ + hard_local_irq_restore(__flags); \ + } while (0) +#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val) +#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val) +#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val) +#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val) + +#define BFIN_READ_FIO_FLAG(name) \ + ({ \ + unsigned long __flags; \ + u16 __ret; \ + __flags = hard_local_irq_save(); \ + __ret = bfin_read16(FIO_FLAG_##name); \ + bfin_read_CHIPID(); \ + hard_local_irq_restore(__flags); \ + __ret; \ + }) +#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D) +#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C) +#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S) +#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T) + +#else +#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) +#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) +#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) +#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) +#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) +#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) +#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) +#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) +#endif + /* DMA Controller */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) @@ -676,93 +679,4 @@ #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - -#if ANOMALY_05000311 -#define BFIN_WRITE_FIO_FLAG(name) \ -static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ -{ \ - unsigned long flags; \ - local_irq_save_hw(flags); \ - bfin_write16(FIO_FLAG_##name, val); \ - bfin_read_CHIPID(); \ - local_irq_restore_hw(flags); \ -} -BFIN_WRITE_FIO_FLAG(D) -BFIN_WRITE_FIO_FLAG(C) -BFIN_WRITE_FIO_FLAG(S) -BFIN_WRITE_FIO_FLAG(T) - -#define BFIN_READ_FIO_FLAG(name) \ -static inline u16 bfin_read_FIO_FLAG_##name(void) \ -{ \ - unsigned long flags; \ - u16 ret; \ - local_irq_save_hw(flags); \ - ret = bfin_read16(FIO_FLAG_##name); \ - bfin_read_CHIPID(); \ - local_irq_restore_hw(flags); \ - return ret; \ -} -BFIN_READ_FIO_FLAG(D) -BFIN_READ_FIO_FLAG(C) -BFIN_READ_FIO_FLAG(S) -BFIN_READ_FIO_FLAG(T) - -#else -#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) -#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) -#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) -#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) -#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) -#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) -#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) -#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) -#endif - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_PLL_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - local_irq_restore_hw(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_VR_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - local_irq_restore_hw(flags); -} - #endif /* _CDEF_BF532_H */ |