diff options
Diffstat (limited to 'arch/arc/plat-arcfpga')
| -rw-r--r-- | arch/arc/plat-arcfpga/Kconfig | 33 | ||||
| -rw-r--r-- | arch/arc/plat-arcfpga/Makefile | 2 | ||||
| -rw-r--r-- | arch/arc/plat-arcfpga/platform.c | 78 | ||||
| -rw-r--r-- | arch/arc/plat-arcfpga/smp.c | 30 |
4 files changed, 32 insertions, 111 deletions
diff --git a/arch/arc/plat-arcfpga/Kconfig b/arch/arc/plat-arcfpga/Kconfig index 295cefeb25d..e27bb5cc3c1 100644 --- a/arch/arc/plat-arcfpga/Kconfig +++ b/arch/arc/plat-arcfpga/Kconfig @@ -33,7 +33,6 @@ config ISS_SMP_EXTN bool "ARC SMP Extensions (ISS Models only)" default n depends on SMP - select ARC_HAS_COH_RTSC help SMP Extensions to ARC700, in a "simulation only" Model, supported in ARC ISS (Instruction Set Simulator). @@ -49,36 +48,4 @@ config ARC_SERIAL_BAUD help Baud rate for the ARC UART -menuconfig ARC_HAS_BVCI_LAT_UNIT - bool "BVCI Bus Latency Unit" - depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4 - help - IP to add artificial latency to BVCI Bus Based FPGA builds. - The default latency (even worst case) for FPGA is non-realistic - (~10 SDRAM, ~5 SSRAM). - -config BVCI_LAT_UNITS - hex "Latency Unit(s) Bitmap" - default "0x0" - depends on ARC_HAS_BVCI_LAT_UNIT - help - There are multiple Latency Units corresponding to the many - interfaces of the system bus arbiter (both CPU side as well as - the peripheral side). - To add latency to ALL memory transaction, choose Unit 0, otherwise - for finer grainer - interface wise latency, specify a bitmap (1 bit - per unit) of all units. e.g. 1,2,12 will be 0x1003 - - Unit 0 - System Arb and Mem Controller - Unit 1 - I$ and System Bus - Unit 2 - D$ and System Bus - .. - Unit 12 - IDE Disk controller and System Bus - -config BVCI_LAT_CYCLES - int "Latency Value in cycles" - range 0 63 - default "30" - depends on ARC_HAS_BVCI_LAT_UNIT - endif diff --git a/arch/arc/plat-arcfpga/Makefile b/arch/arc/plat-arcfpga/Makefile index a44e22ebc1b..4d1bddc34b5 100644 --- a/arch/arc/plat-arcfpga/Makefile +++ b/arch/arc/plat-arcfpga/Makefile @@ -9,4 +9,4 @@ KBUILD_CFLAGS += -Iarch/arc/plat-arcfpga/include obj-y := platform.o irq.o -obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_ISS_SMP_EXTN) += smp.o diff --git a/arch/arc/plat-arcfpga/platform.c b/arch/arc/plat-arcfpga/platform.c index d71f3c3bcf2..61c7e599738 100644 --- a/arch/arc/plat-arcfpga/platform.c +++ b/arch/arc/plat-arcfpga/platform.c @@ -22,59 +22,6 @@ #include <plat/smp.h> #include <plat/irq.h> -/*-----------------------BVCI Latency Unit -----------------------------*/ - -#ifdef CONFIG_ARC_HAS_BVCI_LAT_UNIT - -int lat_cycles = CONFIG_BVCI_LAT_CYCLES; - -/* BVCI Bus Profiler: Latency Unit */ -static void __init setup_bvci_lat_unit(void) -{ -#define MAX_BVCI_UNITS 12 - - unsigned int i; - unsigned int *base = (unsigned int *)BVCI_LAT_UNIT_BASE; - const unsigned long units_req = CONFIG_BVCI_LAT_UNITS; - const unsigned int REG_UNIT = 21; - const unsigned int REG_VAL = 22; - - /* - * There are multiple Latency Units corresponding to the many - * interfaces of the system bus arbiter (both CPU side as well as - * the peripheral side). - * - * Unit 0 - System Arb and Mem Controller - adds latency to all - * memory trasactions - * Unit 1 - I$ and System Bus - * Unit 2 - D$ and System Bus - * .. - * Unit 12 - IDE Disk controller and System Bus - * - * The programmers model requires writing to lat_unit reg first - * and then the latency value (cycles) to lat_value reg - */ - - if (CONFIG_BVCI_LAT_UNITS == 0) { - writel(0, base + REG_UNIT); - writel(lat_cycles, base + REG_VAL); - pr_info("BVCI Latency for all Memory Transactions %d cycles\n", - lat_cycles); - } else { - for_each_set_bit(i, &units_req, MAX_BVCI_UNITS) { - writel(i + 1, base + REG_UNIT); /* loop is 0 based */ - writel(lat_cycles, base + REG_VAL); - pr_info("BVCI Latency for Unit[%d] = %d cycles\n", - (i + 1), lat_cycles); - } - } -} -#else -static void __init setup_bvci_lat_unit(void) -{ -} -#endif - /*----------------------- Platform Devices -----------------------------*/ #if IS_ENABLED(CONFIG_SERIAL_ARC) @@ -132,16 +79,11 @@ static void arc_fpga_serial_init(void) ARRAY_SIZE(fpga_early_devs)); /* - * ARC console driver registers itself as an early platform driver - * of class "earlyprintk". - * Install it here, followed by probe of devices. - * The installation here doesn't require earlyprintk in command line - * To do so however, replace the lines below with - * parse_early_param(); - * early_platform_driver_probe("earlyprintk", 1, 1); - * ^^ + * ARC console driver registers (build time) as an early platform driver + * of class "earlyprintk". However it needs explicit cmdline toggle + * "earlyprintk=ttyARC0" to be successfuly runtime registered. + * Otherwise the early probe below fails to find the driver */ - early_platform_driver_register_all("earlyprintk"); early_platform_driver_probe("earlyprintk", 1, 0); /* @@ -165,11 +107,9 @@ static void __init plat_fpga_early_init(void) { pr_info("[plat-arcfpga]: registering early dev resources\n"); - setup_bvci_lat_unit(); - arc_fpga_serial_init(); -#ifdef CONFIG_SMP +#ifdef CONFIG_ISS_SMP_EXTN iss_model_init_early_smp(); #endif } @@ -201,7 +141,7 @@ static void __init plat_fpga_populate_dev(void) * callback set, by matching the DT compatible name. */ -static const char *aa4_compat[] __initdata = { +static const char *aa4_compat[] __initconst = { "snps,arc-angel4", NULL, }; @@ -211,12 +151,12 @@ MACHINE_START(ANGEL4, "angel4") .init_early = plat_fpga_early_init, .init_machine = plat_fpga_populate_dev, .init_irq = plat_fpga_init_IRQ, -#ifdef CONFIG_SMP +#ifdef CONFIG_ISS_SMP_EXTN .init_smp = iss_model_init_smp, #endif MACHINE_END -static const char *ml509_compat[] __initdata = { +static const char *ml509_compat[] __initconst = { "snps,arc-ml509", NULL, }; @@ -231,7 +171,7 @@ MACHINE_START(ML509, "ml509") #endif MACHINE_END -static const char *nsimosci_compat[] __initdata = { +static const char *nsimosci_compat[] __initconst = { "snps,nsimosci", NULL, }; diff --git a/arch/arc/plat-arcfpga/smp.c b/arch/arc/plat-arcfpga/smp.c index 91b55349a5f..92bad912207 100644 --- a/arch/arc/plat-arcfpga/smp.c +++ b/arch/arc/plat-arcfpga/smp.c @@ -42,6 +42,24 @@ static void iss_model_smp_wakeup_cpu(int cpu, unsigned long pc) } +static inline int get_hw_config_num_irq(void) +{ + uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR); + + switch (val & 0x03) { + case 0: + return 16; + case 1: + return 32; + case 2: + return 8; + default: + return 0; + } + + return 0; +} + /* * Any SMP specific init any CPU does when it comes up. * Here we setup the CPU to enable Inter-Processor-Interrupts @@ -88,18 +106,14 @@ void iss_model_init_smp(unsigned int cpu) smp_ipi_irq_setup(cpu, IDU_INTERRUPT_0 + cpu); } -static void iss_model_ipi_send(void *arg) +static void iss_model_ipi_send(int cpu) { - struct cpumask *callmap = arg; - unsigned int cpu; - - for_each_cpu(cpu, callmap) - idu_irq_assert(cpu); + idu_irq_assert(cpu); } -static void iss_model_ipi_clear(int cpu, int irq) +static void iss_model_ipi_clear(int irq) { - idu_irq_clear(IDU_INTERRUPT_0 + cpu); + idu_irq_clear(IDU_INTERRUPT_0 + smp_processor_id()); } void iss_model_init_early_smp(void) |