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path: root/test/MC/Disassembler
AgeCommit message (Expand)Author
2013-05-05[XCore] Add LDAPB instructions.Richard Osborne
2013-05-05[XCore] Add BLRB instructions.Richard Osborne
2013-04-30s tightens up the encoding description for ARM post-indexed ldr instructions....Mihai Popa
2013-04-26ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet
2013-04-19ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover
2013-04-19ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover
2013-04-18[mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka
2013-04-14Use object file specific section type for initial text sectionNico Rieck
2013-04-12ARM: Correct printing of pre-indexed operands.Quentin Colombet
2013-04-11Add CLAC/STAC instruction encoding/decoding supportMichael Liao
2013-04-10fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo
2013-04-10ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover
2013-04-04[XCore] Add bru instruction.Richard Osborne
2013-04-04[XCore] The RRegs register class is a superset of GRRegs.Richard Osborne
2013-04-03[XCore] Check disassembly of the st8 instruction.Richard Osborne
2013-04-03[XCore] Update disassembler test to improve coverage of the instructions.Richard Osborne
2013-04-03AArch64: implement ETMv4 trace system registers.Tim Northover
2013-03-28Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when th...Gordon Keiser
2013-03-28AArch64: implement GICv3 system registersTim Northover
2013-03-26Patch by Gordon Keiser!Joe Abbey
2013-03-25x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki
2013-03-11Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby
2013-02-28AArch64: remove post-encoder method from FCMP (immediate) instructions.Tim Northover
2013-02-22Make ARMAsmPrinter generate the correct alignment specifier syntax in instruc...Kristof Beyls
2013-02-17[XCore] Add missing 2r instructions.Richard Osborne
2013-02-17[XCore] Add TSETR instruction.Richard Osborne
2013-02-17[XCore] Add missing u10 / lu10 instructions.Richard Osborne
2013-02-17[XCore] Add missing u6 / lu6 instructions.Richard Osborne
2013-02-14death to extra whitespaceKay Tiong Khoo
2013-02-14added basic support for Intel ADX instructionsKay Tiong Khoo
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
2013-02-12added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo
2013-02-11*fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo
2013-02-06Add AArch64 CRC32 instructionsTim Northover
2013-02-06Add icache prefetch operations to AArch64Tim Northover
2013-01-31Add AArch64 as an experimental target.Tim Northover
2013-01-27[XCore] Add missing l2rus instructions.Richard Osborne
2013-01-27[XCore] Add missing l2r instructions.Richard Osborne
2013-01-27[XCore] Add missing 1r instructions.Richard Osborne
2013-01-27[XCore] Add missing 0r instructions.Richard Osborne
2013-01-25Add instruction encodings / disassembly support for l4r instructions.Richard Osborne
2013-01-25Add instruction encodings / disassembly support for l5r instructions.Richard Osborne
2013-01-23Add instruction encodings / disassembly support for l6r instructions.Richard Osborne
2013-01-22Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne
2013-01-21Add instruction encodings / disassembly support for u6 / lu6 instructions.Richard Osborne
2013-01-21Add instruction encoding / disassembly support for ru6 / lru6 instructions.Richard Osborne
2013-01-20Add instruction encodings / disassembly support for l2rus instructions.Richard Osborne
2013-01-20Add instruction encodings / disassembly support for l3r instructions.Richard Osborne
2013-01-20Add instruction encodings / disassembler support for 2rus instructions.Richard Osborne
2013-01-20Add instruction encodings / disassembly support 3r instructions.Richard Osborne
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