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2012-11-17Silence the buildbots for this test while I figure out the tripleAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168249 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17Broaden isSchedulingBoundary to check aliases of SP.Andrew Trick
On PPC the stack pointer is X1, but ADJCALLSTACK writes R1. Fixes PR14315: Register regmask dependency problem with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete ↵Eli Friedman
Couperus. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17[fast-isel] Add the -verify-machineinstrs to these test cases. The remainingChad Rosier
test cases require fixes to fast-isel before the verifier can be enabled. Part of rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17Initial implementation of MipsTargetLowering::isLegalAddressingMode.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao
This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Make sure FABS on v2f32 and v4f32 is legal on ARM NEONAnton Korobeynikov
This fixes PR14359 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168200 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Fix handling of aliases to functions.Richard Osborne
An alias to a function should use pc relative addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16[NVPTX] Order global variables in def-use order before emiting them in the ↵Justin Holewinski
final assembly git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168198 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16llvm/test/CodeGen/X86/hipe-cc*.ll: Add explicit -mcpu, or they don't expect ↵NAKAMURA Takumi
to pass on Atom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of ↵Craig Topper
vector types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168141 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16[mips] Fix delay slot filler so that instructions with register operand $1 areAkira Hatanaka
allowed in branch delay slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman
case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15PowerPC: Lowering floor intrinsic for AltivecAdhemerval Zanella
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and llvm.nearbyint to Altivec instruction when using 4 single-precision float vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Merge commit '08e9cb46feb0c8e08e3d309a0f9fd75a04ca54fb'Derek Schuff
(svn r167699, also the 3.2 branch point) Conflicts: lib/Target/X86/X86Subtarget.cpp
2012-11-14This patch is in preparation for adding medium code model support to theBill Schmidt
PPC64 target. The five tests modified herein test code generation that is sensitive to the code model selected. So I've added -code-model=small to the RUN commands for each. Since small code model is the default, this has no effect for now; but this prepares us for eventually changing the default to medium code model for PPC64. Test changes verified with small and medium code model as default on powerpc64-unknown-linux-gnu. All tests continue to pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Make sure to not get AVX code on an AVX-capable host. Revealed in r167967.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167989 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the ↵NAKAMURA Takumi
failure on i686 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167988 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Remove the CellSPU port.Eric Christopher
Approved by Chris Lattner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14llvm/test/CodeGen/X86/memset.ll: FileCheck-ize, and add another case on +avx.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167975 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Added multiclass for post-increment load instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Force CPU in test so we don't accidentally get AVX code on an AVX-capable host.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167973 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14X86: Enable SSE memory intrinsics even when stack alignment is less than 16 ↵Benjamin Kramer
bytes. The stack realignment code was fixed to work when there is stack realignment and a dynamic alloca is present so this shouldn't cause correctness issues anymore. Note that this also enables generation of AVX instructions for memset under the assumptions: - Unaligned loads/stores are always fast on CPUs supporting AVX - AVX is not slower than SSE We may need some tweaked heuristics if one of those assumptions turns out not to be true. Effectively reverts r58317. Part of PR2962. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167967 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14The code pattern "imm0_255_neg" is used for checking if an immediate value ↵Nadav Rotem
is a small negative number. This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag. rdar://12028498 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167963 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14[NVPTX] Implement custom lowering of loads/stores for i1Justin Holewinski
Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 Fixes PR13291 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Fix really stupid ARM EHABI info generation bug: we should not emitAnton Korobeynikov
eh table and handler data if there are no landing pads in the function. Patch by Logan Chien with some cleanups from me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Merge commit 'be02a90de17f857ba65bbd8a11653ca1bad30adc'Derek Schuff
Conflicts: lib/Target/Mips/MipsISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFormats.td
2012-11-14Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov
Do some cleanup of the code while here. Inspired by patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Revert "Use the 'count' attribute instead of the 'upper_bound' attribute."Eric Christopher
temporarily as it is breaking the gdb bots. This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167886 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13X86: when constructing VZEXT_LOAD from other loads, makes sure its outputManman Ren
chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://12684358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Do not consider a machine instruction that uses and defines the sameUlrich Weigand
physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Codegen support for arbitrary vector getelementptrs.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Use the 'count' attribute instead of the 'upper_bound' attribute.Bill Wendling
If we have a type 'int a[1]' and a type 'int b[0]', the generated DWARF is the same for both of them because we use the 'upper_bound' attribute. Instead use the 'count' attrbute, which gives the correct number of elements in the array. <rdar://problem/12566646> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Cleanup the main RegisterCoalescer loop.Andrew Trick
Block priorities still apply outside loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Fix test case added in patch fixing PR14314Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Infrastructure for weak DAG edges.Andrew Trick
This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Fix PR14314Michael Liao
- Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12[NVPTX] Add more precise PTX/SM target attributesJustin Holewinski
Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Convert an improper CodeGen test to a MC test.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167663 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10xfail a bad test. This is a MC test but it's dependent on a codegen ↵Evan Cheng
optimization which is now disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Disable the Thumb no-return call optimization:Evan Cheng
mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09[NVPTX] Use ABI alignment for parameters when alignment is not specified.Justin Holewinski
Affects SM 2.0+. Fixes bug 13324. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Fix assertions in updateRegMaskSlots().Jakob Stoklund Olesen
The RegMaskSlots contains 'r' slots while NewIdx and OldIdx are 'B' slots. This broke the checks in the assertions. This fixes PR14302. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08Recommit modified r167540.Amara Emerson
Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08Add support of RTM from TSX extensionMichael Liao
- Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.Akira Hatanaka
Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07misched: Heuristics based on the machine model.Andrew Trick
misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8
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