diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-16 02:39:34 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-16 02:39:34 +0000 |
| commit | a032dbd62f46a40b2cf759ce0dd0ebd41ef0614c (patch) | |
| tree | 1526a67e09837250eaa27e9da8776f1710166ad3 /test/CodeGen | |
| parent | 96952bd3b10d6a880b406461e2373b8781abc919 (diff) | |
[mips] Fix delay slot filler so that instructions with register operand $1 are
allowed in branch delay slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168131 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/Mips/brdelayslot.ll | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll index 2fdb736dc8..897fc9768f 100644 --- a/test/CodeGen/Mips/brdelayslot.ll +++ b/test/CodeGen/Mips/brdelayslot.ll @@ -35,3 +35,35 @@ entry: declare void @foo4(double) +@g2 = external global i32 +@g1 = external global i32 +@g3 = external global i32 + +; Check that branch delay slot can be filled with an instruction with operand +; $1. +; +; Default: foo5: +; Default-NOT: nop + +define void @foo5(i32 %a) nounwind { +entry: + %0 = load i32* @g2, align 4 + %tobool = icmp eq i32 %a, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: + %1 = load i32* @g1, align 4 + %add = add nsw i32 %1, %0 + store i32 %add, i32* @g1, align 4 + br label %if.end + +if.else: + %2 = load i32* @g3, align 4 + %sub = sub nsw i32 %2, %0 + store i32 %sub, i32* @g3, align 4 + br label %if.end + +if.end: + ret void +} + |