aboutsummaryrefslogtreecommitdiff
path: root/test/CodeGen
AgeCommit message (Collapse)Author
2009-12-12Disable r91104 for x86. It causes partial register stall which pessimize ↵Evan Cheng
code in 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91223 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Lower setcc branchless, if this is profitable.Anton Korobeynikov
Based on the patch by Brian Lucas! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91175 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Change this to the correct PR number.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91148 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Fix the result type of SELECT nodes lowered from Select instructions withDan Gohman
aggregate return values. This fixes PR5754. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91145 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Honour setHasCalls() set from isel.Anton Korobeynikov
This is used in some weird cases like general dynamic TLS model. This fixes PR5723 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91144 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Tests for 91103 and 91104.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91105 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-10It's not safe to coalesce a move where src and dst registers have different ↵Evan Cheng
subregister indices. e.g.: %reg16404:1<def> = MOV8rr %reg16412:2<kill> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91061 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Fix test.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Optimize splat of a scalar load into a shuffle of a vector load when it's ↵Evan Cheng
legal. e.g. vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0> => vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1> iff ptr is 16-byte aligned (or can be made into 16-byte aligned). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90984 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng
isl lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-08- Support inline asm 'w' constraint for 128-bit vector types.Evan Cheng
- Also support the 'q' NEON registers asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-08Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra ↵Anton Korobeynikov
instruction. Patch inspired by Brian Lucas! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90819 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-07Use FileCheck and set nounwind on calls.David Greene
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90790 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-07Don't enable the post-RA scheduler on x86 except at -O3. In itsDan Gohman
current form, it is too expensive in compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-06Dynamic stack realignment use of sp register as source/dest registerAnton Korobeynikov
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode. Emit the following code instead: mov r4, sp bic r4, r4, #15 mov sp, r4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90724 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90653 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-04Also attempt trivial coalescing for live intervals that end in a copy.Jakob Stoklund Olesen
The coalescer is supposed to clean these up, but when setting up parameters for a function call, there may be copies to physregs. If the defining instruction has been LICM'ed far away, the coalescer won't touch it. The register allocation hint does not always work - when the register allocator is backtracking, it clears the hints. This patch takes care of a few more cases that r90163 missed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90502 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03Don't pull vector sext through both hands of a logical operation, since ↵Nate Begeman
doing so prevents the fusion of vector sext and setcc into vsetcc. Add a testcase for the above transformation. Fix a bogus use of APInt noticed while tracking this down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03Recognize canonical forms of vector shuffles where the same vector is used forBob Wilson
both source operands. In the canonical form, the 2nd operand is changed to an undef and the shuffle mask is adjusted to only reference elements from the 1st operand. Radar 7434842. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90417 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-02Remove unnecessary check.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90352 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01Fix PR5391: support early clobber physical register def tied with a use (ewwww)Evan Cheng
- A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber. - If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range. - Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90269 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01test case for IV-Users simplification loop improvementJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90260 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01Use CFG connectedness as a secondary sort key when deciding the order of ↵Jakob Stoklund Olesen
copy coalescing. This means that well connected blocks are copy coalesced before the less connected blocks. Connected blocks are more difficult to coalesce because intervals are more complicated, so handling them first gives a greater chance of success. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90194 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01Fix PR5614: parts of a physical register def may be killed the rest.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90180 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-30New virtual registers created for spill intervals should inherit allocation ↵Jakob Stoklund Olesen
hints from the original register. This helps us avoid silly copies when rematting values that are copied to a physical register: leaq _.str44(%rip), %rcx movq %rcx, %rsi call _strcmp becomes: leaq _.str44(%rip), %rsi call _strcmp The coalescer will not touch the movq because that would tie down the physical register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90163 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-30Add test case for r90108Mon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90109 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-27While this test is testing a problem in the generic part of codegen,Duncan Sands
the problem only shows for msp430 and pic16 which is why it specifies them using -march. But it is wrong to put such tests in CodeGen/Generic, since not everyone builds these targets. Put a copy of the test in each of the target test directories. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90005 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-26Test for 89905.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89906 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-25ProcessImplicitDefs should watch out for invalidated iterator and extra ↵Evan Cheng
implicit operands on copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89880 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-25Support PIC loading of constant pool entriesBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89863 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24Do not store R31 into the caller's link area on PPC.Dale Johannesen
This violates the ABI (that area is "reserved"), and while it is safe if all code is generated with current compilers, there is some very old code around that uses that slot for something else, and breaks if it is stored into. Adjust testcases looking for current behavior. I've verified that the stack frame size is right in all testcases, whether it changed or not. 7311323. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89811 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24Enable predication of NEON instructions in Thumb2 mode.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov
than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23move fconst[sd] to UAL. <rdar://7414913>Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23update test for 89694Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89695 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22Miss two, PR5307.Edward O'Callaghan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89596 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22Convert Thumb2 tests to FileCheck for PR5307.Edward O'Callaghan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89595 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22Turns out stuff gets allocated to different registers depending on the ↵Benjamin Kramer
subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89594 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22Convert ARM tests to FileCheck for PR5307.Edward O'Callaghan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89593 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22Convert test to FileCheck.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89589 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22Forgot to alter RUN line when converting to FileCheck.Edward O'Callaghan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89588 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22Fix for bad FileCheck converts in revision 89584.Edward O'Callaghan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89586 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22Convert a few tests to FileCheck for PR5307.Edward O'Callaghan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89584 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21Revert 89562. We're being sneakier than I was giving us credit for, and thisJim Grosbach
isn't necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89568 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21Darwin requires a frame pointer for all non-leaf functions to support correctJim Grosbach
backtraces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89562 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21Don't leave temporary files in the test directory.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89531 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21When generating a vector the really slow way, via loadsDale Johannesen
and stores, handle the case where the element size is not a valid target type correctly (PPC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20Enable hoisting load from constant memories.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89510 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20Recommitting PALIGNR shift width fixes.Sean Callanan
Thanks to Daniel Dunbar for fixing clang intrinsics: http://llvm.org/viewvc/llvm-project?view=rev&revision=89499 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89500 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2026-02-21 18:27:30 +0000