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path: root/test/CodeGen/Mips/fp-indexed-ls.ll
AgeCommit message (Collapse)Author
2012-07-31Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined asAkira Hatanaka
single-precision load and store. Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect to map unaligned floating point load/store nodes to these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Fix bugs which were introduced when support for base+index floating point loadsAkira Hatanaka
and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Add support for floating point base register + offset register addressing modeAkira Hatanaka
load and store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8