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AgeCommit message (Expand)Author
2010-11-12Add conditional mvn instructions.Evan Cheng
2010-11-12Add some missing isel predicates on def : pat patterns to avoid generating VF...Evan Cheng
2010-11-08Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson
2010-11-08Revert 118422 in search of bot verdancy.Dale Johannesen
2010-11-08Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim
2010-11-05Add codegen and encoding support for the immediate form of vbic.Owen Anderson
2010-11-04Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immedia...Evan Cheng
2010-11-03Covert VORRIMM to be produced via early target-specific DAG combining, rather...Owen Anderson
2010-11-03Add support for code generation of the one register with immediate form of vorr.Owen Anderson
2010-11-03Fix test.Evan Cheng
2010-11-03Add codegen patterns for VST1-lane instructions. Radar 8599955.Bob Wilson
2010-11-03Check for extractelement with a variable operand for the element number.Bob Wilson
2010-11-03Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten...Evan Cheng
2010-11-03Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng
2010-11-03Two sets of changes. Sorry they are intermingled.Evan Cheng
2010-11-02Inline asm mult-alt constraint tests.John Thompson
2010-11-02Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach
2010-11-01Add support for alignment operands on VLD1-lane instructions.Bob Wilson
2010-11-01Add VLD1-lane testcases for quad-register types.Bob Wilson
2010-11-01Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson
2010-11-01When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling
2010-11-01NEON does not support truncating vector stores. Radar 8598391.Bob Wilson
2010-11-01More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when theBill Wendling
2010-11-01Disable because peephole is disabled.Bill Wendling
2010-10-29Teach machine cse to eliminate instructions with multiple physreg uses and de...Evan Cheng
2010-10-29Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson
2010-10-28Teach the DAG combiner to fold a splat of a splat. Radar 8597790.Bob Wilson
2010-10-28Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng
2010-10-28Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ...Evan Cheng
2010-10-28- Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng
2010-10-27Shifter ops are not always free. Do not fold them (especially to formEvan Cheng
2010-10-27SelectionDAG shuffle nodes do not allow operands with different numbers ofBob Wilson
2010-10-26FileCheck'izeJim Grosbach
2010-10-26When the "true" and "false" blocks of a diamond if-conversion are the same,Bob Wilson
2010-10-25Add support for emitting ARM file attributes.Rafael Espindola
2010-10-22tidy upJim Grosbach
2010-10-22Remove duplicate test.Jim Grosbach
2010-10-22tidy up.Jim Grosbach
2010-10-22FileCheck-ize a few tests.Jim Grosbach
2010-10-21putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick
2010-10-21Revert r116983, which is breaking all the buildbots.Owen Anderson
2010-10-21Add missing scheduling itineraries for transfers between core registers and V...Evan Cheng
2010-10-19Re-enable register pressure aware machine licm with fixes. Hoist() may haveEvan Cheng
2010-10-19Revert r116781 "- Add a hook for target to determine whether an instruction defDaniel Dunbar
2010-10-19- Add a hook for target to determine whether an instruction def isEvan Cheng
2010-10-19Support alignment for NEON vld-lane and vst-lane instructions.Bob Wilson
2010-10-18Revert r116220 - thus turning arm fast isel back on by default.Eric Christopher
2010-10-15ARM instructions that are both predicated and set the condition codesBob Wilson
2010-10-14Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudosJim Grosbach
2010-10-14Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'Jim Grosbach
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