aboutsummaryrefslogtreecommitdiff
path: root/test/CodeGen/ARM
diff options
context:
space:
mode:
authorBob Wilson <bob.wilson@apple.com>2010-10-15 03:23:44 +0000
committerBob Wilson <bob.wilson@apple.com>2010-10-15 03:23:44 +0000
commitcfbece50f602c561c5eac046bcfc9a07c8c006cb (patch)
tree904ee8a1d808cf76884285c7601f21e19b84dc78 /test/CodeGen/ARM
parent197a8df6405511e78265b09b6b313c30e7679094 (diff)
ARM instructions that are both predicated and set the condition codes
have been printed with the "S" modifier after the predicate. With ARM's unified syntax, they are supposed to go in the other order. We fixed this for Thumb when we switched to unified syntax but missed changing it for ARM. Apparently we don't generate these instructions often because no one noticed until now. Thanks to Bill Wendling for the testcase! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r--test/CodeGen/ARM/arm-and-tst-peephole.ll47
1 files changed, 47 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll
index 5b70decd8c..412ecdcbb7 100644
--- a/test/CodeGen/ARM/arm-and-tst-peephole.ll
+++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll
@@ -59,3 +59,50 @@ sw.bb8: ; preds = %tailrecurse.switch
sw.epilog: ; preds = %tailrecurse.switch
ret %struct.Foo* undef
}
+
+; Another test that exercises the AND/TST peephole optimization and also
+; generates a predicated ANDS instruction. Check that the predicate is printed
+; after the "S" modifier on the instruction.
+
+%struct.S = type { i8* (i8*)*, [1 x i8] }
+
+; CHECK: bar
+; THUMB: bar
+; T2: bar
+define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
+entry:
+ %0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0
+ %1 = load i8* %0, align 1
+ %2 = zext i8 %1 to i32
+; CHECK: ands
+; THUMB: ands
+; T2: ands
+ %3 = and i32 %2, 112
+ %4 = icmp eq i32 %3, 0
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+ %5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0
+ %6 = load i8* %5, align 1
+ %7 = zext i8 %6 to i32
+; CHECK: andsne
+; THUMB: ands
+; T2: andsne
+ %8 = and i32 %7, 112
+ %9 = icmp eq i32 %8, 0
+ br i1 %9, label %return, label %bb2
+
+bb2: ; preds = %bb
+ %10 = icmp eq i32 %3, 16
+ %11 = icmp eq i32 %8, 16
+ %or.cond = or i1 %10, %11
+ br i1 %or.cond, label %bb4, label %return
+
+bb4: ; preds = %bb2
+ %12 = ptrtoint %struct.S* %x to i32
+ %phitmp = trunc i32 %12 to i8
+ ret i8 %phitmp
+
+return: ; preds = %bb2, %bb, %entry
+ ret i8 1
+}