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2013-10-11Cherry-pick LLVM 187787 to prevent tail calls on x86-32 when not appropriate.Jan Voung
See: http://llvm.org/viewvc/llvm-project?view=revision&revision=187787 The newer version of newlib tickles this x86-32 bug when building the exception handling tests, which don't strip the "tail" attribute. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3702 Waiting on trybots, but it seems to have fixed the minimal reproducer I have: http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_64/builds/922 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_32/builds/870 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-mac-pnacl-x86_32/builds/875 R=jfb@chromium.org Review URL: https://codereview.chromium.org/26538008
2013-07-24Hide the x86-64 sandbox base address.Jim Stichnoth
Prevent sandbox addresses from being written to the stack. This covers the following cases: 1. Function calls manually push a masked return address and jump to the target, rather than using the call instruction. 2. When the function prolog chooses to use a frame pointer (rbp), it saves a masked version of the old rbp. 3. Indirect branches (jumps, calls, and returns) uniformly use r11 to construct the 64-bit target address. 4. Register r11 is marked as reserved (similar to r15) so that the register allocator won't inadvertently spill a code address to the stack. These transformations can be disabled for performance testing with the flag "-sfi-hide-sandbox-base=false". BUG= https://code.google.com/p/nativeclient/issues/detail?id=1235 R=eliben@chromium.org, mseaborn@chromium.org Review URL: https://codereview.chromium.org/19505003
2013-07-18Merge remote-tracking branch 'origin/master'Eli Bendersky
2013-07-18Correctly adjust LOCALMOD for x64 frame register computation.Eli Bendersky
2013-07-17Disallow a global address in the x86-64 displacement field.Jim Stichnoth
This applies only to %r15 sandboxed memory references. The problem is that if the index register is negative, the sandboxing operation will cause the index to become a large positive 32-bit value, which combined with the displacement, will overflow and try to reference memory outside the sandbox. This situation may legitimately occur if the compiler happens to construct a (constant) interior pointer to the middle of the global struct/array, and then dereferences it with a variable offset. After this fix, pnacl/scripts/testsuite_known_failures_pnacl.txt can be updated to remove the "aha x86-64" known failure. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3517 R=eliben@chromium.org Review URL: https://codereview.chromium.org/17987002
2013-07-16More tests passEli Bendersky
2013-07-16Make it compileEli Bendersky
2013-07-15Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'Eli Bendersky
Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp
2013-07-09PNaCl: Fix negative relocation addends on x86-32Mark Seaborn
Disable an assertion. This assertion made the behaviour on x86-32 inconsistent with x86-64 and ARM. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3548 TEST=*.ll tests + PNaCl toolchain trybots Review URL: https://codereview.chromium.org/18261008
2013-06-24Merge r179774: Allow misaligned stores in x86 fast-isel.Mark Seaborn
This change will fix the regression in -O0 translation time caused by putting "align 1" on integer loads and stores, which was causing FastISel to fall back to SelectionDAG more often. > In X86FastISel::X86SelectStore(), improperly aligned stores are > rejected and handled by the DAG-based ISel. However, > X86FastISel::X86SelectLoad() makes no such requirement. There > doesn't appear to be an x86 architectural correctness issue with > allowing potentially unaligned store instructions. This patch > removes this restriction. > > Patch by Jim Stichnot. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3445 TEST=PNaCl toolchain trybots Review URL: https://codereview.chromium.org/17575003
2013-06-19Fix an x86-64 fast-isel address calculation overflow.Jim Stichnoth
Disallow large displacements in NaCl addressing modes, by rejecting the fast-isel selection and using the logic in the DAG-based isel. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3502 R=dschuff@chromium.org Review URL: https://codereview.chromium.org/16959013
2013-06-13Fix PrologEpilogInserter to save and restore all callee saved registersDerek Schuff
if the function calls _builtin_unwind_init() Also fix the list of callee-saved registers returned by X86RegisterInfo::getCalleeSavedRegisters BUG= https://code.google.com/p/nativeclient/issues/detail?id=3486 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/16987002
2013-05-22Merging r182486:Bill Wendling
------------------------------------------------------------------------ r182486 | d0k | 2013-05-22 10:01:12 -0700 (Wed, 22 May 2013) | 3 lines X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned. Take #2 on fixing PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182364:Bill Wendling
------------------------------------------------------------------------ r182364 | d0k | 2013-05-21 02:58:54 -0700 (Tue, 21 May 2013) | 4 lines X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type. Otherwise we'll get a mix of signed and unsigned compares. Fixes PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Re-allow an x86-32 fast-isel optimization for NaCl / use shorter insts.Jan Voung
There was an old fix for r+r based memory references on x86-64 that checked for isTargetNaCl() instead of isTargetNaCl64(). This disabled some r+r for 32-bit. However, fast isel only sets up r+r with geps, and we don't have geps in the stable ABI. We could potentially add some similar pattern matching in the future... The problem we *do* see with the current bitcode, is that this change also made it preferred to use an index register instead of a base register. This made the memory references on x86-32 look like: cmpl ..., (,%eax,1) instead of cmpl ..., (%eax) So we had longer instructions. Total zipped nexe sizes: 5.73MB (old) vs 5.59 MB (new) (2.5%) Total not zipped: 17.28MB vs 16.28 MB (6%) runtime diffs (min of 5 runs) * eon 4.94 (old) vs 4.72 (new) (~4%) * mesa 21.64 vs 21.08 * mcf 5.76 vs 5.60 * vortex 4.21 vs 4.05 * perlbmk 27.62 vs 26.55 (the rest were under 2% better) BUG=https://code.google.com/p/nativeclient/issues/detail?id=3359 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/15047013
2013-05-16Merging r181529:Bill Wendling
------------------------------------------------------------------------ r181529 | void | 2013-05-09 11:21:45 -0700 (Thu, 09 May 2013) | 8 lines Simplify the code a bit. The compact unwind registers were defined in two different places. It's better just to place them in the function that uses them and specify that this is a 64-bit or 32-bit machine. No functionality change. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181540:Bill Wendling
------------------------------------------------------------------------ r181540 | void | 2013-05-09 13:10:38 -0700 (Thu, 09 May 2013) | 11 lines Generate a compact unwind encoding in the face of a stack alignment push. We generate a `push' of a random register (%rax) if the stack needs to be aligned by the size of that register. However, this could mess up compact unwind generation. In particular, we want to still generate compact unwind in the presence of this monstrosity. Check if the push of of the %rax/%eax register. If it is and it's marked with the `FrameSetup' flag, then we can generate a compact unwind encoding for the function only if the push is the last FrameSetup instruction. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181955 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10LLVM: Add ELF Note section to NaCl object files identifying them as such to goldDerek Schuff
This is needed to switch the native linker to one based on upstream binutils 2.23 R=mseaborn@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=2971 also related to bug https://code.google.com/p/nativeclient/issues/detail?id=3424 Review URL: https://codereview.chromium.org/15067009
2013-05-08Merging r181313:Bill Wendling
------------------------------------------------------------------------ r181313 | mkuper | 2013-05-07 07:05:33 -0700 (Tue, 07 May 2013) | 1 line Re-enable AVX detection on x64 platforms. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05Remove a recently redundant transform from X86ISelLowering.David Majnemer
X86ISelLowering has support to treat: (icmp ne (and (xor %flags, -1), (shl 1, flag)), 0) as if it were actually: (icmp eq (and %flags, (shl 1, flag)), 0) However, r179386 has code at the InstCombine level to handle this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05Add ArrayRef constructor from None, and do the cleanups that this ↵Dmitri Gribenko
constructor enables Patch by Robert Wilhelm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04whitespaceNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04Fix an odd comment.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03X86: Add target description for btver2; make autodetection logic aware of AVX.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03Unbreaking the non-x86 build bots by protecting the AVX test code properly.Aaron Ballman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03Correctly testing for AVX support in x86 based off code from Hosts.cpp.Aaron Ballman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180991 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03In MC asm parsing, account for the possibility of whitespace withinJohn McCall
the "identifier" parsed by the frontend callback by skipping forward until we've consumed a token that ends at the point dictated by the callback. In addition, inform the callback when it's parsing an unevaluated operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one (e.g. mov eax, [A::x]). This commit depends on a clang commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180978 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-0280-col fixup.Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180915 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02Avoid duplicating logic on frame register selecting when lowering eh_returnMichael Liao
No functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180914 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02Avoid duplicating logic on frame register selecting when lowering frameaddrMichael Liao
No functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180912 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01Put VMOVPQIto64rr in the VRPDI class.Rafael Espindola
Patch by Joshua Magee. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26X86: Now that we have a canonical form for vector integer abs, match it into ↵Benjamin Kramer
pabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Make function documentation conform to llvm standards.Preston Gurd
Expunge all remaining traces and use of live variable information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180577 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd
latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Fix section relocation for SECTIONREL32 with immediate offset.Rafael Espindola
Patch by Kai Nacke. This matches the gnu as output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180568 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22[ms-inline asm] Removed this unnecessary check. In the current implementation,Chad Rosier
Disp will always be one of MCSymbolRefExpr or MCConstantExpr, and never NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180059 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22[ms-inline asm] Add the OpDecl to the InlineAsmIdentifierInfo struct and in turnChad Rosier
the MCParsedAsmOperand. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22Fix unused variable warning.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180044 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22[ms-inline asm] Remove the identifier parsing logic from the AsmParser. This isChad Rosier
now taken care of by the frontend, which allows us to parse arbitrary C/C++ variables. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180037 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22[ms-inline asm] Refactor/clean up the SemaLookup interface. No functionalChad Rosier
change indended. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180028 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20Remove unused ShouldFoldAtomicFences flag.Tim Northover
I think it's almost impossible to fold atomic fences profitably under LLVM/C++11 semantics. As a result, this is now unused and just cluttering up the target interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'mEli Bendersky
trying to move as much FastISel logic as possible out of the main path in SelectionDAGISel - intermixing them just adds confusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179902 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ArrayRefize getMachineNode(). No functionality change.Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Make code layout more canonical with iniline asm handled last.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179875 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Refactor the parsing of identifiers. No functional changeChad Rosier
indended. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Remove these asserts. C++ variables that use namespaceChad Rosier
qualifiers don't necessarily begin with an identifier (e.g., ::foo::bar). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Move this variable into the scope in which it is used.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Make this a hard error.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Cleanup the dot operator implementation.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179856 91177308-0d34-0410-b5e6-96231b3b80d8
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