diff options
| author | Mark Seaborn <mseaborn@chromium.org> | 2013-06-24 09:18:55 -0700 |
|---|---|---|
| committer | Mark Seaborn <mseaborn@chromium.org> | 2013-06-24 09:18:55 -0700 |
| commit | 41dd5ede22556305aed7ea2184a2905f187db78c (patch) | |
| tree | f554bb44a06adfb2cfc8428814d75183e69c399d /lib/Target/X86 | |
| parent | ae9f7fcc65aed800db82aaa55e5e72322f20af02 (diff) | |
Merge r179774: Allow misaligned stores in x86 fast-isel.
This change will fix the regression in -O0 translation time caused by
putting "align 1" on integer loads and stores, which was causing
FastISel to fall back to SelectionDAG more often.
> In X86FastISel::X86SelectStore(), improperly aligned stores are
> rejected and handled by the DAG-based ISel. However,
> X86FastISel::X86SelectLoad() makes no such requirement. There
> doesn't appear to be an x86 architectural correctness issue with
> allowing potentially unaligned store instructions. This patch
> removes this restriction.
>
> Patch by Jim Stichnot.
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3445
TEST=PNaCl toolchain trybots
Review URL: https://codereview.chromium.org/17575003
Diffstat (limited to 'lib/Target/X86')
| -rw-r--r-- | lib/Target/X86/X86FastISel.cpp | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index a4d6df8fe1..ba655e9875 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -815,11 +815,6 @@ bool X86FastISel::X86SelectStore(const Instruction *I) { if (S->isAtomic()) return false; - unsigned SABIAlignment = - TD.getABITypeAlignment(S->getValueOperand()->getType()); - if (S->getAlignment() != 0 && S->getAlignment() < SABIAlignment) - return false; - MVT VT; if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) return false; |