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2013-07-08R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst regTom Stellard
Patch by: Vincent Lejeune https://bugs.freedesktop.org/show_bug.cgi?id=64877 NOTE: This is a candidate for the 3.3 branch. Merged from r182600 Author: Tom Stellard <thomas.stellard@amd.com> Date: Thu May 23 18:26:42 2013 +0000 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@185868 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04Merging r183108:Bill Wendling
------------------------------------------------------------------------ r183108 | vljn | 2013-06-03 08:44:42 -0700 (Mon, 03 Jun 2013) | 1 line R600: CALL_FS consumes a stack size entry ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@183181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29Merging r182585:Bill Wendling
------------------------------------------------------------------------ r182585 | aaronballman | 2013-05-23 07:55:00 -0700 (Thu, 23 May 2013) | 1 line Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182112:Bill Wendling
------------------------------------------------------------------------ r182112 | tstellar | 2013-05-17 08:23:12 -0700 (Fri, 17 May 2013) | 1 line R600: Pass MCSubtargetInfo reference to R600CodeEmitter ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Merging r182113:Bill Wendling
------------------------------------------------------------------------ r182113 | tstellar | 2013-05-17 08:23:21 -0700 (Fri, 17 May 2013) | 9 lines R600: Fix encoding for R600 family GPUs Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64193 https://bugs.freedesktop.org/show_bug.cgi?id=64257 https://bugs.freedesktop.org/show_bug.cgi?id=64320 NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Merging r181706:Bill Wendling
------------------------------------------------------------------------ r181706 | rafael | 2013-05-13 07:34:48 -0700 (Mon, 13 May 2013) | 1 line Remove unused fields and arguments. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181580:Bill Wendling
------------------------------------------------------------------------ r181580 | tstellar | 2013-05-09 19:09:45 -0700 (Thu, 09 May 2013) | 10 lines R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181954 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181579:Bill Wendling
------------------------------------------------------------------------ r181579 | tstellar | 2013-05-09 19:09:39 -0700 (Thu, 09 May 2013) | 8 lines R600: Expand SUB for v2i32/v4i32 Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181578:Bill Wendling
------------------------------------------------------------------------ r181578 | tstellar | 2013-05-09 19:09:34 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand MUL for v4i32/v2i32 Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181952 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181577:Bill Wendling
------------------------------------------------------------------------ r181577 | tstellar | 2013-05-09 19:09:29 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand SRA for v4i32/v2i32 v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181951 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181576:Bill Wendling
------------------------------------------------------------------------ r181576 | tstellar | 2013-05-09 19:09:24 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand vselect for v4i32 and v2i32 v2: Add vselect v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181950 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181792:Bill Wendling
------------------------------------------------------------------------ r181792 | tstellar | 2013-05-14 07:42:56 -0700 (Tue, 14 May 2013) | 8 lines R600/SI: Add processor type for Hainan asic Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181949 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcodeTom Stellard
Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemaskTom Stellard
Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600/SI: Add intrinsic for texture image loadingTom Stellard
Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600/SI: Add pattern for uint_to_fpTom Stellard
Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600/SI: Add patterns for integer maxima / minimaTom Stellard
Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600/SI: Add pattern for AMDGPU.trunc intrinsicTom Stellard
Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Remove dead code from the CodeEmitter v2Tom Stellard
v2: - Replace switch statement with TSFlags query Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Emit config values in register / value pairsTom Stellard
Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Stop emitting the instruction type byte before each instructionTom Stellard
Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Emit ISA for CALL_FS_* instructionsTom Stellard
Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03R600: Expand vector or, shl, srl, and xor nodesTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03R600: BFI_INT is a vector-only instructionTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03R600: Add pattern for SHA-256 Ma functionTom Stellard
This can be optimized using the BFI_INT instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03R600: Clean up comments in Processors.tdTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02R600: Signed literals are 64bits wideVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180960 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02R600: Improve asmPrint of ALU clauseVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180957 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02R600: Prettier asmPrint of AluVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02R600: Use new tablegen syntax for patternsTom Stellard
All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180922 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02R600/SI: remove nonsense select patternTom Stellard
Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180921 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Always use texture cache for compute shadersVincent Lejeune
This will improve the performance of memory reads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180762 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: use native for aluVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Packetize instructionsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chipsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Add a Bank Swizzle operandVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Take inner dependency into tex/vtx clausesVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Turn TEX/VTX into native instructionsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Add some new processor variantsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Clean up instruction class definitionsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180752 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: config section now reports use of killgtVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29R600: Use correct CF_END instruction on Northern Island GPUsTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29R600: Fix encoding of CF_END_{EG, R600} instructionsTom Stellard
The EOP bit was not being encoded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTETom Stellard
We need to intialize this to something and since clang does not set the shader type attribute and clang is used only for compute shaders, initializing it to COMPUTE seems like the best choice. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24R600: Initialize BooleanVectorContentsTom Stellard
Fixes test/CodeGen/R600/setcc.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard
The libelf implementation that is distributed here: http://www.mr511.de/software/english.html will not parse sections that are marked SHT_NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23R600: Add CF_ENDVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180123 91177308-0d34-0410-b5e6-96231b3b80d8
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