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AgeCommit message (Expand)Author
2013-07-08R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst regTom Stellard
2013-06-04Merging r183108:Bill Wendling
2013-05-29Merging r182585:Bill Wendling
2013-05-21Merging r182112:Bill Wendling
2013-05-17Merging r182113:Bill Wendling
2013-05-17Merging r181706:Bill Wendling
2013-05-16Merging r181580:Bill Wendling
2013-05-16Merging r181579:Bill Wendling
2013-05-16Merging r181578:Bill Wendling
2013-05-16Merging r181577:Bill Wendling
2013-05-16Merging r181576:Bill Wendling
2013-05-16Merging r181792:Bill Wendling
2013-05-06R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcodeTom Stellard
2013-05-06R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemaskTom Stellard
2013-05-06R600/SI: Add intrinsic for texture image loadingTom Stellard
2013-05-06R600/SI: Add pattern for uint_to_fpTom Stellard
2013-05-06R600/SI: Add patterns for integer maxima / minimaTom Stellard
2013-05-06R600/SI: Add pattern for AMDGPU.trunc intrinsicTom Stellard
2013-05-06R600: Remove dead code from the CodeEmitter v2Tom Stellard
2013-05-06R600: Emit config values in register / value pairsTom Stellard
2013-05-06R600: Stop emitting the instruction type byte before each instructionTom Stellard
2013-05-06R600: Emit ISA for CALL_FS_* instructionsTom Stellard
2013-05-03R600: Expand vector or, shl, srl, and xor nodesTom Stellard
2013-05-03R600: BFI_INT is a vector-only instructionTom Stellard
2013-05-03R600: Add pattern for SHA-256 Ma functionTom Stellard
2013-05-03R600: Clean up comments in Processors.tdTom Stellard
2013-05-02R600: Signed literals are 64bits wideVincent Lejeune
2013-05-02R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune
2013-05-02R600: Improve asmPrint of ALU clauseVincent Lejeune
2013-05-02R600: Prettier asmPrint of AluVincent Lejeune
2013-05-02R600: Use new tablegen syntax for patternsTom Stellard
2013-05-02R600/SI: remove nonsense select patternTom Stellard
2013-04-30R600: Always use texture cache for compute shadersVincent Lejeune
2013-04-30R600: use native for aluVincent Lejeune
2013-04-30R600: Packetize instructionsVincent Lejeune
2013-04-30R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chipsVincent Lejeune
2013-04-30R600: Add a Bank Swizzle operandVincent Lejeune
2013-04-30R600: Take inner dependency into tex/vtx clausesVincent Lejeune
2013-04-30R600: Turn TEX/VTX into native instructionsVincent Lejeune
2013-04-30R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune
2013-04-30R600: Add some new processor variantsVincent Lejeune
2013-04-30R600: Clean up instruction class definitionsVincent Lejeune
2013-04-30R600: config section now reports use of killgtVincent Lejeune
2013-04-29R600: Use correct CF_END instruction on Northern Island GPUsTom Stellard
2013-04-29R600: Fix encoding of CF_END_{EG, R600} instructionsTom Stellard
2013-04-26R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTETom Stellard
2013-04-24R600: Initialize BooleanVectorContentsTom Stellard
2013-04-24R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard
2013-04-23R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune
2013-04-23R600: Add CF_ENDVincent Lejeune
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