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AgeCommit message (Expand)Author
2011-08-11Tighten operand decoding of addrmode2 instruction. The offset register canno...Owen Anderson
2011-08-11Correct immediate range for shifter operands. Patch by James Molloy, with ad...Owen Anderson
2011-08-11Improve error checking in the new ARM disassembler. Patch by James Molloy.Owen Anderson
2011-08-11ARM push of a single register encodes as pre-indexed STR.Jim Grosbach
2011-08-11ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach
2011-08-10ARM LDRT assembly parsing and encoding.Jim Grosbach
2011-08-10Tidy up. 80 columns.Jim Grosbach
2011-08-10ARM LDRH(immediate) assembly parsing and encoding support.Jim Grosbach
2011-08-10ARM LDRD(register) assembly parsing and encoding.Jim Grosbach
2011-08-10Fix typo. Not quite sure how that slipped in there.Jim Grosbach
2011-08-10ARM LDRD(immediate) assembly parsing and encoding support.Jim Grosbach
2011-08-10Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson
2011-08-10Tabs --> spaces.Owen Anderson
2011-08-10Cleanups based on Nick Lewycky's feedback.Owen Anderson
2011-08-10Rewrite some ARM InstrInfo functions to be most accepting of arbitrary regist...Owen Anderson
2011-08-10Add support for the R and Q constraints.Rafael Espindola
2011-08-10Push GPRnopc through a large number of instruction definitions to tighten ope...Owen Anderson
2011-08-09Promote VMOVS to VMOVD when possible.Jakob Stoklund Olesen
2011-08-09Tighten operand checking of register-shifted-register operands.Owen Anderson
2011-08-09Tighten operand checking on memory barrier instructions.Owen Anderson
2011-08-09Tighten operand checking on CPS instructions.Owen Anderson
2011-08-09Create a new register class for the set of all GPRs except the PC. Use it to...Owen Anderson
2011-08-09ARM Disassembler: sign extend branch immediates.Benjamin Kramer
2011-08-09Silence an false-positive warning.Owen Anderson
2011-08-09Don't generate the old-style disassembler in CMake builds either.Owen Anderson
2011-08-09The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction...Benjamin Kramer
2011-08-09Don't continue generating the old-style decoder file.Owen Anderson
2011-08-09ARM fix typo in pre-indexed store lowering.Jim Grosbach
2011-08-09Attempt to fix CMake build.Owen Anderson
2011-08-09Tighten Thumb1 branch predicate decoding.Owen Anderson
2011-08-09Replace the existing ARM disassembler with a new one based on the FixedLenDec...Owen Anderson
2011-08-09Emitting ARM build attributes and values as ULEB, rather than char.Renato Golin
2011-08-08ARM parsing and encoding for LDRBT instruction.Jim Grosbach
2011-08-08Thumb1 BL instructions encoding 22 bits of displacement, not 21.Owen Anderson
2011-08-08Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.Jakob Stoklund Olesen
2011-08-08ARM load/store label parsing.Jim Grosbach
2011-08-08Fix encodings for Thumb ASR and LSR immediate operands. They encode the rang...Owen Anderson
2011-08-08Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly...Eli Friedman
2011-08-08Add MCInstrAnalysis class. This allows the targets to specify own versions of...Benjamin Kramer
2011-08-05ARM load instruction shifted register index operands.Jim Grosbach
2011-08-05ARM indexed load assembly parsing and encoding.Jim Grosbach
2011-08-05ARM refactor indexed store instructions.Jim Grosbach
2011-08-05ARM simplify the postidx_reg operand encoding.Jim Grosbach
2011-08-05ARM use a dedicated printer for postidx_reg operands.Jim Grosbach
2011-08-05Add missing register constraint for some VLD3/VLD4 pseudo instructions.Bob Wilson
2011-08-04Fix broken encodings for the Thumb2 LDRD/STRD instructions.Owen Anderson
2011-08-04ARM assembly parsing and encoding for LDR instructions.Jim Grosbach
2011-08-04LDCL_POST and STCL_POST need one's-complement offsets, rather than two's comp...Owen Anderson
2011-08-03ARM refactoring assembly parsing of memory address operands.Jim Grosbach
2011-08-03Fix broken encoding of tCBNZ.Owen Anderson
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