aboutsummaryrefslogtreecommitdiff
path: root/lib/Target
AgeCommit message (Expand)Author
2012-12-19LLVM sdisel normalize bit extraction of the form:Evan Cheng
2012-12-19Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky
2012-12-19Transform (x&C)>V into (x&C)!=0 where possiblePaul Redmond
2012-12-19PowerPC: Expand VSELECT nodes.Benjamin Kramer
2012-12-19Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund
2012-12-19Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund
2012-12-19Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund
2012-12-19X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses]NAKAMURA Takumi
2012-12-19Optimized load + SIGN_EXTEND patterns in the X86 backend.Elena Demikhovsky
2012-12-19Rename the 'Attributes' class to 'Attribute'. It's going to represent a singl...Bill Wendling
2012-12-19Add some missing Defs and Uses.Reed Kotler
2012-12-18Reverse order of checking SSE level when calculating compare cost, so we checkJakub Staszak
2012-12-18Disable ARM partial flag dependency optimization at -OzQuentin Colombet
2012-12-18Get rid of the pesky -Woverloaded-virtual warning. No change in functionality.Eli Bendersky
2012-12-18Repair bundles that were broken by removing and reinserting the firstJakob Stoklund Olesen
2012-12-18Extract a method, no functional change intended.Jakob Stoklund Olesen
2012-12-17[arm fast-isel] Minor cleanup. No functional change intended.Chad Rosier
2012-12-17[arm fast-isel] Fast-isel only handles simple VTs, so make sure the necessaryChad Rosier
2012-12-17Add instruction encodings / disassembly support for l2r instructions.Richard Osborne
2012-12-17R600: enable S_*N2_* instructionsTom Stellard
2012-12-17R600: BB operand support for SITom Stellard
2012-12-17R600: remove nonsense setPrefLoopAlignmentTom Stellard
2012-12-17Revert/correct some FastISel changes in r170104 (EVT->MVT forPatrik Hagglund
2012-12-17Add instruction encodings for PEEK and ENDIN.Richard Osborne
2012-12-17Fix parameter name in prototypes in XCoreDisassembler.Richard Osborne
2012-12-17Add instruction encodings / disassembly support for rus instructions.Richard Osborne
2012-12-17Add instruction encodings for ZEXT and SEXT.Richard Osborne
2012-12-17Add instruction encodings / disassembly support for 2r instructions.Richard Osborne
2012-12-17Add instruction encodings / disassembly support for 0r instructions.Richard Osborne
2012-12-17Simplify assertion in XCoreInstPrinter.Richard Osborne
2012-12-17Update comments to match recommended doxygen style.Richard Osborne
2012-12-17Remove unnecessary include.Richard Osborne
2012-12-17Remove EFLAGS from the BLSI/BLSMSK/BLSR patterns. The nodes created by DAG co...Craig Topper
2012-12-17Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also add...Craig Topper
2012-12-17Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and...Craig Topper
2012-12-17Remove store forms of DEC/INC from isDefConvertible. Since they are stores th...Craig Topper
2012-12-16Add instruction encodings and disassembly for 1r instructions.Richard Osborne
2012-12-16Add XCore disassembler.Richard Osborne
2012-12-16Remove invalid instruction encodings.Richard Osborne
2012-12-16Mark anything deriving from PseudoInstXCore as a pseudo instruction.Richard Osborne
2012-12-16Set instruction size correctly in XCoreInstrFormats.tdRichard Osborne
2012-12-16Change XCoreAsmPrinter to lower MachineInstrs to MCInsts before emission.Richard Osborne
2012-12-16Replace ${:comment} with the comment symbol.Richard Osborne
2012-12-16This patch is needed to make c++ exceptions work for mips16.Reed Kotler
2012-12-15X86: Add a couple of target-specific dag combines that turn VSELECTS into psu...Benjamin Kramer
2012-12-15Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth
2012-12-15This code implements most of mips16 hardfloat as it is done by gcc.Reed Kotler
2012-12-14FastIsel: Get PIC-style GV loads for NaCl64 even w/out 64-bit pointers.Jan Voung
2012-12-14Make sure the alternate PC+imm syntax of LDR instruction with a smallKevin Enderby
2012-12-14TypeLegalizer: Do not generate target specific nodes with illegal types, beca...Nadav Rotem
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2026-01-20 16:41:17 +0000