| Age | Commit message (Expand) | Author |
|---|
| 2010-08-27 | Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like | Bob Wilson |
| 2010-08-18 | Minor simplification. Gets rid of a needless temporary. | Bill Wendling |
| 2010-08-11 | Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds. | Bill Wendling |
| 2010-08-10 | Turn optimize compares back on with fix. We needed to test that a machine op was | Bill Wendling |
| 2010-08-08 | Use the "isCompare" machine instruction attribute instead of calling the | Bill Wendling |
| 2010-08-06 | Add the Optimize Compares pass (disabled by default). | Bill Wendling |
| 2010-07-30 | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach |
| 2010-07-20 | prune #includes a little. | Chris Lattner |
| 2010-07-16 | Remove the isMoveInstr() hook. | Jakob Stoklund Olesen |
| 2010-07-16 | Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and | Bill Wendling |
| 2010-07-11 | RISC architectures get their memory operand folding for free. | Jakob Stoklund Olesen |
| 2010-07-11 | Replace copyRegToReg with copyPhysReg for ARM. | Jakob Stoklund Olesen |
| 2010-07-09 | Automatically fold COPY instructions into stack load/store. | Jakob Stoklund Olesen |
| 2010-07-08 | For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the | Bob Wilson |
| 2010-07-06 | Represent NEON load/store alignments in bytes, not bits. | Bob Wilson |
| 2010-07-06 | Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion | Rafael Espindola |
| 2010-06-29 | Add a VT argument to getMinimalPhysRegClass and replace the copy related uses | Rafael Espindola |
| 2010-06-25 | Change if-conversion block size limit checks to add some flexibility. | Evan Cheng |
| 2010-06-25 | IT instructions are considered to be scheduling hazards, but are scheduled | Jim Grosbach |
| 2010-06-23 | We are missing opportunites to use ldm. Take code like this: | Bill Wendling |
| 2010-06-18 | Allow ARM if-converter to be run after post allocation scheduling. | Evan Cheng |
| 2010-06-18 | Rewrite chained if's as switches and replace assertions with llvm_unreachable | Bob Wilson |
| 2010-06-17 | Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This | Stuart Hastings |
| 2010-06-15 | Next round of tail call changes. Register used in a tail | Dale Johannesen |
| 2010-06-15 | VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable. | Bob Wilson |
| 2010-06-08 | Reapply r105521, this time appending "LLU" to 64 bit | Bruno Cardoso Lopes |
| 2010-06-05 | revert r105521, which is breaking the buildbots with stuff like this: | Chris Lattner |
| 2010-06-05 | Initial AVX support for some instructions. No patterns matched | Bruno Cardoso Lopes |
| 2010-06-02 | Slightly change the meaning of the reMaterialize target hook when the original | Jakob Stoklund Olesen |
| 2010-06-02 | Clean up 80 column violations. No functional change. | Jim Grosbach |
| 2010-06-02 | Remove the TargetRegisterClass member from CalleeSavedInfo | Rafael Espindola |
| 2010-05-27 | Update the saved stack pointer in the sjlj function context following either | Jim Grosbach |
| 2010-05-24 | Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums | Jakob Stoklund Olesen |
| 2010-05-22 | Implement @llvm.returnaddress. rdar://8015977. | Evan Cheng |
| 2010-05-22 | Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. | Jim Grosbach |
| 2010-05-14 | Added a QQQQ register file to model 4-consecutive Q registers. | Evan Cheng |
| 2010-05-13 | Bring back VLD1q and VST1q and use them for reloading / spilling Q registers.... | Evan Cheng |
| 2010-05-07 | Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack s... | Evan Cheng |
| 2010-05-07 | Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VL... | Evan Cheng |
| 2010-05-07 | Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q... | Evan Cheng |
| 2010-05-06 | Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it | Dan Gohman |
| 2010-05-06 | Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. | Evan Cheng |
| 2010-05-06 | Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coa... | Evan Cheng |
| 2010-05-06 | Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll. | Dan Gohman |
| 2010-05-06 | Revert r103156 since it was breaking the build bots. | Eric Christopher |
| 2010-05-06 | Fix an obvious bug in isMoveInstr. It needs to return sub-register indices. | Evan Cheng |
| 2010-05-06 | Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registe... | Evan Cheng |
| 2010-05-06 | Cosmetic changes. | Evan Cheng |
| 2010-05-06 | storeRegToStackSlot has forgotten about QPR_8 register class. | Evan Cheng |
| 2010-04-29 | Frame index can be negative. | Evan Cheng |
