emscripten-fastcomp - LLVM with the emscripten fastcomp javascript backend

Age	Commit message (Expand)	Author
2012-05-30	Teach taildup to update livein set. rdar://11538365	Evan Cheng
2012-05-30	If-converter models predicated defs as read + write. The read should be marke...	Evan Cheng
2012-05-30	Add an insertPass API to TargetPassConfig. <rdar://problem/11498613>	Bob Wilson
2012-05-29	Optional def can be either a def or a use (of reg0).	Evan Cheng
2012-05-29	Clear the entering, exiting and internal ranges of a bundle before collecting	Lang Hames
2012-05-29	ConstantRangesSet renamed to IntegersSubset. CRSBuilder renamed to IntegersSu...	Stepan Dyatkovskiy
2012-05-28	Add llvm.fabs intrinsic.	Peter Collingbourne
2012-05-28	PR1255: Case Ranges	Stepan Dyatkovskiy
2012-05-27	Have getOrCreateSubprogramDIE store the DIE for a subprogram	Peter Collingbourne
2012-05-27	Missed parens.	Benjamin Kramer
2012-05-27	r157525 didn't work, just disable iterator checking.	Benjamin Kramer
2012-05-27	SDAGBuilder: Avoid iterator invalidation harder.	Benjamin Kramer
2012-05-26	SDAGBuilder: Don't create an invalid iterator when there is only one switch c...	Benjamin Kramer
2012-05-26	SelectionDAGBuilder: When emitting small compare chains for switches order th...	Benjamin Kramer
2012-05-26	ScoreboardHazardRecognizer: Remove dead conditional in debug code.	Benjamin Kramer
2012-05-25	Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall	Justin Holewinski
2012-05-25	misched: trace formatting	Andrew Trick
2012-05-25	Simplify code for calling a function where CanLowerReturn fails, fixing a sma...	Eli Friedman
2012-05-24	Silence unused variable warnings from when assertions are disabled.	Kaelyn Uhrain
2012-05-24	misched: Use the same scheduling heuristics with -misched-topdown/bottomup.	Andrew Trick
2012-05-24	misched: Trace regpressure.	Andrew Trick
2012-05-24	misched: Give each ReadyQ a unique ID	Andrew Trick
2012-05-24	misched: Added ScoreboardHazardRecognizer.	Andrew Trick
2012-05-24	misched: Release bottom roots in reverse order.	Andrew Trick
2012-05-24	misched: rename ReadyQ class	Andrew Trick
2012-05-24	misched: copy comments so compareRPDelta is readable by itself.	Andrew Trick
2012-05-24	regpressure: Added RegisterPressure::dump	Andrew Trick
2012-05-24	regpressure: physreg livein/out fix	Andrew Trick
2012-05-24	Mark some static arrays as const.	Craig Topper
2012-05-23	Add a last resort tryInstructionSplit() to RAGreedy.	Jakob Stoklund Olesen
2012-05-23	Forgot to reverse conditional.	Bill Wendling
2012-05-23	Reduce indentation by early detection of 'continue'. No functionality change.	Bill Wendling
2012-05-23	Correctly deal with identity copies in RegisterCoalescer.	Jakob Stoklund Olesen
2012-05-23	Small fix for the debug output from PBQP (PR12822).	Patrik Hägglund
2012-05-23	Add support for C++11 enum classes in llvm.	Eric Christopher
2012-05-22	Untabify and 80-col.	Eric Christopher
2012-05-22	Formatting consistency.	Eric Christopher
2012-05-22	Only erase virtregs with no uses left.	Jakob Stoklund Olesen
2012-05-21	Fix use of an unitialized value in the LegalizeOps expansion for ISD::SUB. N...	Owen Anderson
2012-05-21	Typo.	Chad Rosier
2012-05-21	Give a small negative bias to giant edge bundles.	Jakob Stoklund Olesen
2012-05-20	Clear kill flags on the fly when joining intervals.	Jakob Stoklund Olesen
2012-05-20	Constrain regclasses in PeepholeOptimizer.	Jakob Stoklund Olesen
2012-05-20	Constrain register classes in TailDup.	Jakob Stoklund Olesen
2012-05-20	When legalising shifts, do not pre-build a list of operands which	Peter Collingbourne
2012-05-20	Plug a leak when using MCJIT.	Benjamin Kramer
2012-05-20	Use TargetMachine's register info instead of creating a new one and leaking it.	Benjamin Kramer
2012-05-20	Properly constrain register classes for sub-registers.	Jakob Stoklund Olesen
2012-05-20	Properly constrain register classes in 2-addr.	Jakob Stoklund Olesen
2012-05-20	Missed a push_back in r157147.	Jakob Stoklund Olesen