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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-20 06:38:37 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-20 06:38:37 +0000 |
| commit | ee0d5d4398fb855c6674da94d902ef45e944f375 (patch) | |
| tree | 479d41d9f92def17e6b1ebbb8a381183a3181fad /lib/CodeGen | |
| parent | 8e86929e3ce3fe56295d2704b93bf14c709b311a (diff) | |
Properly constrain register classes for sub-registers.
Not all GR64 registers have sub_8bit sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157150 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/FastISel.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index 0c1ac6982d..07687ef8b5 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1345,6 +1345,8 @@ unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); assert(TargetRegisterInfo::isVirtualRegister(Op0) && "Cannot yet extract from physregs"); + const TargetRegisterClass *RC = MRI.getRegClass(Op0); + MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), ResultReg) .addReg(Op0, getKillRegState(Op0IsKill), Idx); |