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path: root/lib/CodeGen/SimpleRegisterCoalescing.cpp
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2009-06-17VNInfo cleanup.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16Rename RemoveCopiesFromValNo to TurnCopiesFromValNoToImpDefs.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73479 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16If a val# is defined by an implicit_def and it is being removed, all of the ↵Evan Cheng
copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15Part 1.Evan Cheng
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng
MachineRegisterInfo. This allows more passes to set them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02Update to in-place spilling framework. Includes live interval scaling and ↵Lang Hames
trivial rewriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72729 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11Fixed PR4090.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71495 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30Join cross class copies using getCommonSubClass()Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70513 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30Add a smarter heuristic to determine when to coalesce a virtual register ↵Evan Cheng
with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead. This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70503 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70309 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28Don't coalesce a physical register with an incompatible virtual register.Jakob Stoklund Olesen
If the physical register does not belong to the virtual register's regclass, don't coalesce. The physical register could be an invalid operand for an instruction using the vreg. The regclass matching is done after determining the actual subregisters being copied. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70298 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27Don't skip the CopyMI when removing kill markers.Owen Anderson
This should have no effect on generated code, but makes the intermediate state of the coalescer more sane. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70238 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23Update comments.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23Fix an obvious type.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69918 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30Fix grammar-o in comment.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68057 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11My last coalescer fix introduced a subtler one. It's aborting a commuting ↵Evan Cheng
optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66715 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11Two coalescer fixes in one.Evan Cheng
1. Use the same value# to represent unknown values being merged into sub-registers. 2. When coalescer commute an instruction and the destination is a physical register, update its sub-registers by merging in the extended ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22If a use operand is marked isKill, don't forget to add kill to its live ↵Evan Cheng
interval as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65279 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09Fix another case ShortenDeadCopySrcLiveRange is shortening too much. No test ↵Evan Cheng
case possible since I don't know what to grep for. :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64125 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-08Fix PR3486. Fix a bug in code that manually patch physical register live ↵Evan Cheng
interval after its sub-register is coalesced with a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64082 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-08Strengthen the previous check.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64076 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-08r64073 commit message is lost. Here it is:Evan Cheng
Right now if the coalesced copy def is dead and its src is a kill, and that there are now other uses within the live range, the coalescer would mark the def of the source register as dead. But it should also check if there are other kills which means the value has other uses not in the live range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64075 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-08git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64073 ↵Evan Cheng
91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05isAsCheapAsMove instructions can have register src operands. Check if they ↵Evan Cheng
are really re-materializable. This fixes sse.expandfft and sse.stepfft. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63890 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05ReMaterializeTrivialDef need to trim the live interval to the last kill if ↵Evan Cheng
the copy kills the source register. This fixes uint64tof64.ll after ARM::MOVi is marked as isAsCheapAsAMove. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63853 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04Skip over zero registers.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63748 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-23Only check if coalescing is worthwhile when the result is targeting a more ↵Evan Cheng
restrictive register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62837 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-23Cross register class coalescing. Not yet enabled.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62832 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-20Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng
sub-register indices as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-20Refactor code. No functionality change.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62573 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-13Use assertions to check for conditions that should never happen.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62178 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-13Un-tabify.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62151 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-13FIX llvm-gcc bootstrap on x86_64 linux. If a virtual register is copied to a ↵Evan Cheng
physical register, it's not necessarily defined by a copy. We have to watch out it doesn't clobber any sub-register that might be live during its live interval. If the live interval crosses a basic block, then it's not safe to check with the less conservative check (by scanning uses and defs) because it's possible a sub-register might be live out of the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62144 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07The coalescer does not coalesce a virtual register to a physical register if ↵Evan Cheng
any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: v1024 = EDI // not killed = = EDI One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead. This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05squash warnings.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61707 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-19Fix PR3149. If an early clobber def is a physical register and it is tied to ↵Evan Cheng
an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this. 172 %ECX<def> = MOV32rr %reg1039<kill> 180 INLINEASM <es:subl $5,$1 sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>, 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0 188 %EAX<def> = MOV32rr %EAX<kill> 196 %ECX<def> = MOV32rr %ECX<kill> 204 %ECX<def> = MOV32rr %ECX<kill> 212 %EAX<def> = MOV32rr %EAX<kill> 220 %EAX<def> = MOV32rr %EAX 228 %reg1039<def> = MOV32rr %ECX<kill> The early clobber operand ties ECX input to the ECX def. The live interval of ECX is represented as this: %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47) The right way to represent this is something like %reg20,inf = [46,47:2)[174,182:1)[181:230:0) 0@174-(182) 1@181-230 @2@46-(47) Of course that won't work since that means overlapping live ranges defined by two val#. The workaround for now is to add a bit to val# which says the val# is redefined by a early clobber def somewhere. This prevents the move at 228 from being optimized away by SimpleRegisterCoalescing::AdjustCopiesBackFrom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61259 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-19Perform this loop only when the -debug flag is specified.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61238 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27Remove val# defined by a remat'ed def that is now dead.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58294 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21When the coalescer is doing rematerializing, have it removeDan Gohman
the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57872 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-13Also update sub-register intervals after a trivial computation is rematt'ed ↵Evan Cheng
for a copy instruction. PR2775. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57458 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-11fix typoChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57388 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-07Add an option to enable StrongPHIElimination, for ease of testing.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57259 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-03Switch the MachineOperand accessors back to the short names likeDan Gohman
isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30Re-apply 56835 along with header file changes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56848 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30Revert commit 56835 since it breaks the build.Duncan Sands
"If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56837 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30If a re-materializable instruction has a register operand, the spiller will ↵Evan Cheng
change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56835 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24Next round of earlyclobber handling. Approach theDale Johannesen
RA problem by expanding the live interval of an earlyclobber def back one slot. Remove overlap-earlyclobber throughout. Remove earlyclobber bits and their handling from live internals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56539 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22Mark several codegen passes as preserving all analysis.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56469 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-20Teach coalescer about earlyclobber bits.Dale Johannesen
Check bits for preferred register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56384 91177308-0d34-0410-b5e6-96231b3b80d8
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