Teach coalescer about earlyclobber bits.

Check bits for preferred register.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56384 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 0 deletions

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 33061890c0..88996575db 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1206,6 +1206,14 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
   DOUT << " and "; DstInt.print(DOUT, tri_);
   DOUT << ": ";
 
+  // If one interval is earlyclobber and the other is overlaps-earlyclobber,
+  // we cannot coalesce them.
+  if ((SrcInt.isEarlyClobber && DstInt.overlapsEarlyClobber) ||
+      (DstInt.isEarlyClobber && SrcInt.overlapsEarlyClobber)) {
+    DOUT << "\t\tCannot join due to earlyclobber.";
+    return false;
+  }
+
   // Check if it is necessary to propagate "isDead" property.
   if (!isExtSubReg && !isInsSubReg) {
     MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
@@ -1366,6 +1374,10 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
   if (TargetRegisterInfo::isVirtualRegister(DstReg))
     RemoveUnnecessaryKills(DstReg, *ResDstInt);
 
+  // Merge the earlyclobber bits.
+  ResDstInt->isEarlyClobber |= ResSrcInt->isEarlyClobber;
+  ResDstInt->overlapsEarlyClobber |= ResSrcInt->overlapsEarlyClobber;
+
   if (isInsSubReg)
     // Avoid:
     // r1024 = op