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path: root/lib/CodeGen/SelectionDAG
AgeCommit message (Expand)Author
2011-07-14Add assertion for the chain value typeNadav Rotem
2011-07-14Don't emit a bit test if there is only one case the test can yield false. A s...Benjamin Kramer
2011-07-14Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-AEric Christopher
2011-07-13Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.Jay Foad
2011-07-08Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich
2011-07-08Apparently we can't expect a BinaryOperator here.Benjamin Kramer
2011-07-08Emit a more efficient magic number multiplication for exact sdivs.Benjamin Kramer
2011-07-07Remove a FIXME. All of the standard ones are in the list.Eric Christopher
2011-07-07Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. TheLang Hames
2011-07-06Grammar and 80-col.Eric Christopher
2011-07-06Introduce "expect" intrinsic instructions.Jakub Staszak
2011-07-01Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng
2011-06-30Remove getRegClassForInlineAsmConstraint and all dependencies.Eric Christopher
2011-06-29Revert r133953 for now.Devang Patel
2011-06-29Revert a part of r126557 which could create unschedulable DAGs.Benjamin Kramer
2011-06-29Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries)...Evan Cheng
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
2011-06-27During bottom up fast-isel, instructions emitted to materalize registers are ...Devang Patel
2011-06-27More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng
2011-06-27The index stored in the RegDefIter is one after the current index. When gett...Owen Anderson
2011-06-27pre-RA-sched: Cleanup register pressure tracking.Andrew Trick
2011-06-27Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen
2011-06-24The scheduler needs to be aware on the existence of untyped nodes when it per...Owen Anderson
2011-06-24Handle debug info for i128 constants.Devang Patel
2011-06-22Replace the existing forms of ConstantArray::get() with a single formJay Foad
2011-06-21Fix some trailing issues from my introduction of MVT::untyped and its use for...Owen Anderson
2011-06-21Teach dag combine to match halfword byteswap patterns.Evan Cheng
2011-06-20Fix PromoteIntRes_TRUNCATE: Add support for cases where theNadav Rotem
2011-06-19Code cleanups: Remove duplicated logic in PromotInteRes_BITCAST, reserve vect...Nadav Rotem
2011-06-19Calls to AssertZext and getZeroExtendInReg must be made using scalar types.Nadav Rotem
2011-06-19When promoting the vector elements in CopyToParts, use vector truncNadav Rotem
2011-06-18Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.Benjamin Kramer
2011-06-18Remove unused but set variables.Benjamin Kramer
2011-06-18Fix UMULO support for 2x register width to allow the fullEric Christopher
2011-06-17Fix comment.Eric Christopher
2011-06-17Lower multiply with overflow checking to __mulo<mode>Eric Christopher
2011-06-16Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen
2011-06-16Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak
2011-06-16Change the REG_SEQUENCE SDNode to take an explict register class ID as its fi...Owen Anderson
2011-06-16Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen
2011-06-16Add a DAGCombine for (ext (binop (load x), cst)).Nick Lewycky
2011-06-15Add a new MVT::untyped. This will be used in future work for modelling ISA f...Owen Anderson
2011-06-15Added -stress-sched flag in the Asserts build.Andrew Trick
2011-06-15getZeroExtendInReg needs to get a scalar typeNadav Rotem
2011-06-15Enable the simplification of truncating-store after fixing the usage ofNadav Rotem
2011-06-14When pattern matching during instruction selection make sure shl x,1 is notChad Rosier
2011-06-14Add a testcase for checking the integer-promotion of many different vectorNadav Rotem
2011-06-14Disable trunc-store simplification on vectors.Nadav Rotem
2011-06-14Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes
2011-06-13Fix a bug in FindMemType. When widening vector loads, use a wider memory typeNadav Rotem
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