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2012-04-11TableGen's regpressure: emit per-registerclass weight limits.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Comment typo fix.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154488 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Added a TargetRegisterInfo interface for accessing register pressure sets.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154375 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Fix a long standing tail call optimization bug. When a libcall is emittedEvan Cheng
legalizer always use the DAG entry node. This is wrong when the libcall is emitted as a tail call since it effectively folds the return node. If the return node's input chain is not the entry (i.e. call, load, or store) use that as the tail call input chain. PR12419 rdar://9770785 rdar://11195178 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-08Teach LLVM about a PIE option which, when enabled on top of PIC, makesChandler Carruth
optimizations which are valid for position independent code being linked into a single executable, but not for such code being linked into a shared library. I discussed the design of this with Eric Christopher, and the decision was to support an optional bit rather than a completely separate relocation model. Fundamentally, this is still PIC relocation, its just that certain optimizations are only valid under a PIC relocation model when the resulting code won't be in a shared library. The simplest path to here is to expose a single bit option in the TargetOptions. If folks have different/better designs, I'm all ears. =] I've included the first optimization based upon this: changing TLS models to the *Exec models when PIE is enabled. This is the LLVM component of PR12380 and is all of the hard work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-08Move the TLSModel information into the TargetMachine rather than hidingChandler Carruth
in TargetLowering. There was already a FIXME about this location being odd. The interface is simplified as a consequence. This will also make it easier to change TLS models when compiling with PIE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04Always compute all the bits in ComputeMaskedBits.Rafael Espindola
This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02Add predicates for checking whether targets have free FNEG and FABS ↵Owen Anderson
operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153901 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-25Prune some includes and forward declarations.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Target override to allow CodeGenPrepare to sink address operands to ↵Pete Cooper
intrinsics in the same way it current does for loads and stores git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152666 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05MCRegisterInfo-ize getMatchingSuperReg.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper
static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store register overlaps to reduce static data.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper
static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper
size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.Jim Grosbach
Allows us to de-virtualize the function and provides access to it in the instruction printer, which is useful for handling composite physical registers (e.g., ARM register lists). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Make TargetRegisterClasses non-virtual by making the only virtual function a ↵Benjamin Kramer
function pointer. This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static initializer and a ton of cruft from the generated code. Shrinks ARMBaseRegisterInfo.o by ~100k. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng
direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar
prediction. ...", it is breaking the Clang build during the Compiler-RT part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng
the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper
to static data that should not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-20Improve generated code for extending loads and some trunc stores on ARM.James Molloy
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Modify the code that emits the module flags to use the new module flags accessorBill Wendling
method. This allows the target lowering code to not have to deal with MDNodes. Also, avoid leaking memory like a sieve by not creating a global variable for the image info section, but just emitting the code directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150624 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Add code to the target lowering object file module to handle module flags.Bill Wendling
The MachO back-end needs to emit the garbage collection flags specified in the module flags. This is a WIP, so the front-end hasn't been modified to emit these flags just yet. Documentation and front-end switching to occur soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150507 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames
consistency with setExceptionPointerRegister(...). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Remove redundant getAnalysis<> calls in GlobalOpt. Add a few Itanium ABI callsNick Lewycky
to TargetLibraryInfo and use one of them in GlobalOpt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Store just the SimpleValueType in the generated VT tables for each register ↵Benjamin Kramer
class, eliminating static ctors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Convert assert(0) to llvm_unreachableCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick
Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick
Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Require non-NULL register masks.Jakob Stoklund Olesen
It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Specify SubRegIndex components on the index itself.Jakob Stoklund Olesen
It is simpler to define a composite index directly: def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>; def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>; Than specifying the composite indices on each register: CompositeIndices = [(ssub_2 dsub_1, ssub_0), (ssub_3 dsub_1, ssub_1)] in ... This also makes it clear that SubRegIndex composition is supposed to be unique. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick
automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Properly emit ctors / dtors with priorities into desired sectionsAnton Korobeynikov
and let linker handle the rest. This finally fixes PR5329 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Add an (interleave A, B, ...) SetTheory operator.Jakob Stoklund Olesen
This will interleave the elements from two or more lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20More dead code removal (using -Wunreachable-code)David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Add a TargetOption for disabling tail calls.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen
When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Add TableGen support for callee saved registers.Jakob Stoklund Olesen
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file. TableGen will use this to create a *_SaveList array suitable for returning from getCalleeSavedRegs() as well as a *_RegMask bit mask suitable for returning from getCallPreservedMask(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Moving options declarations around.Andrew Trick
More short term hackery until we have a way to configure passes that work on LiveIntervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148289 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14Add TRI::getCallPreservedMask() hook.Jakob Stoklund Olesen
The hook returns a bit-mask of call-preserved registers that will eventually replace the current list of implicit defs on call instructions. This will make it possible to support multiple calling conventions without duplicating call instruction descriptors. The call-preserved mask is slightly different from the list returned by the getCalleeSavedRegs() hook, it includes all aliases that are preserved by calls. The hook takes a CallingConv::ID argument instead of a MachineFunction pointer, so it can provide information about calls to extern functions, and even indirect function calls. TRI::getCalleeSavedRegs() returns information about the function currently being compiled. TRI::getCallPreservedMask() returns information about the functions it is calling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148165 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13Added the MachineSchedulerPass skeleton.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Allow targets to select source order pre-RA scheduler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Move Sched::Preference out of TargetMachine.h where it is not referenced.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth
of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove unnecessary default cases in switches that cover all enum values.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel
AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
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